3 Volt Intel StrataFlash

Memory

28F128J3, 28F640J3, 28F320J3 (x8/x16)

Datasheet

Product Features

Capitalizing on Intel's 0.25 and 0.18 micron, two-bit-per-cell technology, the 3 Volt Intel StrataFlash

Memory

(J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in

128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-per-cell storage

technology to the flash market segment. Benefits include: more density in less space, high-speed interface,

lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices.

Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, the J3 device takes

advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components

are ideal for code and data applications where high density and low cost are required. Examples include

networking, telecommunications, digital set top boxes, audio recording, and digital imaging.

By applying FlashFileTM memory family pinouts, J3 memory components allow easy design migrations from

existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash

memory (28F640J5 and 28F320J5) devices.

J3 memory components deliver a new generation of forward-compatible software support. By using the

Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density

upgrades and optimized write capabilities of future Intel StrataFlash

memory devices. Manufactured on Intel

0.18 micron ETOXTM VII (J3C) and 0.25 micron ETOXTM VI (J3A) process technology, the J3 memory device

provides the highest levels of quality and reliability.

Performance

--110/115/120/150 ns Initial Access Speed
--25 ns Asynchronous Page-Mode Reads

--32-Byte Write Buffer

--6.8 µs per Byte Effective

Programming Time

Software

--Program and Erase suspend support
--Flash Data Integrator (FDI), Common

Flash Interface (CFI) Compatible

Security

--128-bit Protection Register

--64-bit Unique Device Identifier
--64-bit User Programmable OTP Cells

--Absolute Protection with V

PEN

= GND

--Individual Block Locking
--Block Erase/Program Lockout during

Power Transitions

Architecture

--Multi-Level Cell Technology: High

Density at Low Cost

--High-Density Symmetrical 128-Kbyte

Blocks
--128 Mbit (128 Blocks)
--

4 Mbit (64 Blocks)

--32 Mbit (32 Blocks)

Quality and Reliability

--Operating Temperature:

-40 °C to +85 °C

--100K Minimum Erase Cycles per Block
--0.18 µm ETOXTM VII Process (J3C)
--0.25 µm ETOXTM VI Process (J3A)

Packaging and Voltage

--56-Lead TSOP Package
--64-Ball Intel

Easy BGA Package

--48-Ball Intel

VF BGA Package (32 and

64 Mbit) (x16 only)

--V

2.7 V 3.6 V

--V

CCQ

= 2.7 V 3.6 V

Order Number: 290667-013

February 2003

Notice: This document contains information on new products in production. The specifications are

subject to change without notice. Verify with your local Intel sales office that you have the latest

datasheet before finalizing a design.

Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 3 Volt Intel StrataFlash® Memory may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

1.0

Introduction....................................................................................................................................7
1.1

Document Purpose ...............................................................................................................7

1.2

Nomenclature .......................................................................................................................7

1.3

Conventions..........................................................................................................................7

2.0

Device Description ........................................................................................................................8
2.1

Product Overview .................................................................................................................8

2.2

Ballout Diagrams ..................................................................................................................9

2.3

Signal Descriptions .............................................................................................................12

2.4

Block Diagram ....................................................................................................................13

2.5

Memory Map.......................................................................................................................14

3.0

Device Operations .......................................................................................................................15
3.1

Bus Operations ...................................................................................................................15
3.1.1

Read Mode ............................................................................................................16

3.1.2

Write ......................................................................................................................16

3.1.3

Output Disable .......................................................................................................16

3.1.4

Standby..................................................................................................................17

3.1.5

Reset/Power-Down ................................................................................................17

3.2

Device Commands .............................................................................................................17

4.0

Read Operations ..........................................................................................................................19
4.1

Read Array..........................................................................................................................19
4.1.1

Asynchronous Page-Mode Read ...........................................................................19

4.2

Read Identifier Codes .........................................................................................................19

4.3

Read Status Register..........................................................................................................20

4.4

Read Query/CFI..................................................................................................................22

5.0

Programming Operations ...........................................................................................................22
5.1

Byte/Word Program ............................................................................................................22

5.2

Write to Buffer.....................................................................................................................22

5.3

Program Suspend ...............................................................................................................23

5.4

Program Resume................................................................................................................24

6.0

Erase Operations.........................................................................................................................24
6.1

Block Erase.........................................................................................................................24

6.2

Block Erase Suspend .........................................................................................................24

6.3

Erase Resume ....................................................................................................................25

7.0

Security Modes ............................................................................................................................26
7.1

Set Block Lock-Bit...............................................................................................................26

7.2

Clear Block Lock-Bits..........................................................................................................26

7.3

Protection Register Program ..............................................................................................27
7.3.1

Reading the Protection Register............................................................................27

7.3.2

Programming the Protection Register....................................................................27

7.3.3

Locking the Protection Register.............................................................................27

7.4

Array Protection ..................................................................................................................30

Contents

Datasheet

8.0

Special Modes.............................................................................................................................. 30
8.1

Set Read Configuration ...................................................................................................... 30
8.1.1

Read Configuration................................................................................................ 30

8.2

STS..................................................................................................................................... 30

9.0

Power and Reset.......................................................................................................................... 32
9.1

Power-Up/Down Characteristics......................................................................................... 32

9.2

Power Supply Decoupling................................................................................................... 32

9.3

Reset Characteristics.......................................................................................................... 32

10.0 Electrical Specifications ............................................................................................................. 33

10.1 Absolute Maximum Ratings ................................................................................................ 33
10.2 Operating Conditions .......................................................................................................... 34
10.3 DC Current Characteristics................................................................................................. 35
10.4 DC Voltage Characteristics................................................................................................. 36

11.0 AC Characteristics ...................................................................................................................... 37

11.1 Read Operations................................................................................................................. 37
11.2 Write Operations................................................................................................................. 39
11.3 Block Erase, Program, and Lock-Bit Configuration Performance....................................... 40
11.4 Reset Operation.................................................................................................................. 42
11.5 AC Test Conditions............................................................................................................. 42
11.6 Capacitance........................................................................................................................ 43

Appendix A Write State Machine (WSM) .............................................................................................44
Appendix B Common Flash Interface..................................................................................................45
Appendix C Flow Charts .......................................................................................................................52
Appendix D Mechanical Information ...................................................................................................61
Appendix E Design Considerations.....................................................................................................64
Appendix F Additional Information......................................................................................................66
Appendix G Ordering Information .......................................................................................................67

Datasheet

Contents

Revision History

Date of

Revision

Version

Description

07/07/99

-001

Original Version

08/03/99

-002

indicated on block diagram

09/07/99

-003

Changed Minimum Block Erase time,I

, I

, Page Mode and Byte Mode

currents. Modified RP# on AC Waveform for Write Operations

12/16/99

-004

Changed Block Erase time and t

AVWH

Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart

03/16/00

-005

Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
Removed V

CCQ1

setting and changed V

CCQ2/3

to V

CCQ1/2

Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed V

of 0.45 V; Removed V

of 2.4 V

Updated I

CCR

Typ values

Added Max lock-bit program and lock times
Added note on max measurements

06/26/00

-006

Updated cover sheet statement of 700 million units to one billion
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7

2/15/01

-007

Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
Changed V

PENLK

Max voltage from 0.8 V to 2.0 V, Section 6.4, DC

Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC CharacteristicsRead-Only Operations

(1,2)

Updated write parameter W13 (t

WHRL

) from 90 ns to 500 ns, Section 6.6, AC

CharacteristicsWrite Operations
Updated Max. Program Suspend Latency W16 (t

WHRH1

) from 30 to 75 µs,

Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance

(1,2,3)

04/13/01

-008

Revised Section 7.0, Ordering Information

Contents

Datasheet

07/27/01

-009

Added Figure 4, 3 Volt Intel StrataFlash

Memory VF BGA Package (32 Mbit)

Added Figure 5, 3 Volt Intel StrataFlash

Memory VF BGA Mechanical

Specifications
Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced t

EHQZ

to 35 ns. Reduced t

WHEH

to 0 ns

Added parameter values for 40 °C operation to Lock-Bit and Suspend Latency
Updated V

LKO

and V

PENLK

to 2.2 V

Removed Note #4, Section 6.4 and Section 6.6
Minor text edits

10/31/01

-010

Added notes under lead descriptions for VF BGA Package
Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics
Added ordering information for VF BGA Package
Minor text edits

03/21/02

-011

Changed datasheet to reflect the best known methods
Updated max value for Clear Block Lock-Bits time
Minor text edits

12/12/02

-012

Added nomenclature for J3C (0.18 µm) devices.

01/24/03

-013

Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128
Mb J3C device. Added "TE" package designator for J3C TSOP package.

Date of

Revision

Version

Description

28F128J3, 28F640J3, 28F320J3

Datasheet

1.0

Introduction

1.1

Document Purpose

This document contains information pertaining to the 3 Volt Intel StrataFlash

Memory device, J3.

The purpose of this document is to facilitate the use of this product and describe the features,
operations, and specifications of this device.

1.2

Nomenclature

AMIN:

AMIN = A0 for x8
AMIN = A1 for x16

AMAX:

32 Mbit

AMAX = A21

64 Mbit

AMAX = A22

128 Mbit

AMAX = A23

Block:

A group of flash cells that share common erase circuitry and erase simultaneously

Clear:

Indicates a logic zero (0)

CUI:

Command User Interface

MLC:

Multi-Level Cell

OTP:

One Time Programmable

PLR:

Protection Lock Register

PR:

Protection Register

PRD

Protection Register Data

Program:

To write data to the flash array

RCR:

Read Configuration Register

RFU:

Reserved for Future Use

Set:

Indicates a logic one (1)

SR:

Status Register

SRD

Status Register Data

VPEN:

Refers to a signal or package connection name

PEN

Refers to timing or voltage levels

WSM:

Write State Machine

XSR

eXtended Status Register

1.3

Conventions

0x:

Hexadecimal prefix

0b:

Binary prefix

k (noun):

1,000

M (noun):

1,000,000

Nibble

4 bits

Byte:

8 bits

Word:

16 bits

Kword:

1,024 words

Kb:

1,024 bits

KB:

1,024 bytes

Mb:

1,048,576 bits

MB:

1,048,576 bytes

Brackets:

Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]).

28F128J3, 28F640J3, 28F320J3

Datasheet

2.0

Device Description

2.1

Product Overview

The 3 Volt Intel StrataFlash

memory family contains high-density memories organized as 16

Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized

as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is
organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two 128-
Kbyte erase blocks. Blocks are selectively and individually lockable in-system. A 128-bit
protection register has multiple uses, including unique flash device identification.

The device's optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-

compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,

memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device's 128-Kbyte blocks typically within one second--
independent of other blocks. Each block can be independently erased 100,000 times. Block erase

suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming

performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance more than 20 times over non-Write Buffer writes.

Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block
erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block

Lock-Bit and Clear Block Lock-Bits commands).

The Status Register indicates when the WSM's block erase, program, or lock-bit configuration
operation is finished.

The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/

28F128J3, 28F640J3, 28F320J3

Datasheet

BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-
bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.

Three CE signals are used to enable and disable the device. A unique CE logic design (see

Table 3,

"Chip Enable Truth Table" on page 16

) reduces decoder logic typically required for multi-chip

designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.

The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-
bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-
bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care).
A device block diagram is shown in Figure 4 on page 14.

When the device is disabled (see

Table 3 on page 16

) and the RP# signal is at V

, the standby

mode is enabled. When the RP# signal is at GND, a further power-down mode is enabled which
minimizes power consumption and provides write protection during reset. A reset time (t

PHQV

) is

required from RP# switching high until outputs are valid. Likewise, the device has a wake time
(t

PHWL

) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is

reset and the Status Register is cleared.

2.2

Ballout Diagrams

Intel StrataFlash

Memory is available in three package types. Easy BGA in a 64-ball

configuration, along with 56-lead TSOP (Thin Small Outline Package), support all offered
densities. A 48-ball VF BGA package supporting the 32 and 64 Mbit device is also supported.

Figure 1

Figure 2

, and

Figure 3

show the pinouts.

28F128J3, 28F640J3, 28F320J3

Datasheet

NOTES:

1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).

NOTES:

1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC).
2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC).
3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC).
4. V

= 5 V ± 10% for the 28F640J5/28F320J5.

Figure 1. 3 Volt Intel StrataFlash

Memory Easy BGA Ballout

Easy BGA

Top View- Ball side down

CE2# RFU

D13

VSS

A24

256M

VSS

WE#

BYTE#

OE#

STS

A11

RFU

RP#

A16 A17

RFU

A10

A15

A12

A20 A21

RFU

VSS

A14

CEO#

A19 CE1#

RFU

A13

VPEN

A18 A22

VCC

A23

128M

VCCQ

D14

D10

D12

D11

RFU

D15

RFU

Easy BGA

Bottom View- Ball side up

CE2#

RFU

D13 VSS

A24

256M

VSS

WE#

BYTE#

OE#

STS

A11

RFU RP#

A16

A17

RFU

A10

A15 A12

A20

A21

RFU

VSS

A14 CEO#

A19

CE1#

RFU

A13 VPEN

A18

A22

VCC

A23

128M

D5 VCCQ

D14

D10

D12 D11

RFU RFU

D15 RFU

VCC

Figure 2. 3 Volt Intel StrataFlash

Memory 56-Lead TSOP (32/64/128 Mbit)

Highlights pinout changes

3 Volt Intel

StrataFlash

Memory

56-Lead TSOP

Standard Pinout

14 mm x 20 mm

Top View

3
4

7
8

11
12

15
16

19
20

23
24

27
28

54
53

50
49

46
45

42
41

38
37

34
33

30
29

OE#
STS

WE#

GND

GND
DQ

CCQ

BYTE#

PEN

RP#

GND

(1)

32/64/128M

3 Volt Intel

StrataFlash

Memory

32/64/128M

3 Volt Intel

StrataFlash

Memory

(2)

(3)

28F320J5

OE#
STS

WE#

GND

CCQ

(4)

BYTE#

28F320J5

GND

PEN

RP#

(4)

28F160S3

RP#

GND

28F160S3

OE#

STS

WE#

GND

WP#

GND
DQ

BYTE#

NC
NC

28F128J3, 28F640J3, 28F320J3

Datasheet

2.3

Signal Descriptions

Table 1

lists the active signals used and provides a description of each.

Table 1. Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

INPUT

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is
in x8 mode. This address is latched during a x8 program cycle. Not used in x16
mode (i.e., the A0 input buffer is turned off when BYTE# is high).

A[23:1]

INPUT

ADDRESS INPUTS: Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
32-Mbit: A[21:0]
64-Mbit: A[22:0]
128-Mbit: A[23:0]

D[7:0]

INPUT/

OUTPUT

LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and
inputs commands during CUI writes. Outputs array, query, identifier, or status data
in the appropriate read mode. Floated when the chip is de-selected or the outputs
are disabled. Outputs D[6:0] are also floated when the WSM is busy. Check SR7 to
determine WSM status.

D[15:8]

INPUT/

OUTPUT

HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming
operations. Outputs array, query, or identifier data in the appropriate read mode; not
used for Status Register reads. Floated when the chip is de-selected, the outputs
are disabled, or the WSM is busy.

CE0,
CE1,
CE2

INPUT

CHIP ENABLES: Activates the device's control logic, input buffers, decoders, and
sense amplifiers. When the device is de-selected (see

Table 3 on page 16

), power

reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device
deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device
(see

Table 3 on page 16

RP#

INPUT

RESET/ POWER-DOWN: Resets internal automation and puts the device in power-
down mode. RP#-high enables normal operation. Exit from reset sets the device to
read array mode. When driven low, RP# inhibits write operations which provides
data protection during power transitions.

OE#

INPUT

OUTPUT ENABLE: Activates the device's outputs through the data buffers during a
read cycle. OE# is active low.

WE#

INPUT

WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.

STS

OPEN

DRAIN

OUTPUT

STATUS: Indicates the status of the internal state machine. When configured in
level mode (default mode), it acts as a RY/BY# signal. When configured in one of its
pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS signal, see the Configurations command.
Tie STS to VCCQ with a pull-up resistor.

BYTE#

INPUT

BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or
output on D[7:0], while D[15:8] float. Address A0 selects between the high and low
byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer.
Address A1 then becomes the lowest order address.

VPEN

INPUT

ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks,
programming data, or configuring lock-bits.
With V

PEN

PENLK

, memory contents cannot be altered.

VCC

SUPPLY

DEVICE POWER SUPPLY: With V

LKO

, all write attempts to the flash memory

are inhibited.

28F128J3, 28F640J3, 28F320J3

Datasheet

2.4

Block Diagram

VCCQ

POWER

I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to
V

GND

SUPPLY

GROUND: Do not float any ground signals.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

RFU

RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for
future device functionality and enhancement.

Table 1. Signal Descriptions (Sheet 2 of 2)

Symbol

Type

Name and Function

Figure 4. 3 Volt Intel StrataFlash

Memory Block Diagram

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Mbit: One-hundred

twenty-eight

128-Kbyte Blocks

Input Buffer

Outp

t
c
h
/
Mu

l
t
i
p
l
e

x
e
r

Y-Gating

Program/Erase
Voltage Switch

Data

Comparator

Status

Identifier
Register

t
a

e
gi

s
t
er

I/O Logic

Address

Latch

Address

Counter

X-Decoder

Y-Decoder

Input Buffer

Output

Buffer

GND

VCC

VPEN

CE0
CE1
CE2

WE#

OE#
RP#

BYTE#

Command

User

Interface

A[MAX:MIN]

D[15:0]

VCC

r
i
t
e

uffer

Write State

Machine

Multiplexer

Query

STS

VCCQ

Logic

A[2:0]

28F128J3, 28F640J3, 28F320J3

Datasheet

3.0

Device Operations

This section provides an overview of device operations. The on-chip Write State Machine (WSM)
manages all block-erase and word-program algorithms. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus.

Device commands are written to the CUI to control all of the flash memory device's operations.
The CUI does not occupy an addressable memory location; it's the mechanism through which the
flash device is controlled.

3.1

Bus Operations

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.

Table 2. Bus Operations

Mode

RP#

CE0,1,2

OE#

(2)

WE#

(2)

Address

VPEN

Data

(3)

STS

(default

mode)

Notes

Read Array

Enabled

OUT

High Z

(7)

4,5,6

Output Disable

Enabled

High Z

Standby

Disabled

High Z

Reset/Power-Down
Mode

High Z

(7)

Read Identifier Codes

Enabled

See

Table 5

Note 8

High Z

(7)

Read Query

Enabled

See

Table 4.4

Note 9

High Z

(7)

Read Status (WSM off)

Enabled

OUT

Read Status (WSM on)

Enabled

D7 = D

OUT

D[15:8] = High Z

D[6:0] = High Z

Write

Enabled

PENH

6,10,11

NOTES:

1. See

Table 3 on page 16

for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.
3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.
4. Refer to DC Characteristics. When V

PEN

PENLK

, memory contents can be read, but not altered.

5. X can be V

or V

for control and address signals, and V

PENLK

or V

PENH

for V

PEN

. See DC Characteristics for V

PENLK

and

PENH

voltages.

6. In default mode, STS is V

when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It

is V

when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or

reset/power-down mode.

7. High Z will be V

with an external pull-up resistor.

8. See

Section 4.2, "Read Identifier Codes" on page 19

for read identifier code data.

9. See

Section 4.4, "Read Query/CFI" on page 22

for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V

PEN

= V

PENH

and V

is within specification.

28F128J3, 28F640J3, 28F320J3

Datasheet

3.1.1

Read Mode

To perform a bus read operation, CE# (Please refer to

Table 3 on page 16

) and OE# must be

asserted. CE# is the device-select control; when active, it enables the flash memory device. OE# is
the data-output control; when active, the addressed flash memory data is driven onto the I/O bus.
For all read states, WE# and RP# must be de-asserted. See

Section 11.1, "Read Operations" on

page 37

. Refer to

Section 4.0, "Read Operations" on page 19

for details on reading from the flash

array, and refer to

Section 8.0, "Special Modes" on page 30

for details regarding all other available

read states.

3.1.2

Write

Writing commands to the Command User Interface enables various modes of operation, including
the reading of device data, query, identifier codes, inspection and clearing of the Status Register,
and, when V

PEN

= V

PENH

, block erasure, program, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Block Lock-Bit commands require the command and block within the device to be
locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see

Table 3 on

page 16

). Standard microprocessor write timings are used.

3.1.3

Output Disable

With OE# at a logic-high level (V

), the device outputs are disabled. Output signals D[15:0] are

placed in a high-impedance state.

Table 3. Chip Enable Truth Table

CE2

CE1

CE0

DEVICE

Enabled

Disabled

Enabled

Disabled

NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND.

28F128J3, 28F640J3, 28F320J3

Datasheet

3.1.4

Standby

CE0, CE1, and CE2 can disable the device (see

Table 3 on page 16

) and place it in standby mode

which substantially reduces device power consumption. D[15:0] outputs are placed in a high-
impedance state independent of OE#. If deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and consuming active power until the operation
completes.

3.1.5

Reset/Power-Down

RP# at V

initiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and

turns off numerous internal circuits. RP# must be held low for a minimum of t

PLPH

. Time t

PHQV

required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0x80.

During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t

PLPH

+ t

PHRH

until the

reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t

PHWL

is required after RP# goes to logic-high (V

) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel

Flash memories

allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.2

Device Commands

When the V

PEN

voltage

PENLK

, only read operations from the Status Register, query, identifier

codes, or blocks are enabled. Placing V

PENH

on V

PEN

additionally enables block erase, program,

and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI.

Table 4, "Intel StrataFlash® Memory Command Set Definitions" on

page 17

defines these commands.

Table 4. Intel StrataFlash

Memory Command Set Definitions (Sheet 1 of 2)

Command

Scalable or

Basic

Command

Set

(2)

Bus

Cycles

Req'd.

First Bus Cycle

Second Bus Cycle

Notes

Oper

(3)

Addr

(4)

Data

(5,6)

Oper

(3)

Addr

(4)

Data

(5,6)

Read Array

SCS/BCS

Write

0xFF

Read Identifier Codes

SCS/BCS

Write

0X90

Read

1,7

Read Query

SCS

Write

0x98

Read

28F128J3, 28F640J3, 28F320J3

Datasheet

Read Status Register

SCS/BCS

Write

0x70

Read

SRD

1,8

Clear Status Register

SCS/BCS

Write

0x50

Write to Buffer

SCS/BCS

> 2

Write

0xE8

Write

1,9, 10,

Word/Byte Program

SCS/BCS

Write

0x40 or

0x10

Write

1,12,13

Block Erase

SCS/BCS

Write

0x20

Write

0xD0

1,11,12

Block Erase, Program
Suspend

SCS/BCS

Write

0xB0

1,12,14

Block Erase, Program
Resume

SCS/BCS

Write

0xD0

1,12

Configuration

SCS

Write

0xB8

Write

Set Block Lock-Bit

SCS

Write

0x60

Write

0x01

Clear Block Lock-Bits

SCS

Write

0x60

Write

0xD0

1,15

Protection Program

Write

0xC0

Write

NOTES:

1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable

Command Set (SCS) is also referred to as the Intel Extended Command Set.

3. Bus operations are defined in

Table 2

4. X = Any valid address within the device.

BA = Address within the block.
IA = Identifier Code Address: see

Table 5

QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A[16:1]; all other address
inputs are ignored.

5. ID = Data read from Identifier Codes.

QD = Data read from Query database.
SRD = Data read from Status Register. See

Table 6

for a description of the Status Register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.

6. The upper byte of the data bus (D[15:8]) during command writes is a "Don't Care" in x16 operation.
7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See

Section 4.2

for read identifier code data.

8. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on

this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0F. The third and consecutive
bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (0xD0) is expected after
exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. See

Figure

12, "Write to Buffer Flowchart" on page 52

for additional information

11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued.
12.Attempts to issue a block erase or program to a locked block.
13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup.
14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated.
15.The clear block lock-bits operation simultaneously clears all block lock-bits.

Table 4. Intel StrataFlash

Memory Command Set Definitions (Sheet 2 of 2)

Command

Scalable or

Basic

Command

Set

(2)

Bus

Cycles

Req'd.

First Bus Cycle

Second Bus Cycle

Notes

Oper

(3)

Addr

(4)

Data

(5,6)

Oper

(3)

Addr

(4)

Data

(5,6)

28F128J3, 28F640J3, 28F320J3

Datasheet

4.0

Read Operations

The device supports four types of read modes: read array, read identifier, read status or read query.
Upon power-up or return from reset, the device defaults to read array mode. To change the device's
read mode, the appropriate Read command must be written to the device. (See

Section 3.2, "Device

Commands" on page 17

.) See

Section 8.0, "Special Modes" on page 30

for details regarding read

status, read ID, and CFI query modes.

Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read
Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the
data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be
enabled (see

Table 3, "Chip Enable Truth Table" on page 16

), and OE# must be driven active to

obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled
(see

Table 3

), select the memory device. OE# is the data output (D[15:0]) control and, when active,

drives the selected memory data onto the I/O bus. WE# must be at V

4.1

Read Array

Upon initial device power-up and after exit from reset/power-down mode, the device defaults to
read array mode. The read configuration register defaults to asynchronous read page mode. The
Read Array command also causes the device to enter read array mode. The device remains enabled
for reads until another command is written. If the internal WSM has started a block erase, program,

or lock-bit configuration, the device will not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via an Erase or Program Suspend command.
The Read Array command functions independently of the V

PEN

voltage.

4.1.1

Asynchronous Page-Mode Read

Asynchronous Page Mode is the default read mode on power-up or reset. To perform a page mode
read after any other operation, the Read Array command must be issued to read from the flash
array. Asynchronous page mode reads are permitted in all blocks and is used to access register
information, but only one word is loaded into the page buffer during register access. In

asynchronous page mode, array data is sensed and loaded into a page buffer. After the initial delay,
the first word out of the page buffer corresponds to the initial address.

Address bits A[2:0] determine which word is output from the page buffer. Subsequent reads from
the device come from the page buffer, and are output on D[15:0] after a minimum delay as long as

address bits A[2:0] are the only address bits that change. Data can be read from the page buffer
multiple times, and in any order. If address bits A[MAX:3] change at any time, or if CE# is
toggled, the device will sense and load new data into the page buffer.

4.2

Read Identifier Codes

The Read identifier codes operation outputs the manufacturer code, device-code, and the block
lock configuration codes for each block (See

Figure 3.2 on page 17

for details on issuing the Read

Device Identifier command). Page-mode reads are not supported in this read mode. To terminate
the operation, write another valid command. Like the Read Array command, the Read Identifier

28F128J3, 28F640J3, 28F320J3

Datasheet

Codes command functions independently of the V

PEN

voltage. This command is valid only when

the WSM is off or the device is suspended. Following the Read Identifier Codes command, the
following information can be read

4.3

Read Status Register

The Status Register may be read to determine when a block erase, program, or lock-bit
configuration is complete and whether the operation completed successfully. It may be read at any
time by writing the Read Status Register command. After writing this command, all subsequent
read operations output data from the Status Register until another valid command is written. Page-

mode reads are not supported in this read mode. The Status Register contents are latched on the
falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see

Table 3,

"Chip Enable Truth Table" on page 16

). OE# must toggle to V

or the device must be disabled

before further reads to update the Status Register latch. The Read Status Register command
functions independently of the V

PEN

voltage.

During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR7 is valid
until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and
D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check
SR7), all contents of the Status Register are valid when read.

Table 5. Identifier Codes

Code

Address

(1)

Data

Manufacture Code

00000

(00) 89

Device Code

32-Mbit

00001

(00) 16

64-Mbit

00001

(00) 17

128-Mbit

00001

(00) 18

Block Lock Configuration

0002

(2)

Block Is Unlocked

D0 = 0

Block Is Locked

D0 = 1

Reserved for Future Use

D[7:1]

NOTES:

1. A0 is not used in either x8 or x16 modes when obtaining the identifier

codes. The lowest order address line is A1. Data is always presented
on the low byte in x16 mode (upper byte contains 00h).

2. X selects the specific block's lock configuration code.

28F128J3, 28F640J3, 28F320J3

Datasheet

Table 6. Status Register Definitions

Table 7. eXtended Status Register Definitions

WSMS

ESS

ECLBS

PSLBS

VPENS

PSS

DPS

bit 7

bit 6

bit 5

bit 4

bit 3

bit2

bit 1

bit 0

High Z

When

Busy?

Status Register Bits

Notes

Yes

SR7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

SR6 = ERASE SUSPEND STATUS

1 = Block Erase Suspended
0 = Block Erase in Progress/Completed

SR5 = ERASE AND CLEAR LOCK-BITSSTATUS

1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits

SR4 = PROGRAM AND SET LOCK-BIT STATUS

1 = Error in Setting Lock-Bit
0 = Successful Set Block Lock Bit

SR3 = PROGRAMMING VOLTAGE STATUS

1 = Low Programming Voltage Detected, Operation

Aborted

0 = Programming Voltage OK

SR2 = PROGRAM SUSPEND STATUS

1 = Program suspended
0 = Program in progress/completed

SR1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit Detected, Operation Abort
0 = Unlock

SR0 = RESERVED FOR FUTURE ENHANCEMENTS

Check STS or SR7 to determine block erase,
program, or lock-bit configuration completion.
SR[6:0] are not driven while SR7 = "0."

If both SR5 and SR4 are "1"s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.

SR3 does not provide a continuous programming
voltage level indication. The WSM interrogates and
indicates the programming voltage level only after
Block Erase, Program, Set Block Lock-Bit, or Clear
Block Lock-Bits command sequences.

SR1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bits only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, depending on the attempted
operation, if the block lock-bit is set. Read the block
lock configuration codes using the Read Identifier
Codes command to determine block lock-bit status.
SR0 is reserved for future use and should be
masked when polling the Status Register.

WBS

Reserved

bit 7

bits 6--0

High Z

When

Busy?

Status Register Bits

Notes

Yes

XSR7 = WRITE BUFFER STATUS
1 = Write buffer available
0 = Write buffer not available
XSR6XSR0 = RESERVED FOR FUTURE
ENHANCEMENTS

After a Buffer-Write command, XSR7 = 1 indicates
that a Write Buffer is available.
SR[6:0] are reserved for future use and should be
masked when polling the Status Register.

28F128J3, 28F640J3, 28F320J3

Datasheet

4.4

Read Query/CFI

The query register contains an assortment of flash product information such as block size, density,
allowable command sets, electrical specifications and other product information. The data
contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any
information from the query register, execute the Read Query Register command. See

Section 3.2,

"Device Commands" on page 17

for details on issuing the CFI Query command. Refer to

Appendix B, "Query Structure Overview" on page 46

for a detailed explanation of the CFI register.

Information contained in this register can only be accessed by executing a single-word read.

5.0

Programming Operations

The device supports two different programming methods: word programming, and write-buffer
programming. Successful programming requires the addressed block to be unlocked. An attempt to
program a locked block will result in the operation aborting, and SR1 and SR4 being set, indicating
a programming error. The following sections describe device programming in detail.

5.1

Byte/Word Program

Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup
(standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address
and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program
and program verify algorithms internally. After the program sequence is written, the device
automatically outputs SRD when read (see

Figure 14, "Byte/Word Program Flowchart" on

page 54

). The CPU can detect the completion of the program event by analyzing the STS signal or

SR7.

When program is complete, SR4 should be checked. If a program error is detected, the Status
Register should be cleared. The internal WSM verify only detects errors for "1"s that do not
successfully program to "0"s. The CUI remains in Read Status Register mode until it receives
another command.

Reliable byte/word programming can only occur when V

and V

PEN

are valid. If a byte/word

program is attempted while V

PEN

PENLK

, SR4 and SR3 will be set. Successful byte/word

programs require that the corresponding block lock-bit be cleared. If a byte/word program is
attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set.

5.2

Write to Buffer

To program the flash device, a Write to Buffer command sequence is initiated. A variable number
of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the
Write to Buffer Setup command is issued along with the Block Address (see

Figure 12, "Write to

Buffer Flowchart" on page 52

). At this point, the eXtended Status Register (XSR, see

Table 7

)

information is loaded and XSR7 reverts to "buffer available" status. If XSR7 = 0, the write buffer is
not available. To retry, continue monitoring XSR7 by issuing the Write to Buffer setup command

with the Block Address until XSR7 = 1. When XSR7 transitions to a "1," the buffer is ready for
loading.

28F128J3, 28F640J3, 28F320J3

Datasheet

Next, a word/byte count is given to the part with the Block Address. On the next write, a device
start address is given along with the write buffer data. Subsequent writes provide additional device
addresses and data, depending on the count. All subsequent addresses must lie within the start
address plus the count.

Internally, this device programs many flash cells in parallel. Because of this parallel programming,
maximum programming performance and lower power are obtained by aligning the start address at
the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).

After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM

(Write State Machine) to begin copying the buffer data to the flash array. If a command other than
Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated
and SR5 and SR4 will be set. For additional buffer writes, issue another Write to Buffer Setup
command and check XSR7.

If an error occurs while writing, the device will stop writing, and SR4 will be set to indicate a
program failure. The internal WSM verify only detects errors for "1"s that do not successfully
program to "0"s. If a program error is detected, the Status Register should be cleared. Any time
SR4 and/or SR5 is set (e.g., a media failure occurs during a program or an erase), the device will
not accept any more Write to Buffer commands. Additionally, if the user attempts to program past
an erase block boundary with a Write to Buffer command, the device will abort the write to buffer
operation. This will generate an "Invalid Command/Sequence" error and SR5 and SR4 will be set.

Reliable buffered writes can only occur when V

PEN

= V

PENH

. If a buffered write is attempted

while V

PEN

PENLK

, SR4 and SR3 will be set. Buffered write attempts with invalid V

and

PEN

voltages produce spurious results and should not be attempted. Finally, successful

programming requires that the corresponding block lock-bit be reset. If a buffered write is
attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set.

5.3

Program Suspend

The Program Suspend command allows program interruption to read data in other flash memory
locations. Once the programming process starts (either by initiating a write to buffer or byte/word
program operation), writing the Program Suspend command requests that the WSM suspend the
program sequence at a predetermined point in the algorithm. The device continues to output SRD
when read after the Program Suspend command is written. Polling SR7 can determine when the
programming operation has been suspended. When SR7 = 1, SR2 should also be set, indicating that
the device is in the program suspend mode. STS in level RY/BY# mode will also transition to V

Specification t

WHRH1

defines the program suspend latency.

At this point, a Read Array command can be written to read data from locations other than that
which is suspended. The only other valid commands while programming is suspended are Read
Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a

Program Resume command is written, the WSM will continue the programming process. SR2 and
SR7 will automatically clear and STS in RY/BY# mode will return to V

. After the Program

Resume command is written, the device automatically outputs SRD when read. V

PEN

must remain

at V

PENH

and V

must remain at valid V

levels (the same V

PEN

and V

levels used for

programming) while in program suspend mode. Refer to

Figure 15, "Program Suspend/Resume

Flowchart" on page 55

28F128J3, 28F640J3, 28F320J3

Datasheet

5.4

Program Resume

To resume (i.e., continue) a program suspend operation, execute the Program Resume command.
The Resume command can be written to any device address. When a program operation is nested
within an erase suspend operation and the Program Suspend command is issued, the device will
suspend the program operation. When the Resume command is issued, the device will resume and
complete the program operation. Once the nested program operation is completed, an additional
Resume command is required to complete the block erase operation. The device supports a
maximum suspend/resume of two nested routines. See

Figure 15, "Program Suspend/Resume

Flowchart" on page 55

6.0

Erase Operations

Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once
a block is erased, all bits within that block will read as a logic level one. To determine the status of
a block erase, poll the Status Register and analyze the bits. This following section describes block
erase operations in detail.

6.1

Block Erase

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires an appropriate
address within the block to be erased (erase changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle
block erase sequence is written, the device automatically outputs SRD when read (see

Figure 16,

"Block Erase Flowchart" on page 56

). The CPU can detect block erase completion by analyzing

the output of the STS signal or SR7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register.

When the block erase is complete, SR5 should be checked. If a block erase error is detected, the
Status Register should be cleared before system software attempts corrective actions. The CUI
remains in Read Status Register mode until a new command is issued.

This two-step command sequence of setup followed by execution ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both SR4 and
SR5 being set. Also, reliable block erasure can only occur when V

is valid and V

PEN

= V

PENH

If block erase is attempted while V

PEN

PENLK

, SR3 and SR5 will be set. Successful block erase

requires that the corresponding block lock-bit be cleared. If block erase is attempted when the

corresponding block lock-bit is set, SR1 and SR5 will be set.

6.2

Block Erase Suspend

The Block Erase Suspend command allows block-erase interruption to read or program data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs SRD when read after the Block Erase Suspend command is written.

Polling SR7 then SR6 can determine when the block erase operation has been suspended (both will
be set). In default mode, STS will also transition to V

. Specification t

WHRH

defines the block

erase suspend latency.

28F128J3, 28F640J3, 28F320J3

Datasheet

At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A program command sequence can also be issued during erase suspend to program
data in other blocks. During a program operation with block erase suspended, SR7 will return to
"0" and STS output (in default mode) will transition to V

. However, SR6 will remain "1" to

indicate block erase suspend status. Using the Program Suspend command, a program operation
can also be suspended. Resuming a suspended programming operation by issuing the Program
Resume command allows continuing of the suspended programming operation. To resume the
suspended erase, the user must wait for the programming operation to complete before issuing the
Block Erase Resume command.

The only other valid commands while block erase is suspended are Read Query, Read Status
Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM will continue the block erase process. SR6 and
SR7 will automatically clear and STS (in default mode) will return to V

. After the Erase Resume

command is written, the device automatically outputs SRD when read (see

Figure 17, "Block Erase

Suspend/Resume Flowchart" on page 57

). V

PEN

must remain at V

PENH

(the same V

PEN

level used

for block erase) while block erase is suspended. Block erase cannot resume until program
operations initiated during block erase suspend have completed.

6.3

Erase Resume

To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The
Resume command can be written to any device address. When a program operation is nested

within an erase suspend operation and the Program Suspend command is issued, the device will
suspend the program operation. When the Resume command is issued, the device will resume the
program operations first. Once the nested program operation is completed, an additional Resume
command is required to complete the block erase operation. The device supports a maximum
suspend/resume of two nested routines. See

Figure 16, "Block Erase Flowchart" on page 56

28F128J3, 28F640J3, 28F320J3

Datasheet

7.0

Security Modes

This device offers both hardware and software security features. Block lock operations, PRs, and
VPEN allow the user to implement various levels of data protection. The following section
describes security features in detail.

7.1

Set Block Lock-Bit

A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program

and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command.
This command is invalid while the WSM is running or the device is suspended.

Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with
appropriate block address is followed by either the set block lock-bit confirm (and an address

within the block to be locked). The WSM then controls the set lock-bit algorithm. After the
sequence is written, the device automatically outputs Status Register data when read (see

Figure 18

on page 58

). The CPU can detect the completion of the set lock-bit event by analyzing the STS

signal output or SR7.

When the set lock-bit operation is complete, SR4 should be checked. If an error is detected, the
Status Register should be cleared. The CUI will remain in Read Status Register mode until a new
command is issued.

This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally

set. An invalid Set Block Lock-Bit command will result in SR4 and SR5 being set. Also, reliable
operations occur only when V

and V

PEN

are valid. With V

PEN

PENLK

, lock-bit contents are

protected against alteration.

7.2

Clear Block Lock-Bits

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-
bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while
the WSM is running or the device is suspended.

Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup
is first written. The device automatically outputs Status Register data when read (see

Figure 19 on

page 59

). The CPU can detect completion of the clear block lock-bits event by analyzing the STS

signal output or SR7.

When the operation is complete, SR5 should be checked. If a clear block lock-bit error is detected,
the Status Register should be cleared. The CUI will remain in Read Status Register mode until
another command is issued.

This two-step sequence of setup followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR4 and
SR5 being set. Also, a reliable clear block lock-bits operation can only occur when V

and V

PEN

are valid. If a clear block lock-bits operation is attempted while V

PEN

PENLK

, SR3 and SR5 will

be set.

28F128J3, 28F640J3, 28F320J3

Datasheet

If a clear block lock-bits operation is aborted due to V

PEN

or V

transitioning out of valid range,

block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required
to initialize block lock-bit contents to known values.

7.3

Protection Register Program

The 3 Volt Intel StrataFlash

memory includes a 128-bit Protection Register that can be used to

increase the security of a system design. For example, the number contained in the PR can be used

to "mate" the flash component with other system components such as the CPU or ASIC, preventing
device substitution.

The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at
the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank

for customer designers to program as desired. Once the customer segment is programmed, it can be
locked to prevent further programming.

7.3.1

Reading the Protection Register

The Protection Register is read in the identification read mode. The device is switched to this mode
by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses
shown in

Table 8

Table 9

retrieve the specified information. To return to read array mode, write

the Read Array command (0xFF).

7.3.2

Programming the Protection Register

Protection Register bits are programmed using the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time
for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next
write to the device will latch in address and data and program the specified location. The allowable
addresses are shown in

Table 8

Table 9

. See

Figure 20, "Protection Register Programming

Flowchart" on page 60

Any attempt to address Protection Program commands outside the defined PR address space will
result in a Status Register error (SR4 will be set). Attempting to program a locked PR segment will
result in a Status Register error (SR4 and SR1 will be set).

7.3.3

Locking the Protection Register

The user-programmable segment of the Protection Register is lockable by programming Bit 1 of
the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique
device number. Bit 1 is set using the Protection Program command to program "0xFFFD" to the
PLR. After these bits have been programmed, no further changes can be made to the values stored
in the protection register. Protection Program commands to a locked section will result in a Status
Register error (SR4 and SR1 will be set). PR lockout state is not reversible.

28F128J3, 28F640J3, 28F320J3

Datasheet

Table 8. Word-Wide Protection Register Addressing

Word

Use

LOCK

Both

Factory

User

NOTE:

All address lines not specified in the above table must be 0 when accessing the Protection Register
(i.e., A[MAX:9] = 0.)

Table 9. Byte-Wide Protection Register Addressing

Byte

Use

LOCK

Both

LOCK

Both

Factory

User

NOTE:

All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A[MAX:9] = 0.

28F128J3, 28F640J3, 28F320J3

Datasheet

7.4

Array Protection

The V

PEN

signal is a hardware mechanism to prohibit array alteration. When the V

PEN

voltage is

below the V

PENLK

voltage, array contents cannot be altered. To ensure a proper erase or program

operation, V

PEN

must be set to a valid voltage level. To determine the status of an erase or program

operation, poll the Status Register and analyze the bits.

8.0

Special Modes

This section describes how to read the status, ID, and CFI registers. This section also details how to
configure the STS signal.

8.1

Set Read Configuration

This command is not supported on this product. This device will default to the asynchronous page
mode. If this command is given to the device, it will not affect the operation of the device.

8.1.1

Read Configuration

The device will support both asynchronous page mode and standard word/byte reads. No
configuration is required.

Status Register and identifier only support standard word/byte single read operations.

Table 10. Read Configuration Register Definition

8.2

STS

The Status (STS) signal can be configured to different states using the Configuration command.
Once the STS signal has been configured, it remains in that configuration until another
configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/
BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the
state machine is ready for a new operation or suspended.

Table 11, "STS Configuration Coding

Definitions" on page 31

displays the possible STS configurations.

16 (A16)

Notes

RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled

Read mode configuration effects reads from the flash array.
Status Register, query, and identifier reads support standard
word/byte read cycles.

RCR.151 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to "0."

28F128J3, 28F640J3, 28F320J3

Datasheet

To reconfigure the Status (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described below. For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00
configuration code with the Configuration command resets the STS signal to the default RY/BY#
level mode. The possible configurations and their usage are described in

Table 11, "STS

Configuration Coding Definitions" on page 31

. The Configuration command may only be given

when the device is not busy or suspended. Check SR7 for device status. An invalid configuration
code will result in both SR4 and SR5 being set. When configured in one of the pulse modes, the

STS signal pulses low with a typical pulse width of 250 ns.

Table 11. STS Configuration Coding Definitions

Reserved

Pulse on

Program

Complete

(1)

Pulse on

Erase

Complete

(1)

D[1:0] = STS Configuration Codes

Notes

00 = default, level mode;

device ready indication

Used to control HOLD to a memory controller to prevent accessing a

flash memory subsystem while any flash device's WSM is busy.

01 = pulse on Erase Complete

Used to generate a system interrupt pulse when any flash device in

an array has completed a block erase. Helpful for reformatting blocks

after file system free space reclamation or "cleanup."

10 = pulse on Program Complete

Used to generate a system interrupt pulse when any flash device in

an array has completed a program operation. Provides highest

performance for servicing continuous buffer write operations.

11 = pulse on Erase or Program

Complete

Used to generate system interrupts to trigger servicing of flash arrays

when either erase or program operations are completed, when a

common interrupt service routine is desired.

NOTES:

1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR4 and SR5 being set.

28F128J3, 28F640J3, 28F320J3

Datasheet

9.0

Power and Reset

This section provides an overview of some system level considerations in regards to the flash
device. This section provides a brief description of power-up, power-down, decoupling and reset
design considerations.

9.1

Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is

recommended to power-up and power-down VCC and VCCQ together. It is also recommended to
power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly
before VCC.

9.2

Power Supply Decoupling

When the device is enabled, many internal conditions change. Circuits are energized, charge pumps
are switched on, and internal voltage nodes are ramped. All of this internal activities produce

transient signals. The magnitude of the transient signals depends on the device and system loading.
To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each
VCC/VSS and VCCQ

signal

. Capacitors should be placed as close as possible to device

connections.

Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between
VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome
voltage slumps caused by PCB (printed circuit board) trace inductance.

9.3

Reset Characteristics

By holding the flash device in reset during power-up and power-down transitions, invalid bus
conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,
internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return

from reset, a certain amount of time is required before the flash device is able to perform normal
operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is
driven low during a program or erase operation, the program or erase operation will be aborted and
the memory contents at the aborted block or address are no longer valid. See

Figure 9, "AC

Waveform for Reset Operation" on page 42

for detailed information regarding reset timings.

28F128J3, 28F640J3, 28F320J3

Datasheet

10.0

Electrical Specifications

10.1

Absolute Maximum Ratings

This datasheet contains information on new products in production. The specifications are subject
to change without notice. Verify with your local Intel Sales office that you have the latest datasheet
before finalizing a design. Absolute maximum ratings are shown in

Table 12

Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage.

These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended
and extended exposure beyond the "Operating Conditions" may affect device reliability.

Table 12. Absolute Maximum Ratings

Parameter

Maximum Rating

Temperature under Bias Extended

40 °C to +85 °C

Storage Temperature

65 °C to +125 °C

Voltage On Any signal

2.0 V to +5.0 V

(1)

Output Short Circuit Current

100 mA

(2)

NOTES:

1. All specified voltages are with respect to GND. Minimum DC voltage is 0.5 V on input/output signals and

0.2 V on V

and V

PEN

signals. During transitions, this level may undershoot to 2.0 V for periods <20

ns. Maximum DC voltage on input/output signals, V

, and V

PEN

is V

+0.5 V which, during transitions,

may overshoot to V

+2.0 V for periods <20 ns.

2. Output shorted for no more than one second. No more than one output shorted at a time.

28F128J3, 28F640J3, 28F320J3

Datasheet

10.3

DC Current Characteristics

Table 14. DC Current Characteristics

Symb

Parameter

Typ

Max

Unit

Test Conditions

Notes

Input and V

PEN

Load Current

= V

Max; V

CCQ

= V

CCQ

Max

= V

CCQ

or GND

Output Leakage Current

= V

Max; V

CCQ

= V

CCQ

Max

= V

CCQ

or GND

CCS

Standby Current

120

CMOS Inputs, V

= V

Max,

Device is disabled (see

Table 3, "Chip

Enable Truth Table" on page 16

RP# = V

CCQ

± 0.2 V

1,2,3

0.71

TTL Inputs, V

= V

Max,

Device is disabled (see

Table 3

), RP# = V

CCD

Power-Down Current

120

RP# = GND ± 0.2 V, I

OUT

(STS) = 0 mA

CCR

Page Mode Read Current

CMOS Inputs, V

= V

Max, V

CCQ

Max using standard 4 word page

mode reads.
Device is enabled (see

Table 3

)

f = 5 MHz, I

OUT

= 0 mA

1,3

CMOS Inputs,V

= V

Max, V

CCQ

Max using standard 4 word page

mode reads.
Device is enabled (see

Table 3

)

f = 33 MHz, I

OUT

= 0 mA

CCW

Program or Set Lock-Bit

Current

CMOS Inputs, V

PEN

= V

1,4

TTL Inputs, V

PEN

= V

CCE

Block Erase or Clear Block

Lock-Bits Current

CMOS Inputs, V

PEN

= V

1,4

TTL Inputs, V

PEN

= V

CCWS

CCES

Program Suspend or Block

Erase Suspend Current

Device is enabled (see

Table 3

)

1,5

NOTES:

1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and

speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical
specifications.

2. Includes STS.
3. CMOS inputs are either V

± 0.2 V or GND ± 0.2 V. TTL inputs are either V

or V

4. Sampled, not 100% tested.
5. I

CCWS

and I

CCES

are specified with the device selected. If the device is read or written while in erase suspend mode,

the device's current draw is I

CCR

and I

CCWS

28F128J3, 28F640J3, 28F320J3

Datasheet

10.4

DC Voltage Characteristics

Table 15. DC Voltage Characteristics

Symbol

Parameter

Typ

Max

Unit

Test Conditions

Notes

Input Low Voltage

0.5

0.8

Input High Voltage

2.0

CCQ

+ 0.5

Output Low Voltage

0.4

CCQ

= V

CCQ

Min

= 2 mA

1,2

0.2

CCQ

= V

CCQ

Min

= 100 µA

Output High Voltage

0.85

CCQ

= V

CCQ

Min

= 2.5 mA

1,2

CCQ

0.2

CCQ

= V

CCQ

Min

= 100 µA

PENLK

PEN

Lockout during Program,

Erase and Lock-Bit Operations

2.2

2,3,4

PENH

PEN

during Block Erase,

Program, or Lock-Bit Operations

2.7

3.6

3,4

LKO

Lockout Voltage

2.2

NOTES:

1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when V

PEN

PENLK

and not guaranteed in the range between V

PENLK

(max) and V

PENH

(min), and above V

PENH

(max).

4. Typically, V

PEN

is connected to V

(2.7 V3.6 V).

5. Block erases, programming, and lock-bit configurations are inhibited when V

< V

LKO

, and

not guaranteed in the range between V

LKO

(min) and V

(min), and above V

(max).

28F128J3, 28F640J3, 28F320J3

Datasheet

11.0

AC Characteristics

11.1

Read Operations

Table 16. Read Operations (Sheet 1 of 2)

Versions

(All units in ns unless otherwise noted)

= 2.7 V3.6 V

(3)

Notes

CCQ

= 2.7 V3.6 V

(3)

Sym

Parameter

Density

Min

Max

AVAV

Read/Write Cycle Time

32 Mbit

110

1,2

64 Mbit

115/120

1,2

128 Mbit

120/150

1,2

AVQV

Address to Output Delay

32 Mbit

110

1,2

64 Mbit

115/120

1,2

128 Mbit

120/150

1,2

ELQV

to Output Delay

32 Mbit

110

1,2

64 Mbit

115/120

1,2

128 Mbit

120/150

1,2

GLQV

OE# to Non-Array Output Delay

1,2,4

PHQV

RP# High to Output Delay

32 Mbit

150

1,2

64 Mbit

180

1,2

128 Mbit

210

1,2

ELQX

to Output in Low Z

1,2,5

GLQX

OE# to Output in Low Z

1,2,5

EHQZ

High to Output in High Z

1,2,5

GHQZ

OE# High to Output in High Z

1,2,5

R10

Output Hold from Address, CE

, or OE#

Change, Whichever Occurs First

1,2,5

R11

ELFL/

ELFH

Low to BYTE# High or Low

1,2,5

R12

FLQV/

FHQV

BYTE# to Output Delay

1000

1,2

R13

FLQZ

BYTE# to Output in High Z

1000

1,2,5

R14

EHEL

CEx High to CEx Low

1,2,5

28F128J3, 28F640J3, 28F320J3

Datasheet

0606_16

NOTE:

low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE

high is defined at

the first edge of CE0, CE1, or CE2 that disables the device (see

Table 3

For standard word/byte read operations, R15 (t

APA

) will equal R2 (t

AVQV

When reading the flash array a faster t

GLQV

(R16) applies. Non-array reads refer to Status Register

reads, query reads, or device identifier reads.

R15

APA

Page Address Access Time

5, 6

R16

GLQV

OE# to Array Output Delay

NOTES:

low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE

high is defined at the first

edge of CE0, CE1, or CE2 that disables the device (see

Table 3

1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE# may be delayed up to t

ELQV

-t

GLQV

after the first edge of CE0, CE1, or CE2 that enables

the device (see

Table 3

) without impact on t

ELQV

3. See

Figure 10, "Transient Input/Output Reference Waveform for VCCQ = 2.7 V3.6 V" on

page 42

and

Figure 11, "Transient Equivalent Testing Load Circuit" on page 43

for testing

characteristics.

4. When reading the flash array a faster t

GLQV

(R16) applies. Non-array reads refer to Status

5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (t

APA

) will equal R2 (t

AVQV

Figure 7. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations

Table 16. Read Operations (Sheet 2 of 2)

Versions

(All units in ns unless otherwise noted)

= 2.7 V3.6 V

(3)

Notes

CCQ

= 2.7 V3.6 V

(3)

Sym

Parameter

Density

Min

Max

R10

High Z

R13

R11

R12

R4 or R16

Valid

Output

ADDRESSES [A

-A

]

Disabled (V

)

Enabled (V

)

[E]

OE# [G]

WE# [W]

DATA [D/Q]

-DQ

RP# [P]

BYTE# [F]

High Z

R14

ADDRESSES [A

-A

]

Valid

Output

R15

Valid

Output

Valid

Address

Valid

Address

Valid

Address

Valid

Output

Valid

Address

28F128J3, 28F640J3, 28F320J3

Datasheet

11.2

Write Operations

Table 17. Write Operations

Versions

Valid for All

Speeds

Unit

Notes

Symbol

Parameter

Min

Max

PHWL

PHEL

)

RP# High Recovery to WE# (CE

) Going Low

µs

1,2,3

ELWL

WLEL

)

(WE#) Low to WE# (CE

) Going Low

1,2,4

Write Pulse Width

1,2,4

DVWH

DVEH

)

Data Setup to WE# (CE

) Going High

1,2,5

AVWH

AVEH

)

Address Setup to WE# (CE

) Going High

1,2,5

WHEH

EHWH

)

(WE#) Hold from WE# (CE

) High

1,2,

WHDX

EHDX

)

Data Hold from WE# (CE

) High

1,2,

WHAX

EHAX

)

Address Hold from WE# (CE

) High

1,2,

WPH

Write Pulse Width High

1,2,6

W11

VPWH

VPEH

)

PEN

Setup to WE# (CE

) Going High

1,2,3

W12

WHGL

EHGL

)

Write Recovery before Read

1,2,7

W13

WHRL

EHRL

)

WE# (CE

) High to STS Going Low

500

1,2,8

W15

QVVL

PEN

Hold from Valid SRD, STS Going High

1,2,3,8,9

NOTES:

low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE

high is defined at the first edge of CE0, CE1,

or CE2 that disables the device (see

Table 3

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as

during read-only operations. Refer to AC CharacteristicsRead-Only Operations.

2. A write operation can be initiated and terminated with either CE

or WE#.

3. Sampled, not 100% tested.
4. Write pulse width (t

) is defined from CE

or WE# going low (whichever goes low last) to CE

or WE# going

high (whichever goes high first). Hence, t

= t

WLWH

= t

ELEH

= t

WLEH

= t

ELWH

5. Refer to

Table 4

for valid A

and D

for block erase, program, or lock-bit configuration.

6. Write pulse width high (t

WPH

) is defined from CE

or WE# going high (whichever goes high first) to CE

or WE#

going low (whichever goes low first). Hence, t

WPH

= t

WHWL

= t

EHEL

= t

WHEL

= t

EHWL

7. For array access, t

AVQV

is required in addition to t

WHGL

for any accesses after a write.

8. STS timings are based on STS configured in its RY/BY# default mode.
9. V

PEN

should be held at V

PENH

until determination of block erase, program, or lock-bit configuration success

(SR[1,3,4:5] = 0).

28F128J3, 28F640J3, 28F320J3

Datasheet

11.3

Block Erase, Program, and Lock-Bit Configuration

Performance

Table 18. Configuration Performance

Sym

Parameter

Typ

Max

(8)

Unit

Notes

W16

Write Buffer Byte Program Time
(Time to Program 32 bytes/16 words)

218

654

µs

1,2,3,4,5,6,7

W16

WHQV3

EHQV3

Byte Program Time (Using Word/Byte Program Command)

210

630

µs

1,2,3,4

Block Program Time (Using Write to Buffer Command)

0.8

2.4

sec

1,2,3,4

W16

WHQV4

EHQV4

Block Erase Time

1.0

5.0

sec

1,2,3,4

W16

WHQV5

EHQV5

Set Lock-Bit Time

75/85

µs

1,2,3,4,9

W16

WHQV6

EHQV6

Clear Block Lock-Bits Time

0.5

0.70/1.4

sec

1,2,3,4,10

W16

WHRH1

EHRH1

Program Suspend Latency Time to Read

75/90

µs

1,2,3,9

W16

WHRH

EHRH

Erase Suspend Latency Time to Read

35/40

µs

1,2,3,9

NOTES:

1. Typical values measured at T

= +25 °C and nominal voltages. Assumes corresponding lock-bits are

not set. Subject to change based on device characterization.

2. These performance numbers are valid for all speed versions.
3. Sampled but not 100% tested.
4. Excludes system-level overhead.
5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
6. Effective per-byte program time (t

WHQV1

, t

EHQV1

) is 6.8 µs/byte (typical).

7. Effective per-word program time (t

WHQV2

, t

EHQV2

) is 13.6 µs/word (typical).

8. Max values are measured at worst case temperature and V

corner after 100k cycles (except as

noted).

9. Max values are expressed at -25 °C/-40 °C.

10.Max values are expressed at 25 °C/-40 °C.

28F128J3, 28F640J3, 28F320J3

Datasheet

0606_18

NOTE:

STS is shown in its default mode (RY/BY#).

11.5

AC Test Conditions

NOTE:

AC test inputs are driven at V

CCQ

for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and

output timing ends, at V

CCQ

/2 V (50% of V

CCQ

). Input rise and fall times (10% to 90%) < 5 ns.

11.4

Reset Operation

Figure 9. AC Waveform for Reset Operation

RP# (P)

STS (R)

Table 19. Reset Specifications

Sym

Parameter

Min

Max

Unit

Notes

PLPH

RP# Pulse Low Time
(If RP# is tied to V

, this specification is not

applicable)

µs

1,2

PHRH

RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration

100

1,3

NOTES:

1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not

executing then the minimum required RP# Pulse Low Time is 100 ns.

3. A reset time, t

PHQV

, is required from the latter of STS (in RY/BY# mode) or RP# going high until

outputs are valid.

Figure 10. Transient Input/Output Reference Waveform for V

CCQ

= 2.7 V3.6 V

Output

Test Points

Input V

CCQ

0.0

CCQ

28F128J3, 28F640J3, 28F320J3

Datasheet

Appendix B Common Flash Interface

The Common Flash Interface(CFI) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for
entire families of devices. This allows device independent, JEDEC ID-independent, and forward-
and backward-compatible software support for the specified flash device families. It allows flash
vendors to standardize their existing interfaces for long-term compatibility.

This appendix defines the data structure or "database" returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.

B.1

Query Structure Output

The Query "database" allows system software to gain information for controlling the flash

component. This section describes the device's CFI-compliant interface that allows the host system
to access Query data.

Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H
data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (D[7:0]) and 00h in the

high byte (D[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the
"h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always
"00h," the leading "00" has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

28F128J3, 28F640J3, 28F320J3

Datasheet

B.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or "database." The structure sub-sections and address locations are summarized
below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for
a full description of CFI.

The following sections describe the Query structure sub-sections in detail.

Table 20. Summary of Query Structure Output as a Function of Device and Mode

Device

Type/

Mode

Query start location in

maximum device bus

width addresses

Query data with maximum

device bus width addressing

Query data with byte

addressing

Hex

Offset

Hex

Code

ASCII

Value

Hex

Offset

Hex

Code

ASCII

Value

x16 device

10h

10:

0051

"Q"

20:

"Q"

x16 mode

11:

0052

"R"

21:

"Null"

12:

0059

"Y"

22:

"R"

x16 device

20:

"Q"

x8 mode

N/A

(1)

N/A

(1)

21:

"Q"

22:

"R"

NOTE:

1. The system must drive the lowest order addresses to access all the device's array data when the device is

configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the
system, is "Not Applicable" for x8-configured devices.

Table 21. Example of Query Structure Output of a x16- and x8-Capable Device

Word Addressing

Byte Addressing

Offset

Hex Code

Value

Offset

Hex Code

Value

D15D

0010h

0051

"Q"

20h

"Q"

0011h

0052

"R"

21h

"Q"

0012h

0059

"Y"

22h

"R"

0013h

P_ID

PrVendor

23h

"R"

0014h

P_ID

ID #

24h

"Y"

0015h

PrVendor

25h

"Y"

0016h

TblAdr

26h

P_ID

PrVendor

0017h

A_ID

AltVendor

27h

P_ID

ID #

0018h

A_ID

ID #

28h

P_ID

ID #

...

28F128J3, 28F640J3, 28F320J3

Datasheet

B.3

Block Status Register

The block status register indicates whether an erase operation completed successfully or whether a
given block is locked or can be accessed for flash program/erase operations.

B.4

CFI Query Identification String

The CFI Query Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and supported
vendor-specified command set(s).

Table 22. Query Structure

Offset

Sub-Section Name

Description

Notes

00h

Manufacturer Code

01h

Device Code

(BA+2)h

(2)

Block Status Register

Block-Specific Information

1,2

04-0Fh

Reserved

Reserved for Vendor-Specific Information

10h

CFI Query Identification String

Reserved for Vendor-Specific Information

1Bh

System Interface Information

Command Set ID and Vendor Data Offset

27h

Device Geometry Definition

Flash Device Layout

(3)

Primary Intel-Specific Extended
Query Table

Vendor-Defined Additional Information
Specific to the Primary Vendor Algorithm

1,3

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset

address as a function of device bus width and mode.

2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the

block size is 128 Kbyte).

3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.

Table 23. Block Status Register

Offset

Length

Description

Address

Value

(BA+2)h

(1)

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked
1 = Locked

BA+2:

(bit 0): 0 or 1

BSR 17: Reserved for Future Use

BA+2:

(bit 17): 0

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location

in word mode).

Table 24. CFI Identification (Sheet 1 of 2)

Offset

Length

Description

Add.

Hex

Code

Value

10h

Query-unique ASCII string "QRY"

--51

"Q"

11:

--52

"R"

12:

--59

"Y"

13h

Primary vendor command set and control interface ID code.

13:

--01

16-bit ID code for vendor-specified algorithms

14:

--00

15h

Extended Query Table primary algorithm address

15:

--31

16:

--00

17h

Alternate vendor command set and control interface ID code.

17:

--00

28F128J3, 28F640J3, 28F320J3

Datasheet

B.5

System Interface Information

The following device information can optimize system interface software.

B.6

Device Geometry Definition

This field provides critical details of the flash device geometry.

0000h means no second vendor-specified algorithm exists

18:

--00

19h

Secondary algorithm Extended Query Table address.

19:

--00

0000h means none exists

1A:

--00

Table 24. CFI Identification (Sheet 2 of 2)

Offset

Length

Description

Add.

Hex

Code

Value

Table 25. System Interface Information

Offset

Length

Description

Add.

Hex

Code

Value

1Bh

logic supply minimum program/erase voltage

bits 03 BCD 100 mV
bits 47 BCD volts

1B:

--27

2.7 V

1Ch

logic supply maximum program/erase voltage

bits 03 BCD 100 mV
bits 47 BCD volts

1C:

--36

3.6 V

1Dh

[programming] supply minimum program/erase voltage

bits 03 BCD 100 mV
bits 47 HEX volts

1D:

--00

0.0 V

1Eh

[programming] supply maximum program/erase voltage

bits 03 BCD 100 mV
bits 47 HEX volts

1E:

--00

0.0 V

1Fh

"n" such that typical single word program time-out = 2

µs

1F:

--07

128 µs

20h

"n" such that typical max. buffer write time-out = 2

µs

20:

--07

128 µs

21h

"n" such that typical block erase time-out = 2

21:

--0A

1 s

22h

"n" such that typical full chip erase time-out = 2

22:

--00

23h

"n" such that maximum word program time-out = 2

times

typical

23:

--04

2 ms

24h

"n" such that maximum buffer write time-out = 2

times typical

24:

--04

2 ms

25h

"n" such that maximum block erase time-out = 2

times typical

25:

--04

16 s

26h

"n" such that maximum chip erase time-out = 2

times typical

26:

--00

Table 26. Device Geometry Definition (Sheet 1 of 2)

Offset

Length

Description

Code See Table

Below

27h

"n" such that device size = 2

in number of bytes

27:

28h

Flash device interface: x8 async x16 async x8/x16 async

28:

--02

x8/

x16

28:00,29:00 28:01,29:00 28:02,29:00

29:

--00

2Ah

"n" such that maximum number of bytes in write buffer = 2

2A:

--05

2B:

--00

28F128J3, 28F640J3, 28F320J3

Datasheet

Device Geometry Definition

B.7

Primary-Vendor Specific Extended Query Table

Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query
table specifies this and other similar information.

2Ch

Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in "bulk"
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)

2C:

--01

2Dh

Erase Block Region 1 Information

2D:

bits 015 = y, y+1 = number of identical-size erase blocks

2E:

bits 1631 = z, region erase block(s) size are z x 256 bytes

2F:
30:

Table 26. Device Geometry Definition (Sheet 2 of 2)

Offset

Length

Description

Code See Table

Below

Address

32 Mbit

64 Mbit

128 Mbit

27:

--16

--17

--18

28:

--02

29:

--00

2A:

--05

2B:

--00

2C:

--01

2D:

--1F

--3F

--7F

2E:

--00

2F:

--00

30:

--02

Table 27. Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

(P+0)h

Primary extended query table

31:

--50

"P"

(P+1)h

Unique ASCII string "PRI"

32:

--52

"R"

(P+2)h

33:

--49

"I"

(P+3)h

Major version number, ASCII

34:

--31

"1"

(P+4)h

Minor version number, ASCII

35:

--31

"1"

28F128J3, 28F640J3, 28F320J3

Datasheet

(P+5)h
(P+6)h
(P+7)h
(P+8)h

Optional feature and command support (1=yes, 0=no)

36:

--0A

bits 931 are reserved; undefined bits are "0." If bit 31 is

37:

--00

"1" then another 31 bit field of optional features follows at

38:

--00

the end of the bit-30 field.

39:

--00

bit 0 Chip erase supported

bit 0 = 0

bit 1 Suspend erase supported

bit 1 = 1

Yes

bit 2 Suspend program supported

bit 2 = 1

Yes

bit 3 Legacy lock/unlock supported

bit 3 = 1

(1)

Yes

(1)

bit 4 Queued erase supported

bit 4 = 0

bit 5 Instant Individual block locking supported

bit 5 = 0

bit 6 Protection bits supported

bit 6 = 1

Yes

bit 7 Page-mode read supported

bit 7 = 1

Yes

bit 8 Synchronous read supported

bit 8 = 0

(P+9)h

Supported functions after suspend: read Array, Status,
Query

Other supported operations are:
bits 17 reserved; undefined bits are "0"

3A:

--01

bit 0 Program supported after erase suspend

bit 0 = 1

Yes

(P+A)h
(P+B)h

Block status register mask

3B:

--01

bits 215 are Reserved; undefined bits are "0"

3C:

--00

bit 0 Block Lock-Bit Status register active

bit 0 = 1

Yes

bit 1 Block Lock-Down Bit Status active

bit 1 = 0

(P+C)h

logic supply highest performance program/erase

voltage

bits 03 BCD value in 100 mV
bits 47 BCD value in volts

3D:

--33

3.3 V

(P+D)h

optimum program/erase supply voltage

bits 03 BCD value in 100 mV
bits 47 HEX value in volts

3E:

--00

0.0 V

NOTE:

1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a

value of "0."

Table 27. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

28F128J3, 28F640J3, 28F320J3

Datasheet

Table 28. Protection Register Information

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

(P+E)h

Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available

3F:

--01

(P+F)h

(P+10)h

(P+11)h

(P+12)h

Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user-
programmable. Bits 0-15 point to the protection register lock
byte, the section's first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = "n" such that 2

= factory pre-programmed bytes

bits 24-31 = "n" such that 2

= user-programmable bytes

40:

--00

00h

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Table 29. Burst Read Information

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

(P+13)h

Page Mode Read capability
bits 07 = "n" such that 2

HEX value represents the number

of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.

44:

--03

8 byte

(P+14)h

Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.

45:

--00

(P+15)h

Reserved for future use

46:

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

28F128J3, 28F640J3, 28F320J3

Datasheet

Figure 14. Byte/Word Program Flowchart

Start

Write 40H,

Address

Write Data and

Address

Read Status

SR.7 =

Full Status

Check if Desired

Byte/Word

Program Complete

Read Status

(See Above)

Voltage Range Error

Device Protect Error

Programming Error

Byte/Word

Program

Successful

SR.3 =

SR.1 =

SR.4 =

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.

SR full status check can be done after each program operation, or
after a sequence of programming operations.

Write FFH after the last program operation to place device in read
array mode.

Bus

Operation

Standby

Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.

If an error is detected, clear the status register before attempting retry
or other error recovery.

Command

Setup Byte/

Word Program

Byte/Word

Program

Comments

Data = 40H
Addr = Location to Be Programmed

Data = Data to Be Programmed
Addr = Location to Be Programmed

Check SR.7
1 = WSM Ready
0 = WSM Busy

Command

Comments

Check SR.3
1 = Programming to Voltage Error

Detect

Check SR.4
1 = Programming Error

Read

(Note 1)

Status Register Data

Standby

Check SR.1
1 = Device Protect Detect

RP# = V

, Block Lock-Bit Is Set

Only required for systems
implemeting lock-bit configuration.

28F128J3, 28F640J3, 28F320J3

Datasheet

0606_11b

Figure 18. Set Block Lock-Bit Flowchart

Start

Write 60H,

Block Address

Write 01H,

Block Address

Read Status Register

SR.7 =

Full Status

Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Command

Set Block Lock-Bit

Setup

Comments

Data = 60H
Addr =Block Address

Read Status Register

Data (See Above)

Voltage Range Error

SR.3 =

Command Sequence

Error

SR.4,5 =

Set Lock-Bit Error

SR.4 =

Set Lock-Bit

Successful

Bus

Operation

Standby

Command

Comments

Check SR.3
1 = Programming Voltage Error

Detect

SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
command, in cases where multiple lock-bits are set before full status is
checked.

If an error is detected, clear the status register before attempting retry
or other error recovery.

Standby

Check SR.4, 5
Both 1 = Command Sequence

Error

Standby

Check SR.4
1 = Set Lock-Bit Error

Write

Set Block Lock-Bit

Confirm

Data = 01H
Addr = Block Address

Standby

Repeat for subsequent lock-bit operations.

Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device in read
array mode.

Check SR.7
1 = WSM Ready
0 = WSM Busy

Read

Status Register Data

28F128J3, 28F640J3, 28F320J3

Datasheet

0606_12b

Figure 19. Clear Lock-Bit Flowchart

Start

Write 60H

Write D0H

Read Status Register

SR.7 =

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

Write FFH after the clear lock-bits operation to place device in read
array mode.

Bus

Operation

Standby

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.

If an error is detected, clear the status register before attempting retry
or other error recovery.

Command

Clear Block

Lock-Bits Setup

Clear Block or

Lock-Bits Confirm

Comments

Data = 60H
Addr = X

Data = D0H
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Command

Comments

Check SR.3
1 = Programming Voltage Error

Detect

Read Status Register

Data (See Above)

Voltage Range Error

SR.3 =

Command Sequence

Error

SR.4,5 =

Clear Block Lock-Bits

Error

SR.5 =

Read

Status Register Data

Standby

Check SR.4, 5
Both 1 = Command Sequence

Error

Standby

Check SR.5
1 = Clear Block Lock-Bits Error

Clear Block Lock-Bits

Successful

28F128J3, 28F640J3, 28F320J3

Datasheet

Figure 20. Protection Register Programming Flowchart

Start

Write C0H

(Protection Reg.

Program Setup)

Write Protect. Register

Address/Data

Read Status Register

SR.7 = 1?

Full Status

Check if Desired

Program Complete

Read Status Register

Data (See Above)

PEN

Range Error

Protection Register

Programming Error

Attempted Program to

Locked Register -

Aborted

Program Successful

SR.3, SR.4 =

SR.1, SR.4 =

FULL STATUS CHECK PROCEDURE

Bus Operation

Write

Standby

Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of
program operations.

Write FFH after the last program operation to reset device to read array mode.

Bus Operation

Standby

SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.

If an error is detected, clear the status register before attempting retry or other
error recovery.

Yes

1, 1

0,1

1,1

Command

Protection Program

Setup

Protection Program

Comments

Data = C0H

Data = Data to Program
Addr = Location to Program

Check SR.7
1 = WSM Ready
0 = WSM Busy

Command

Comments

SR.1 SR.3 SR.4

PEN

Low

Prot. Reg.

Prog. Error

Locked:
Aborted

Read

Status Register Data Toggle
CE# or OE# to Update Status
Register Data

Standby

28F128J3, 28F640J3, 28F320J3

Datasheet

Appendix D Mechanical Information

Figure 21. 56-Lead TSOP Package Drawing and Specifications

Table 30. 56-Lead TSOP Dimension Table

Millimeters

Inches

Sym

Min

Nom

Max

Notes

Min

Nom

Max

Notes

Package Height

1.200

0.047

Standoff

0.050

0.002

Package Body Thickness

0.965

0.995

1.025

0.038

0.039

0.040

Lead Width

0.100

0.150

0.200

0.004

0.006

0.008

Lead Thickness

0.100

0.150

0.200

0.004

0.006

0.008

Package Body Length

18.200

18.400

18.600

0.717

0.724

0.732

Package Body Width

13.800

14.000

14.200

0.543

0.551

0.559

Lead Pitch

0.500

0.0197

Terminal Dimension

19.800

20.00

20.200

0.780

0.787

0.795

Lead Tip Length

0.500

0.600

0.700

0.020

0.024

0.028

Lead Count

Lead Tip Angle

0°

3°

5°

0°

3°

5°

Seating Plane Coplanarity

0.100

0.004

Lead to Package Offset

0.150

0.250

0.350

0.006

0.010

0.014

A5569-01

Detail A

Pin 1

Detail B

See Detail A

See Detail B

Seating
Plane

See Note 2

[231369-90]

See Notes 1 and 3

28F128J3, 28F640J3, 28F320J3

Datasheet

NOTES:

1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web

page at; www.intel.com/design/packtech/index.htm

2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page

at; www.intel.com/design/packtech/index.htm

Figure 22. 3 Volt Intel StrataFlash

Memory Easy BGA Mechanical Specifications

Seating

Plane

Top View - Ball side down

Bottom View - Ball Side Up

Ball A1

Corner

Note: Drawing not to scale

Ball A1

Corner

Side View

Millimeters

Inches

Symbol

Min

Nom

Max

Notes

Min

Nom

Ma x

Package Height

1.200

0.0472

Ball Height

0.250

0.0098

Package Body Thickness

0.780

0.0307

Ball (Lead) Width

0.330

0.430

0.530

0.0130

0.0169

0.0209

Package Body Width

9.900

10.000

10.100

0.3898

0.3937

0.3976

Package Body Length

12.900

13.000

13.100

0.5079

0.5118

0.5157

Pitch

[e]

1.000

0.0394

Ball (Lead) Count

Seating Plane Coplanarity

0.100

0.0039

Corner to Ball A1 Dista nc e Along D

1.400

1.500

1.600

0.0551

0.0591

0.0630

Corner to Ball A1 Dista nc e Along E

2.900

3.000

3.100

0.1142

0.1181

0.1220

Dimensions Table

Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size,
and are subject to change.

28F128J3, 28F640J3, 28F320J3

Datasheet

NOTES:

1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web

page at; www.intel.com/design/packtech/index.htm

2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page

at; www.intel.com/design/packtech/index.htm

Figure 23. 3 Volt Intel StrataFlash

Memory VF BGA Mechanical Specifications

Seating

Plane

Top View - Bump S ide Down

Bottom View - Ball Side Up

Ball A1

Corner

Ball A1

Corner

Note: Drawing not to scale

Side View

Millimeters

Inches

Symbol

M in

Nom

Max

Notes

Min

Nom

Max

Package Height

1.000

0.0394

Ball Height

0.150

0.0059

Package Body Thickness

0.665

0.0262

Ball (Lead) Width

0.325

0.375

0.425

0.0128

0.0148

0.0167

7.186

7.286

7.386

0.2829

0.2868

0.2908

Package Body Length

10.750

10.850

10.950

0.4232

0.4272

0.4311

Pitch

[e]

0.750

0.0295

Ball (Lead) Count

Seating Plane Coplanarity

0.100

0.0039

Corner to Ball A1 Dista nc e Along D

0.918

1.018

1.118

0.0361

0.0401

0.0440

Corner to Ball A1 Dista nc e Along E

3.450

3.550

3.650

0.1358

0.1398

0.1437

Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size,
and are subject to change.

Dimensions Table

28F128J3, 28F640J3, 28F320J3

Datasheet

Appendix E Design Considerations

E.1

Three-Line Output Control

The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,

CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:

Lowest possible memory power dissipation.

Complete assurance that data bus contention will not occur.

To use these control inputs efficiently, an address decoder should enable the device (see

Table 3

)

while OE# should be connected to all memory devices and the system's READ# control line. This

assures that only selected memory devices have active outputs while de-selected memory devices

are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent

unintended writes during system power transitions. POWERGOOD should also toggle during

system reset.

E.2

STS and Block Erase, Program, and Lock-Bit Configuration

Polling

STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a

hardware method of detecting block erase, program, and lock-bit configuration completion. It is

recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions

low after block erase, program, or lock-bit configuration commands and returns to High Z when

the WSM has finished executing the internal algorithm. For alternate configurations of the STS

signal, see the Configuration command.

STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the device is in block erase suspend (with programming

inactive), program suspend, or in reset/power-down mode.

E.3

Input Signal Transitions--Reducing Overshoots and

Undershoots When Using Buffers or Transceivers

As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory

devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory

specifications. (See "Absolute Maximum Ratings" on page 33.) Many buffer/transceiver vendors

now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.

Internal output-damping resistors diminish the nominal output drive currents, while still leaving

sufficient drive capability for most applications. These internal output-damping resistors help

reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-

drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When

considering a buffer/transceiver interface design to flash, devices with internal output-damping

resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For

additional information, please refer to AP-647, 5 Volt Intel StrataFlash

Memory Design Guide

(Order Number: 292205).

28F128J3, 28F640J3, 28F320J3

Datasheet

E.4

, V

PEN

, RP# Transitions

Block erase, program, and lock-bit configuration are not guaranteed if V

PEN

or V

falls outside of

the specified operating ranges, or RP#

. If RP# transitions to V

during block erase,

program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of

PLPH

+ t

PHRH

until the reset operation is complete. Then, the operation will abort and the device

will enter reset/power-down mode. The aborted operation may leave data partially corrupted after

programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase

and lock-bit configuration commands must be repeated after normal operation is restored. Device

power-off or RP# = V

clears the Status Register.

The CUI latches commands issued by system software and is not altered by V

PEN

, CE

, or

transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/

power-down mode, or after V

transitions below V

LKO

. V

must be kept at or above V

PEN

during V

transitions.

After block erase, program, or lock-bit configuration, even after V

PEN

transitions down to V

PENLK

the CUI must be placed in read array mode via the Read Array command if subsequent access to

the memory array is desired. V

PEN

must be kept at or below V

during V

PEN

transitions.

E.5

Power Dissipation

When designing portable systems, designers must consider battery power consumption not only

during device operation, but also for data retention during system idle time. Flash memory's

nonvolatility increases usable battery life because data is retained when system power is removed.

28F128J3, 28F640J3, 28F320J3

Datasheet

Appendix F Additional Information

Order Number

Document/Tool

298130

3 Volt Intel

StrataFlashTM Memory 28F128J3, 28F640J3, 28F320J3

Specification Update

298136

Intel

Persistent Storage Manager (IPSM) User's Guide

Software Manual

297833

Intel

Flash Data Integrator (FDI) User's Guide

Software Manual

290737

3 Volt Synchronous Intel StrataFlash

Memory 28F640K3, 28F640K18,

28F128K3, 28F128K18, 28F256K3, 28F256K18

292280

AP-732 3 Volt Intel StrataFlash

Memory J3 to K3/K18 Migration Guide

292237

AP-689 Using Intel

Persistent Storage Manager

290606

5 Volt Intel

StrataFlashTM MemoryI28F320J5 and 28F640J5

datasheet

297859

AP-677 Intel

StrataFlashTM Memory Technology

292222

AP-664 Designing Intel

StrataFlashTM Memory into Intel

Architecture

292221

AP-663 Using the Intel

StrataFlashTM Memory Write Buffer

292218

AP-660 Migration Guide to 3 Volt Intel

StrataFlashTM Memory

292204

AP-646 Common Flash Interface (CFI) and Command Sets

298161

Intel

Flash Memory Chip Scale Package User's Guide

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools.
3. For the most current information on Intel StrataFlash memory, visit our website at http://

developer.intel.com/design/flash/isf.

28F128J3, 28F640J3, 28F320J3

Datasheet

Appendix G Ordering Information

NOTE:

1. These speeds are for either the standard asynchronous read access times or for the first access of a page-

mode read sequence.

VALID COMBINATIONS

R C 2 8 F 1 2 8 J 3 A - 1 5

Package
E = 56-Lead TSOP
TE = 56-Lead TSOP
RC = 64-Ball Easy BGA
GE = 48-Ball VF BGA

Product line designator
for all Intel

Flash

products

Access Speed (ns)

128 Mbit = 120 or 150

64 Mbit = 115 or 120
32 Mbit = 110

Product Family
J = Intel

StrataFlash

memory,

2 bits-per-cell

Device Density
128 = x8/x16 (128 Mbit)
640 = x8/x16 (64 Mbit)
320 = x8/x16 (32 Mbit)

Voltage (V

PEN

)

3 = 3 V/3 V

Process Technology
A = 0.25 µm
C = 0.18 µm

56-Lead TSOP

64-Ball Easy BGA

48-Ball VF BGA

E28F320J3A-110

RC28F320J3A-110

GE28F320J3A-110

E28F640J3A-120

RC28F640J3A-120

GE28F320J3C-110

E28F128J3A-150

RC28F128J3A-150

GE28F640J3C-115

TE28F320J3C-110

RC28F320J3C-110

GE28F640J3C-120

TE28F640J3C-115

RC28F640J3C-115

TE28F640J3C-120

RC28F640J3C-120

TE28F128J3C-120

RC28F128J3C-120

TE28F128J3C-150

RC28F128J3C-150

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 28F320J3

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 28F320J3