82443GX Host Bridge

Datasheet

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

The 82443GX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available upon request.

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82443GX Host Bridge

Datasheet

iii

Intel 82443GX Features

The Intel

440GX AGPset is intended for the Pentium

II processor and Pentium

II XeonTM

processor platforms. The 82443GX Host Bridge provides a Host-to-PCI bridge, optimized
DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a
high performance, component level interconnect targeted at 3D graphics applications and is
based on a set of performance enhancements to PCI.

The I/O subsystem portion of the Intel

440GX AGPset platform is based on the 82371EB

(PIIX4E), a highly integrated version of the Intel's PCI-ISA bridge family.

Processor/System bus support

-- Optimized for Pentium

II and

Pentium

II XeonTM processors at

100 MHz system bus frequency

-- Supports full symmetric

Multiprocessor (SMP) Protocol for
up to two processors; I/O APIC
related buffer management support
(WSC# signal)

-- In-order transaction and dynamic

deferred transaction support

-- Supports GTL+ and AGTL+ bus

driver technology (gated GTL+
receivers for reduced power)

Integrated DRAM controller

-- 16 MB to 2 GB
-- Supports up to 4 double-sided

DIMMs (8 rows memory)

-- 64-bit data interface with ECC

support (SDRAM only)

-- Unbuffered and Registered

SDRAM (Synchronous) Support
(x-1-1-1 access @ 100 MHz)

-- Enhanced SDRAM Open Page

Architecture Support for 16-, 64-,
128-, and 256-Mbit* DRAM devices
with 2k, 4k and 8k page sizes

PCI bus interface

-- PCI Rev. 2.1, 3.3V and 5V, 33MHz

interface compliant

-- PCI Parity Generation Support
-- Data streaming support from PCI to

DRAM

-- Delayed Transaction support for

PCI-DRAM Reads

-- Supports concurrent CPU, AGP and

PCI transactions to main memory

AGP interface

-- Supports single AGP compliant

device (AGP-66/133 3.3V device)

-- AGP Specification Rev 1.0 compliant
-- AGP-data/transaction flow optimized

arbitration mechanism

-- AGP side-band interface for efficient

request pipelining without
interfering with the data streams

-- AGP-specific data buffering
-- Supports concurrent CPU, AGP and

PCI transactions to main memory

-- AGP high-priority transactions

("expedite") support

Power management functions

-- Stop Clock Grant and Halt special

cycle translation (host to PCI Bus)

-- "Deep Green" Desktop support for

system suspend/resume (i.e., DRAM
and power-on suspend)

-- SDRAM self-refresh power down

support in suspend mode

-- Independent, internal dynamic clock

gating reduces average power
dissipation

-- Static STOP CLOCK support
-- Power-on Suspend mode
-- Suspend to DRAM
-- ACPI compliant power management

Packaging/Voltage

-- 492 Pin BGA
-- 3.3V core & mixed 3.3V & GTL I/O

Supporting I/O Bridge

-- System Management Bus (SMB)

with support for DIMM Serial
Presence Detect (SPD)

-- PCI-ISA Bridge (PIIX4E)
-- Power Management Support
-- 3.3V core and mixed 5V, 3.3V I/O

and interface to the 2.5V CPU signals
via open-drain output buffers

The Intel 82443GX may contain design defects or errors known as errata which may cause the products to deviate from
published specifications. Current characterized errata are available on request.

* Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel's current plans are
to validate this feature in the second half of 1998 when 256-Mbit SDRAM devices are available.

82443GX Host Bridge

Datasheet

Contents

Architectural Overview ...............................................................................................1-1

Signal Description ......................................................................................................2-1

2.1

Host Interface Signals...................................................................................2-1

2.2

DRAM Interface ............................................................................................2-3

2.3

PCI Interface (Primary) .................................................................................2-4

2.4

Primary PCI Sideband Interface ...................................................................2-6

2.5

AGP Interface Signals...................................................................................2-6

2.6

Clocks, Reset, and Miscellaneous ................................................................2-8

2.7

Power-Up/Reset Strap Options.....................................................................2-9

Register Description...................................................................................................3-1

3.1

I/O Mapped Registers ...................................................................................3-2
3.1.1

CONFADD--Configuration Address Register..................................3-2

3.1.2

CONFDATA--Configuration Data Register .....................................3-3

3.1.3

PM2_CTL--ACPI Power Control 2 Control Register .......................3-4

3.2

PCI Configuration Space Access..................................................................3-4
3.2.1

Configuration Space Mechanism Overview .....................................3-5

3.2.2

Routing the Configuration Accesses to PCI or AGP ........................3-5

3.2.3

PCI Bus Configuration Mechanism Overview ..................................3-6
3.2.3.1 Type 0 Access ....................................................................3-6
3.2.3.2 Type 1 Access ....................................................................3-6

3.2.4

AGP Bus Configuration Mechanism Overview ................................3-6

3.2.5

Mapping of Configuration Cycles on AGP .......................................3-7

3.3

Host-to-PCI Bridge Registers (Device 0) ......................................................3-8
3.3.1

VID--Vendor Identification Register (Device 0).............................3-10

3.3.2

DID--Device Identification Register (Device 0) .............................3-10

3.3.3

PCICMD--PCI Command Register (Device 0) ..............................3-11

3.3.4

PCISTS--PCI Status Register (Device 0) .....................................3-12

3.3.5

RID--Revision Identification Register (Device 0) ..........................3-13

3.3.6

SUBC--Sub-Class Code Register (Device 0) ...............................3-13

3.3.7

BCC--Base Class Code Register (Device 0) ................................3-13

3.3.8

MLT--Master Latency Timer Register (Device 0)..........................3-14

3.3.9

HDR--Header Type Register (Device 0) .......................................3-14

3.3.10 APBASE--Aperture Base Configuration Register (Device 0)........3-14
3.3.11 SVID--Subsystem Vendor Identification Register (Device 0)........3-15
3.3.12 SID--Subsystem Identification Register (Device 0).......................3-16
3.3.13 CAPPTR--Capabilities Pointer Register (Device 0) ......................3-16
3.3.14 NBXCFG--NBX Configuration Register (Device 0) .......................3-16
3.3.15 DRAMC--DRAM Control Register (Device 0) ...............................3-19
3.3.16 PAM[6:0]--Programmable Attribute Map Registers

(Device 0).......................................................................................3-20

3.3.17 DRB[0:7]--DRAM Row Boundary Registers (Device 0) ................3-22
3.3.18 FDHC--Fixed DRAM Hole Control Register (Device 0) ................3-24
3.3.19 MBSC--Memory Buffer Strength Control Register

(Device 0).......................................................................................3-24

3.3.20 SMRAM--System Management RAM Control Register

(Device 0).......................................................................................3-28

82443GX Host Bridge

Datasheet

3.3.21 ESMRAMC--Extended System Management RAM Control Register

(Device 0) ......................................................................................3-29

3.3.22 RPS--SDRAM Row Page Size Register (Device 0)......................3-30
3.3.23 SDRAMC--SDRAM Control Register (Device 0) ..........................3-30
3.3.24 PGPOL--Paging Policy Register (Device 0) .................................3-32
3.3.25 PMCR--Power Management Control Register (Device 0) ............3-33
3.3.26 SCRR--Suspend CBR Refresh Rate Register (Device 0) ............3-34
3.3.27 EAP--Error Address Pointer Register (Device 0)..........................3-34
3.3.28 ERRCMD--Error Command Register (Device 0) ..........................3-35
3.3.29 ERRSTS--Error Status Register (Device 0)..................................3-36
3.3.30 ACAPID--AGP Capability Identifier Register (Device 0) ...............3-37
3.3.31 AGPSTAT--AGP Status Register (Device 0) ................................3-37
3.3.32 AGPCMD--AGP Command Register (Device 0)...........................3-38
3.3.33 AGPCTRL--AGP Control Register (Device 0) ..............................3-39
3.3.34 APSIZE--Aperture Size Register (Device 0) .................................3-40
3.3.35 ATTBASE--Aperture Translation Table Base Register

(Device 0) ......................................................................................3-40

3.3.36 MBFS--Memory Buffer Frequency Select Register

(Device 0) ......................................................................................3-41

3.3.37 BSPAD--BIOS Scratch Pad Register (Device 0) ..........................3-43
3.3.38 DWTC--DRAM Write Thermal Throttling Control Register

(Device 0) ......................................................................................3-43

3.3.39 DRTC--DRAM Read Thermal Throttling Control Register

(Device 0) ......................................................................................3-44

3.3.40 BUFFC--Buffer Control Register (Device 0) .................................3-45

3.4

PCI-to-PCI Bridge Registers (Device 1) .....................................................3-46
3.4.1

VID1--Vendor Identification Register (Device 1)...........................3-47

3.4.2

DID1--Device Identification Register (Device 1) ...........................3-47

3.4.3

PCICMD1--PCI-to-PCI Command Register (Device 1) ................3-48

3.4.4

PCISTS1--PCI-to-PCI Status Register (Device 1) ........................3-49

3.4.5

RID1--Revision Identification Register (Device 1) ........................3-49

3.4.6

SUBC1--Sub-Class Code Register (Device 1) .............................3-50

3.4.7

BCC1--Base Class Code Register (Device 1) ..............................3-50

3.4.8

MLT1--Master Latency Timer Register (Device 1)........................3-50

3.4.9

HDR1--Header Type Register (Device 1) .....................................3-51

3.4.10 PBUSN--Primary Bus Number Register (Device 1)......................3-51
3.4.11 SBUSN--Secondary Bus Number Register (Device 1) .................3-51
3.4.12 SUBUSN--Subordinate Bus Number Register (Device 1) ............3-52
3.4.13 SMLT--Secondary Master Latency Timer Register

(Device 1) ......................................................................................3-52

3.4.14 IOBASE--I/O Base Address Register (Device 1) ..........................3-52
3.4.15 IOLIMIT--I/O Limit Address Register (Device 1) ...........................3-52
3.4.16 SSTS--Secondary PCI-to-PCI Status Register (Device 1) ...........3-53
3.4.17 MBASE--Memory Base Address Register (Device 1)...................3-54
3.4.18 MLIMIT--Memory Limit Address Register (Device 1)....................3-54
3.4.19 PMBASE--Prefetchable Memory Base Address Register

(Device 1) ......................................................................................3-55

3.4.20 PMLIMIT--Prefetchable Memory Limit Address Register

(Device 1) ......................................................................................3-55

3.4.21 BCTRL--PCI-to-PCI Bridge Control Register (Device 1) ..............3-56

82443GX Host Bridge

Datasheet

vii

Functional Description ...............................................................................................4-1

4.1

System Address Map....................................................................................4-1
4.1.1

Memory Address Ranges ................................................................4-2
4.1.1.1 Compatibility Area ...............................................................4-3
4.1.1.2 Extended Memory Area ......................................................4-4
4.1.1.3 AGP Memory Address Range.............................................4-6
4.1.1.4 AGP DRAM Graphics Aperture...........................................4-6
4.1.1.5 System Management Mode (SMM) Memory Range...........4-6

4.1.2

Memory Shadowing .........................................................................4-8

4.1.3

I/O Address Space...........................................................................4-8

4.1.4

AGP I/O Address Mapping...............................................................4-8

4.1.5

Decode Rules and Cross-Bridge Address Mapping ........................4-9
4.1.5.1 PCI Interface Decode Rules ...............................................4-9
4.1.5.2 AGP Interface Decode Rules ..............................................4-9
4.1.5.3 Legacy VGA Ranges ........................................................4-10

4.2

Host Interface..............................................................................................4-10
4.2.1

Host Bus Device Support ...............................................................4-10

4.2.2

Symmetric Multiprocessor (SMP) Protocol Support.......................4-13

4.2.3

In-Order Queue Pipelining .............................................................4-13

4.2.4

Frame Buffer Memory Support (USWC) ........................................4-13

4.3

DRAM Interface ..........................................................................................4-14
4.3.1

DRAM Organization and Configuration..........................................4-14
4.3.1.1 Configuration Mechanism For DIMMS ..............................4-16

4.3.2

DRAM Address Translation and Decoding ....................................4-17

4.3.3

SDRAMC Register Programming ..................................................4-19

4.3.4

SDRAM Paging Policy ...................................................................4-19

4.4

PCI Interface ...............................................................................................4-19

4.5

AGP Interface .............................................................................................4-20

4.6

Data Integrity Support .................................................................................4-20
4.6.1

Data Integrity Mode Selection ........................................................4-20
4.6.1.1 Non-ECC (Default Mode of Operation) .............................4-20
4.6.1.2 EC Mode ...........................................................................4-20
4.6.1.3 ECC Mode ........................................................................4-21
4.6.1.4 ECC Generation and Error Detection/Correction and

Reporting ..........................................................................4-21

4.6.1.5 Optimum ECC Coverage ..................................................4-22

4.6.2

DRAM ECC Error Signaling Mechanism........................................4-22

4.6.3

CPU Bus Integrity ..........................................................................4-22

4.6.4

PCI Bus Integrity ............................................................................4-22

4.7

System Clocking .........................................................................................4-23

4.8

Power Management....................................................................................4-23
4.8.1

Overview ........................................................................................4-23

4.8.2

82443GX Reset .............................................................................4-26
4.8.2.1 CPU Reset ........................................................................4-27
4.8.2.2 CPU Clock Ratio Straps....................................................4-27
4.8.2.3 82443GX Straps ...............................................................4-28

4.8.3

Suspend Resume ..........................................................................4-28
4.8.3.1 Suspend Resume protocols ..............................................4-28
4.8.3.2 Suspend Refresh ..............................................................4-29

4.8.4

Clock Control Functions .................................................................4-29

4.8.5

SMRAM..........................................................................................4-30

viii

82443GX Host Bridge

Datasheet

Pinout and Package Information................................................................................5-1

5.1

82443GX Pinout ...........................................................................................5-1

5.2

Package Dimensions ....................................................................................5-8

Figures

1-1

Intel

440GX AGPset System Block Diagram .............................................1-2

3-1

82443GX PCI Bus Hierarchy ........................................................................3-5

3-2

SDRAM DIMMs and Corresponding DRB Registers ..................................3-23

4-1

Memory System Address Space ..................................................................4-2

4-2

Four-DIMM Configuration with FET switches .............................................4-15

4-3

Typical Intel

440GX AGPset System Clocking .........................................4-23

4-4

Reset CPURST# in a Desktop System When PCIRST# Asserted .............4-27

4-5

External Glue Logic Drives CPU Clock Ratio Straps ..................................4-28

5-1

82443GX Pinout (Top Viewleft side)...........................................................5-2

5-2

82443GX Pinout (Top Viewright side) ........................................................5-3

5-3

82443GX BGA Package Dimensions--Top and Side Views........................5-8

5-4

82443GX BGA Package Dimensions--Bottom Views..................................5-9

82443GX Host Bridge

Datasheet

Tables

2-1

Host Interface Signals...................................................................................2-1

2-2

Host Signals Not supported by the 82443GX ...............................................2-3

2-3

DRAM Interface Signals................................................................................2-3

2-4

Primary PCI Interface Signals.......................................................................2-4

2-5

Primary PCI Sideband Interface Signals.......................................................2-6

2-6

AGP Interface Signals...................................................................................2-6

2-7

Clocks, Reset, and Miscellaneous ................................................................2-8

2-8

Power Management Interface.......................................................................2-9

2-9

Reference Pins .............................................................................................2-9

2-10

Strapping Options .......................................................................................2-10

3-1

82443GX Register Map -- Device 0.............................................................3-8

3-2

Attribute Bit Assignment..............................................................................3-20

3-3

PAM Registers and Associated Memory Segments ...................................3-21

3-4

82443GX Configuration Space--Device 1..................................................3-46

4-1

Memory Segments and their Attributes.........................................................4-3

4-2

SMRAM Decoding ........................................................................................4-7

4-3

SMRAM Range Decode................................................................................4-7

4-4

SMRAM Decode Control...............................................................................4-7

4-5

Host Bus Transactions Supported By 82443GX.........................................4-11

4-6

Host Responses supported by the 82443GX..............................................4-12

4-7

Host Special Cycles with 82443GX ............................................................4-12

4-8

Data Bytes on DIMM Used for Programming DRAM Registers ..................4-16

4-9

Supported Memory Configurations .............................................................4-18

4-10

MA Muxing vs. DRAM Address Split...........................................................4-18

4-11

Programmable SDRAM Timing Parameters ...............................................4-19

4-12

Low Power Mode ........................................................................................4-25

4-13

AGPset Reset .............................................................................................4-26

4-14

Reset Signals..............................................................................................4-26

4-15

Suspend / Resume Events and Activities ...................................................4-28

5-1

82443GX Alphabetical BGA Pin List.............................................................5-4

5-2

82443GX Package Dimensions (492 BGA) ..................................................5-9

82443GX Host Bridge Datasheet

1-1

Architectural Overview

The Intel

440GX AGPset includes the 82443GX Host Bridge and the 82371EB PIIX4E for the

I/O subsystem. The 82443GX functions and capabilities include:

Support for single and dual Pentium

II processor and Pentium

II XeonTM processor

configurations

64-bit GTL+ and AGTL+ based System (Host) Bus Interface

32-bit Host address Support

64-bit Main Memory Interface with optimized support for SDRAM at 100 MHz

32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter

AGP Interface (AGP) with 133 MHz data transfer capability configurable as a Secondary PCI
Bus

Extensive Data Buffering between all interfaces for high throughput and concurrent operations

"Deep Green" Desktop power management support

Figure 1-1 shows a block diagram of a typical platform based on the Intel

440GX AGPset. The

82443GX host bus interface supports up to two Pentium II processors or two Pentium II XeonTM
processors at 100 MHz bus frequency. The physical interface design is based on the GTL+
specification optimized for the desktop. The 82443GX provides an optimized 64-bit DRAM
interface. This interface is implemented as a 3.3V-only interface that supports only 3V DRAM
technology. Two copies of the MA, and CS# signals drive a maximum of two DIMMs each;
providing unbuffered high performance at 100 MHz. The 82443GX provides interface to PCI
operating at 33 MHz. This interface implementation is compliant with PCI Rev 2.1 Specification.
The 82443GX AGP interface implementation is based on Rev 1.0 of the AGP Specification. The
AGP interface supports 133 MHz data transfer rates.

The 82443GX is designed to support the PIIX4E I/O bridge. PIIX4E is a highly integrated
multifunctional component supporting the following functions and capabilities:

PCI Rev 2.1 compliant PCI-ISA Bridge with support for both 3.3V and 5V 33 MHz PCI
operations

Deep Green Desktop Power Management Support

Enhanced DMA controller and Interrupt Controller and Timer functions

Integrated IDE controller with Ultra DMA/33 support

USB host interface with support for 2 USB ports

System Management Bus (SMB) with support for DIMM Serial PD

Support for an external I/O APIC component

Architectural Overview

1-2

82443GX Host Bridge Datasheet

Host Interface

The Pentium

II processor and Pentium

II XeonTM processor support a second level cache via a

cache bus interface. All control for the L2 cache is handled by the processor. The 82443GX
provides bus control signals and address paths for transfers between the processors system bus
(host bus), PCI bus, AGP and main memory. The 82443GX supports a 4-deep in-order queue (i.e.,
supports pipelining of up to 4 outstanding transaction requests on the host bus). Due to the system
concurrency requirements, along with support for pipelining of address requests from the host bus,
the 82443GX supports request queuing for all three interfaces (Host, AGP and PCI).

Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space. Host-initiated
memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable memory space) or
DRAM (including AGP aperture memory). For memory cycles (host, PCI or AGP initiated) that
target the AGP aperture space in DRAM, the 82443GX translates the address using the AGP
address translation table. Other host cycles forwarded to AGP are defined by the AGP address map.

PCI and AGP initiated cycles that target the AGP graphics aperture are also translated using the
AGP aperture translation table. AGP-initiated cycles that target the AGP graphics aperture mapped
in main memory do not require a snoop cycle on the host bus, since the coherency of data for that
particular memory range will be maintained by the software.

Figure 1-1. Intel

440GX AGPset System Block Diagram

sys_blk.vsd

Video BIOS

System Bus

82443GX

Host Bridge

Main

Memory

Pentium

II or

Pentium

XeonTM Processor

3.3V SDRAM

Support

2X AGP Bus

Graphics

Device

Display

ISA Bus

ISA Slots

System BIOS

System MGMT (SM) Bus

2 IDE Ports

(Ultra DMA/33)

2 USB

Ports

USB

APIC

82371EB

(PIIX4E)

(PCI-to-ISA

Bridge)

Primary PCI Bus

(PCI Bus #0)

PCI Slots

Encoder

Graphics

Local Memory

Video
- DVD
- Camera
- VCR

- VMI
- Video Capture

100 MHz

Pentium

II or

Pentium

XeonTM Processor

82443GX Host Bridge Datasheet

1-3

Architectural Overview

DRAM Interface

The 82443GX integrates a DRAM controller that supports a 64-bit main memory interface. The
DRAM controller supports the following features:

DRAM type: Synchronous DRAM (SDRAM) controller optimized for dual/quad-bank
SDRAM organization on a row by row basis

Memory Size: 16 MB to 2 GB with eight memory rows

Addressing Type: Asymmetrical addressing

Memory Modules supported: Single and double-sided 3.3V DIMMs

DRAM device technology: 16 Mbit, 64 Mbit, 128 Mbit, and 256 Mbit

DRAM Speed: 100 MHz synchronous memory (SDRAM).

The Intel

440GX AGPset also provides DIMM plug-and-play support via Serial Presence Detect

(SPD) mechanism using the SMBus interface. The 82443GX provides optional data integrity
features including ECC in the memory array. During reads from DRAM, the 82443GX provides
error checking and correction of the data. The 82443GX supports multiple-bit error detection and
single-bit error correction when ECC mode is enabled and single/multi-bit error detection when
correction is disabled. During writes to the DRAM, the 82443GX generates ECC for the data on a
QWord basis. Partial QWord writes require a read-modify-write cycle when ECC is enabled.

AGP Interface

The 82443GX AGP implementation is compatible with the following:

The Accelerated Graphics Port Specification, Rev 1.0

Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96)

The 82443GX supports only a synchronous AGP interface coupling to the 82443GX core
frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using
133 MHz AGP compliant devices).

PCI Interface

The 82443GX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to
five external PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM
interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec
for streaming writes.

System Clocking

The 82443GX operates the host interface, SDRAM, and core at 100 MHz only; PCI at
33 MHz; and AGP at 66/133 MHz.

I/O APIC

I/O APIC is used to support dual processors as well as enhanced interrupt processing in the single
processor environment. The 82443GX supports an external status output signal that can be used to
control synchronization of interrupts in configurations that use PIIX4E with stand-alone I/O APIC
component.

Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel's current plans are to validate this feature
in the second half of 1998 when 256-Mbit SDRAM devices are available.

82443GX Host Bridge Datasheet

2-1

Signal Description

S i g n a l D e s c r i p t i o n

This chapter provides a detailed description of 82443GX signals. The signals are arranged in
functional groups according to their associated interface.

The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When "#" is not present after the signal name the signal is
asserted when at the high voltage level.

The following notations are used to describe the signal type:

Input pin

Output pin

Open Drain Output pin. This pin requires a pullup to the VCC of the processor core

I/OD

Input / Open Drain Output pin. This pin requires a pullup to the VCC of the processor
core

I/O

Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal:

GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete

details

PCI

PCI bus interface signals. These signals are compliant with the PCI 3.3V and 5.0V
Signaling Environment DC and AC Specifications

AGP

AGP interface signals. These signals are compatible with AGP 3.3V Signaling
Environment DC and AC Specifications

CMOS The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V only.

2.1

Host Interface Signals

Table 2-1. Host Interface Signals (Sheet 1 of 2)

Name

Type

Description

CPURST#

GTL+

CPU Reset. The CPURST# pin is an output from the 82443GX. The 82443GX
generates this signal based on the PCIRST# input (from PIIX4E) and also the
SUSTAT# pin in mobile mode. The CPURST# allows the CPUs to begin execution in
a known state.

A[31:3]#

I/O

GTL+

Address Bus: A[31:3]# connect to the CPU address bus. During CPU cycles, the
A[31:3]# are inputs.

HD[63:0]#

I/O

GTL+

Host Data: These signals are connected to the CPU data bus. Note that the data
signals are inverted on the CPU bus.

Signal Description

2-2

82443GX Host Bridge Datasheet

NOTE:

1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding

table highlights 82443GX specific uses of these signals.

ADS#

I/O

GTL+

Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two
cycles of a request phase.

BNR#

I/O

GTL+

Block Next Request: Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the CPU bus pipeline depth.

BPRI#

GTL+

Priority Agent Bus Request: The 82443GX is the only Priority Agent on the CPU
bus. It asserts this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was asserted.

BREQ0#

GTL+

Symmetric Agent Bus Request: Asserted by the 82443GX when CPURST# is
asserted to configure the symmetric bus agents. BREQ0# is negated 2 host clocks
after CPURST# is negated.

DBSY#

I/O

GTL+

Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.

DEFER#

GTL+

Defer: The 82443GX generates a deferred response as defined by the rules of the
82443GX's dynamic defer policy. The 82443GX also uses the DEFER# signal to
indicate a CPU retry response.

DRDY#

I/O

GTL+

Data Ready: Asserted for each cycle that data is transferred.

HIT#

I/O

GTL+

Hit: Indicates that a caching agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.

HITM#

I/O

GTL+

Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line. Also
driven in conjunction with HIT# to extend the snoop window.

HLOCK#

GTL+

Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#,
until the negation of HLOCK# must be atomic, i.e. no PCI or AGP snoopable access
to DRAM is allowed when HLOCK# is asserted by the CPU.

HREQ[4:0]#

I/O

GTL+

Request Command: Asserted during both clocks of request phase. In the first clock,
the signals define the transaction type to a level of detail that is sufficient to begin a
snoop request. In the second clock, the signals carry additional information to define
the complete transaction type. The transactions supported by the 82443GX Host
Bridge are defined in the Host Interface section of this document.

HTRDY#

I/O

GTL+

Host Target Ready: Indicates that the target of the CPU transaction is able to enter
the data transfer phase.

RS[2:0]#

I/O

GTL+

Response Signals: Indicates type of response according to the following the table:

RS[2:0]

Response type

000

Idle state

001

Retry response

010 Deferred

response

011

Reserved (not driven by 82443GX)

100

Hard Failure (not driven by 82443GX)

101

No data response

110

Implicit Writeback

111

Normal data response

Table 2-1. Host Interface Signals (Sheet 2 of 2)

Name

Type

Description

82443GX Host Bridge Datasheet

2-3

Signal Description

Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel

440GX

AGPset.

2.2

DRAM Interface

Table 2-2. Host Signals Not supported by the 82443GX

Signal

Function

Not Supported By 82443GX

A[35:32]#

Address

Extended addressing (over 4 GB)

AERR#

Address Parity Error

Parity protection on address bus

AP[1:0]#

Address Parity

Parity protection on address bus

BINIT#

Bus Initialization

Checking for bus protocol violation and protocol recovery mechanism

DEP[7:0]#

Data Bus ECC/Parity

Enhanced data bus integrity

IERR#

Internal Error

Direct internal error observation via IERR# pin

INIT#

Soft Reset

Implemented by PIIX4E, BIST supported by external logic.

BERR#

Bus Error

Unrecoverable error without a bus protocol violation

RP#

Request Parity

Parity protection on ADS# and PREQ[4:0]#

RSP#

Response Parity
Signal

Parity protection on RS[2:0]#

BP[3:2]#

BreakPoint

Breakpoint status

BPM[1:0]#

BreakPoint Monitor

Breakpoint and performance monitor

Table 2-3. DRAM Interface Signals (Sheet 1 of 2)

Name

Type

Description

CSA[7:0]#

/CSB[7:0]#

CMOS

Chip Select (SDRAM): These pins perform the function of selecting the
particular SDRAM components during the active state.

Note that there are 2 copies of CS# per physical memory row to improve the
loading.

DQMA[7:0]

CMOS

Input/Output Data Mask A-side: These pins control A half of the memory array
and act as synchronized output enables during read cycles and as a byte enables
during write cycles.

DQMB[1,5]

CMOS

Input/Output Data Mask B-side (SDRAM): The same function as the
corresponding signals for the A side (DQMAx). These signals are used to reduce
the loading in an ECC configuration.

GCKE

CMOS

Global CKE: Global CKE is used in a 4 DIMM configuration requiring power
down mode for the SDRAM. External logic must be used to implement this
function.

SRAS[B,A]#

CMOS

SDRAM Row Address Strobe: The SRAS[B,A]# signals are multiple copies of
the same logical SRASx signal (for loading purposes) used to generate SDRAM
command encoded on SRASx/SCASx/WE signals.

FENA

CMOS

FET Enable (FENA): FENA is used to select the proper MD path through the
FET switches in a 4 DIMM configuration.

SCAS[B,A]#

CMOS

SDRAM Column Address Strobe: The SCAS[B,A]# signals are multiple copies
of the same logical SCASx signal (for loading purposes) used to generate
SDRAM command encoded on SRASx/SCASx/WE signals.

Signal Description

2-4

82443GX Host Bridge Datasheet

2.3

PCI Interface (Primary)

MAA[14:0]

MAB[12:11]#

MAB[14,13,10]
MAB[9:0]#

CMOS

Memory Address(SDRAM): MAA[14:0] and MAB[14,13,12#,11#,10,9#:0#] are
used to provide the multiplexed row and column address to DRAM. There are two
sets of MA signals which drive a max. of 2 DIMMs each. MAB[12:11,9:0]# are
inverted copies of MAA[12:11,9:0]. MAA[14,13,10] and MAB[14,13,10] are
identical copies. Each MAA/MAB[14:0] line has a programmable buffer strength to
optimize for different signal loading conditions.

WEA#

WEB#

CMOS

Write Enable Signa: WE# is asserted during writes to DRAM. The WE# lines
have a programmable buffer strength to optimize for different signal loading
conditions.

MD[63:0]

I/O

CMOS

Memory Data: These signals are used to interface to the DRAM data bus.

MECC[7:0]

I/O

CMOS

Memory ECC Data: These signals carry Memory ECC data during access to
DRAM.

Table 2-4. Primary PCI Interface Signals (Sheet 1 of 2)

Name

Type

Description

AD[31:0]

I/O

PCI

PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven by the 82443GX with FRAME# assertion, data is driven or received
in the following clocks. When the 82443GX acts as a target on the PCI Bus, the
AD[31:0] signals are inputs and contain the address during the first clock of FRAME#
assertion and input data (writes) or output data (reads) on subsequent clocks.

DEVSEL#

I/O

PCI

Device Select: Device select, when asserted, indicates that a PCI target device has
decoded its address as the target of the current access. The 82443GX asserts
DEVSEL# based on the DRAM address range or

AGP address range

being accessed

by a PCI initiator. As an input it indicates whether any device on the bus has been
selected.

FRAME#

I/O

PCI

Frame: FRAME# is an output when the 82443GX acts as an initiator on the PCI Bus.
FRAME# is asserted by the 82443GX to indicate the beginning and duration of an
access. The 82443GX asserts FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the
transaction is in the final data phase. FRAME# is an input when the 82443GX acts as
a PCI target. As a PCI target, the 82443GX latches the C/BE[3:0]# and the AD[31:0]
signals on the first clock edge on which it samples FRAME# active.

IRDY#

I/O

PCI

Initiator Ready: IRDY# is an output when 82443GX acts as a PCI initiator and an
input when the 82443GX acts as a PCI target. The assertion of IRDY# indicates the
current PCI Bus initiator's ability to complete the current data phase of the
transaction.

Table 2-3. DRAM Interface Signals (Sheet 2 of 2)

Name

Type

Description

82443GX Host Bridge Datasheet

2-5

Signal Description

NOTE:

1. All PCI interface signals conform to the PCI Rev 2.1 specification.

C/BE[3:0]#

I/O

PCI

Command/Byte Enable: PCI Bus Command and Byte Enable signals are
multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]#
define the bus command. During the data phase C/BE[3:0]# are used as byte
enables. The byte enables determine which byte lanes carry meaningful data. PCI
Bus command encoding and types are listed below.

C/BE[3:0]#

Command Type

0000

Interrupt Acknowledge

0001

Special Cycle

0010

I/O Read

0011

I/O Write

0100

Reserved

0101

Reserved

0110

Memory Read

0111

Memory Write

1000

Reserved

1001

Reserved

1010

Configuration Read

1011

Configuration Write

1100

Memory Read Multiple

1101

Reserved (Dual Address Cycle)

1110

Memory Read Line

1111

Memory Write and Invalidate

PAR

I/O

PCI

Parity: PAR is driven by the 82443GX when it acts as a PCI initiator during address
and data phases for a write cycle, and during the address phase for a read cycle. PAR
is driven by the 82443GX when it acts as a PCI target during each data phase of a
PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.

PLOCK#

I/O

PCI

Lock: PLOCK# indicates an exclusive bus operation and may require multiple
transactions to complete. When PLOCK# is asserted, non-exclusive transactions may
proceed. The 82443GX supports lock for CPU initiated cycles only. PCI initiated
locked cycles are not supported.

TRDY#

I/O

PCI

Target Ready: TRDY# is an input when the 82443GX acts as a PCI initiator and an
output when the 82443GX acts as a PCI target. The assertion of TRDY# indicates the
target agent's ability to complete the current data phase of the transaction.

SERR#

I/O

PCI

System Error: The 82443GX asserts this signal to indicate an error condition. The
SERR# assertion by the 82443GX is enabled globally via SERRE bit of the PCICMD
register. SERR# is asserted under the following conditions:

In an ECC configuration, the 82443GX asserts SERR#, for single bit (correctable)
ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled
via the ERRCMD control register. Any ECC errors received during initialization should
be ignored.

The 82443GX asserts SERR# for one clock when it detects a target abort during
82443GX initiated PCI cycle.

The 82443GX can also assert SERR# when a PCI parity error occurs during the
address or data phase.

The 82443GX can assert SERR# when it detects a PCI address or data parity
error on AGP.

The 82443GX can assert SERR# upon detection of access to an invalid entry in
the Graphics Aperture Translation Table.

The 82443GX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M
range or above TOM).

The 82443GX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture.

The 82443GX asserts SERR# for one clock when it detects a target abort during
82443GX initiated AGP cycle.

STOP#

I/O

PCI

Stop: STOP# is an input when the 82443GX acts as a PCI initiator and an output
when the 82443GX acts as a PCI target. STOP# is used for disconnect, retry, and
abort sequences on the PCI Bus.

Table 2-4. Primary PCI Interface Signals (Sheet 2 of 2)

Name

Type

Description

Signal Description

2-6

82443GX Host Bridge Datasheet

2.4

Primary PCI Sideband Interface

2.5

AGP Interface Signals

There are 17 new signals added to the normal PCI group of signals that together constitute the AGP
interface. The sections below describe their operation and use, and are organized in five groups:

AGP Addressing Signals

AGP Flow Control Signals

AGP Status Signals

AGP Clocking Signals - Strobes

PCI Signals

Table 2-5. Primary PCI Sideband Interface Signals

Name

Type

Description

PHOLD#

PCI

PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus
ownership. The 82443GX will flush and disable the CPU-to-PCI write buffers before
granting the PIIX4E the PCI bus via PHLDA#. This prevents bus deadlock between
PCI and ISA.

PHLDA#

PCI

PCI Hold Acknowledge: This signal is driven by the 82443GX to grant PCI bus
ownership to the PIIX4E after CPU-PCI post buffers have been flushed and disabled.

WSC#

CMOS

Write Snoop Complete. This signal is asserted active to indicate that all that the
snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is
complete and that is safe to send the APIC interrupt message.

PREQ[4:0]#

PCI

PCI Bus Request: PREQ[4:0]# are the PCI bus request signals used as inputs by the
internal PCI arbiter.

PGNT[4:0]#

PCI

PCI Grant: PGNT[4:0]# are the PCI bus grant output signals generated by the internal
PCI arbiter.

Table 2-6. AGP Interface Signals (Sheet 1 of 3)

Name

Type

Description

AGP Sideband Addressing Signals

PIPE#

AGP

Pipelined Read:

This signal is asserted by the current master to indicate a full width

address is to be queued by the target. The master queues one request each rising
clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are
queued across the AD bus. PIPE# is a sustained tri-state signal from

masters

(graphics controller)

and is an input to the 82443GX. Note that initial AGP designs

may not use PIPE#.

SBA[7:0]

AGP

Sideband Address: This bus

provides an additional bus to pass address and

command to the 82443GX from the AGP master. Note that, when sideband
addressing is disabled, these signals are isolated (no external/internal pull-ups are
required).

AGP Flow Control Signals

RBF#

AGP

Read Buffer Full.

This signal indicates if the master is ready to accept previously

requested low priority read data. When RBF# is asserted the 82443GX is not allowed
to return low priority read data to the AGP master on the first block. RBF# is only
sampled at the beginning of a cycle.

If the AGP master is always ready to accept return read data then it is not required to
implement this signal.

82443GX Host Bridge Datasheet

2-7

Signal Description

AGP Status Signals

ST[2:0]

AGP

Status

Bus: This bus provides information from the arbiter to a AGP Master on what

it may do. ST[2:0] only have meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.

000 Indicates that previously requested low priority read data is being returned to

the master.

001 Indicates that previously requested high priority read data is being returned to

the master.

010 Indicates that the master is to provide low priority write data for a previously

queued write command.

011 Indicates that the master is to provide high priority write data for a previously

queued write command.

100 Reserved

101 Reserved

110 Reserved

111 Indicates that the master has been given permission to start a bus transaction.

The master may queue AGP requests by asserting PIPE# or start a PCI
transaction by asserting FRAME#. ST[2:0] are always an output from the
82443GX and an input to the master.

AGP Clocking Signals - Strobes

ADSTB_A

I/O

AGP

AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm
external pull-up resistor.

ADSTB_B

I/O

AGP

AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This
signal requires an 8.2K ohm external pull-up resistor.

SBSTB

AGP

Sideband Strobe: THis signal provides timing for a side-band bus. This signal
requires an 8.2K ohm external pull-up resistor.

AGP FRAME# Protocol SIgnals (similar to PCI)

GFRAME#

I/O

AGP

Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted
by its own pull up resistor.

GIRDY#

I/O

AGP

Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant
master is ready to provide

all

write data for the current transaction. Once IRDY# is

asserted for a write operation, the master is not allowed to insert wait states. The
assertion of IRDY# for reads indicates that the master is ready to transfer to a
subsequent block (32 bytes) of read data. The master is

never

allowed to insert wait

states during the initial data transfer (32 bytes) of a read transaction. However, it may
insert wait states after each 32 byte block is transferred.

(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)

GTRDY#

I/O

AGP

Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant
target is ready to provide read data for the entire transaction (when the transfer size is
less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block
(32 bytes) of data when the transfer size is greater than 32 bytes. The target is
allowed to insert wait states after each block (32 bytes) is transferred on both read
and write transactions.

GSTOP#

I/O

AGP

Graphics Stop: Same as PCI. Not used by AGP.

GDEVSEL#

I/O

AGP

Graphics Device Select: Same as PCI. Not used by AGP.

GREQ#

AGP

Graphics Request: Same as PCI. (Used to request access to the bus to initiate a
PCI or AGP request.)

Table 2-6. AGP Interface Signals (Sheet 2 of 3)

Name

Type

Description

Signal Description

2-8

82443GX Host Bridge Datasheet

NOTE:

AGP Sideband Addressing Signals.

The above table contains two mechanisms to queue requests by

the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue
addresses the master is not allowed to queue addresses using the SBA bus. For example, during
configuration time, if the master indicates that it can use either mechanism, the configuration software will
indicate which mechanism the master will use. Once this choice has been made, the master will continue to
use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This
change of modes is not a dynamic mechanism but rather a static decision when the device is first being
configured after reset.

2. PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For

transactions on the AGP interface carried using PCI protocol these signals completely preserve PCI
semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6.

3. The LOCK# signal is not supported on the AGP interface (even for PCI operations).
4. PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI

transactions on the AGP Interface.

2.6

Clocks, Reset, and Miscellaneous

GGNT#

AGP

Graphics Grant: Same meaning as PCI but additional information is provided on
ST[2:0]. The additional information indicates that the selected master is the recipient
of previously requested read data (high or normal priority), it is to provide write data
(high or normal priority), for a previously queued write command or has been given
permission to start a bus transaction (AGP or PCI).

GAD[31:0]

I/O

AGP

Graphics Address/Data: Same as PCI.

GC/BE[3:0]#

I/O

AGP

Graphics Command/Byte Enables: Slightly different meaning. Provides command
information (different commands than PCI) when requests are being queued when
using PIPE#. Provide valid byte information during AGP write transactions and are
not used during the return of read data.

GPAR

I/O

AGP

Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI
transactions as defined by the PCI specification.

Table 2-6. AGP Interface Signals (Sheet 3 of 3)

Name

Type

Description

Table 2-7. Clocks, Reset, and Miscellaneous (Sheet 1 of 2)

Name

Type

Description

HCLKIN

CMOS

Host Clock In: This pin receives a buffered host clock. This clock is used by all of the
82443GX logic that is in the Host clock domain.

When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

PCLKIN

CMOS

PCI Clock In: This is a buffered PCI clock reference that is synchronously derived by
an external clock synthesizer component from the host clock. This clock is used by all
of the 82443GX logic that is in the PCI clock domain.

When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

DCLKO

CMOS

SDRAM Clock Out: 100 MHz SDRAM clock reference. It feeds an external buffer
clock device that produces multiple copies for the DIMMs.

DCLKWR

CMOS

SDRAM Write Clock: Feedback reference from the external SDRAM clock buffer.

PCIRST#

CMOS

PCI Reset: When asserted, this signal will reset the 82443GX logic. All PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.

When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

GCLKIN

CMOS

AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal.

82443GX Host Bridge Datasheet

2-9

Signal Description

2.7

Power-Up/Reset Strap Options

Table 2-10 is the list of all power-up options that are loaded into the 82443GX during cold reset.
The 82443GX is required to float all the signals connected to straps during cold reset and keep
them floated for a minimum of 4 host clocks after the end of cold reset sequence. Cold reset
sequence is performed when the 82443GX power is applied.

Note:

All signals used to select power-up strap options are connected to either internal pull-down or pull-
up resistors of minimum 50K ohms (maximum is 150K). That selects a default mode on the signal
during reset. To enable different modes, external pull ups or pull downs (the opposite of the internal

GCLKO

CMOS

AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used to feed
both the reference input pin on the 82443GX and the AGP compliant device.

CRESET#

CMOS

Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This signal is used
to control the multiplexer for the CPU strap signals. CRESET# is delayed from
CPURST# by two host clocks.

Note: This pin requires an external pull-up resistor. If not used, no pull up is required.

TESTIN#

CMOS

Test Input: This pin is used for manufacturing, and board level test purposes.

Note: This pin has an internal 50K ohm pull-up.

Table 2-8. Power Management Interface

Name

Type

Description

CLKRUN#

I/OD

CMOS

Primary PCI Clock Run: The 82443GX requests the central resource (PIIX4E) to
start or maintain the PCI clock by the assertion of CLKRUN#. The 82443GX tristates
CLKRUN# upon deassertion of PCIRST# (since CLK is running upon deassertion of
reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop,
Mobile requires (8.2k10K) pull-up. Otherwise, a 100 Ohm pull down is required.

SUSTAT#

CMOS

Suspend Status (from PIIX): SUSTAT# signals the system suspend state transition
from the PIIX4E. It is used to isolate the suspend voltage well and enter/exit DRAM
self-refresh mode. During POS/STR SUSTAT# is active.

GXPWROK

CMOS

GX Power OK: GXPWROK input must be connected to the PWROK signal that
indicates valid power is applied to the 82443GX.

Table 2-9. Reference Pins

Name

Description

GTLREF[B:A]

GTL Buffer voltage reference input

VTT[B:A]

GTL Threshold voltage for early clamps

VCC

Power pin @ 3.3V

VSS

Ground

REF5V

PCI 5V reference voltage (for 5V tolerant buffers)

AGPREF

External Input Reference

Table 2-7. Clocks, Reset, and Miscellaneous (Sheet 2 of 2)

Name

Type

Description

Signal Description

2-10

82443GX Host Bridge Datasheet

resistor) of approximately 10K ohm can be connected to particular signals. These pull up or pull
down resistors should be connected to the 3.3V power supply.

During normal operation of the 82443GX, including while it is in suspend mode, the paths from
GND or Vcc to internal strapping resistors are disabled to effectively disable the resistors. In these
cases, the MAB# lines are driven by the 82443GX to a valid voltage levels.

Note:

Note that when resuming from suspend, even while PCIRST# is active, the MAB# lines remain
driven by the 82443GX and the strapping latches maintain the value stored during the cold reset.

This first column in Table 2-10 lists the signal that is sampled to obtain the strapping option. The
second column shows which register the strapping option is loaded into. The third column is a
description of what functionality the strapping selects.

The GTL+ signals are connected to the VTT through the normal pull-ups. CPU bus straps
controlled by the 82443GX (e.g. A7# and A15#), are driven active at least six clocks prior to the
active-to-inactive edge of CPURST# and driven inactive four clocks after the active-to-inactive
edge of the CPURST#.

NOTE:

1. Proper strapping must be used to define logical values for these signals. Default value "0", or "1" provided by

the internal pull-up or pull-down resistor can be overridden by the external pull-up, or pull-down resistor.

Table 2-10. Strapping Options

Signal

Register

Name[bit]

Description

MAB13#

Reserved.

MAB12#

NBXCFG[13]

MAB12# is strapped to 1 for a host bus frequency of 100 MHz. Strapping
MAB12# to 0 is a reserved condition. An internal pull-down provides a default
setting of 0.

MAB11#

NBXCFG[2]

In-Order Queue Depth Enable: If MAB11# is strapped to 0 during the rising
edge of PCIRST#, then the 82442GX will drive A7# low during the CPURST#
deassertion. This forces the CPU bus to be configured for non-pipelined
operation.

If MAB11 is strapped to 1 (default), then the 82443GX does not drive the A7# low
during reset, and A7# is sampled in default non-driven state (i.e. pulled-up as far
as GTL+ termination is concerned) then the maximum allowable queue depth by
the CPU bus protocol is selected (i.e., 8).

Note that internal pull-up is used to provide pipelined bus mode as a default.

MAB10

Reserved.

MAB9#

PMCR[1]

AGP Disable: When strapped to a 1, the AGP interface is disabled, all AGP
signals are tri-stated and isolated. When strapped to a 0 (default), the AGP
interface is enabled.

When MMCONFIG is strapped active, we require that AGP_DISABLE is also
strapped active. When MMCONFIG is strapped inactive, AGP_DISABLE can be
strapped active or inactive but IDSEL_REDIRECT (bit 16 in NBXCFG register)
must never be activated.

This signal has an internal pull-down resistor.

MAB[8:6]

Reserved.

A[7]#

none

In-order Queue Depth Status: The value on A[7]# sampled at the rising edge of
CPURST# reflects if the IOQD is set to 1 or maximum allowable by the CPU bus.

82443GX Host Bridge Datasheet

3-1

R e g i s t e r D e s c r i p t i o n

The 82443GX contains two sets of software accessible registers, accessed via the Host CPU I/O
address space:

1. Control registers that are I/O mapped into the CPU I/O space. These registers control access to

PCI and AGP configuration space.

2. Internal configuration registers residing within the 82443GX, partitioned into two logical

device register sets ("logical" since they reside within a single physical device). The first
register set is dedicated to Host-to-PCI Bridge functionality. This set (device 0) controls PCI
interface operations, DRAM configuration, and other chip-set operating parameters and
optional features. The second register set (device 1) is dedicated to Host-to-AGP Bridge
functions (controls AGP interface configurations and operating parameters).

The following nomenclature is used for register access attributes.

The 82443GX supports PCI configuration space access using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.

The 82443GX internal registers (both I/O Mapped and Configuration registers) are accessible by
the Host CPU. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities,
with the exception of CONFADD which can only be accessed as a Dword. All multi-byte numeric
fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the
field).

Some of the 82443GX registers described in this section contain reserved bits. These bits are
labeled "Reserved". Software must deal correctly with fields that are reserved. On reads, software
must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit positions are
preserved. That is, the values of reserved bit positions must first be read, merged with the new
values for other bit positions and then written back.

Note:

Software does not need to perform read, merge, write operation for the configuration address
register.

In addition to reserved bits within a register, the 82443GX contains address locations in the
configuration space of the Host-to-PCI Bridge entity that are marked either "Reserved" or "Intel
Reserved". The 82443GX responds to accesses to "Reserved" address locations by completing the
host cycle. When a "Reserved" register location is read, a zero value is returned. ("Reserved"
registers can be 8-, 16-, or 32-bit in size). Writes to "Reserved" registers have no effect on the

Read Only. If a register is read only, writes to this register have no effect.

R/W

Read/Write. A register with this attribute can be read and written

R/WC

Read/Write Clear. A register bit with this attribute can be read and written.
However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has
no effect.

R/WO

Read/Write Once. A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only.

R/WL

Read/Write/Lock. This register includes a lock bit. Once the lock bit has been set to
1, the register becomes read only.

3-2

82443GX Host Bridge Datasheet

82443GX. Registers that are marked as "Intel Reserved" must not be modified by system software.
Writes to "Intel Reserved" registers may cause system failure. Reads to "Intel Reserved" registers
may return a non-zero value. Software should not write to reserved configuration locations in the
device-specific region (above address offset 3Fh)

Upon reset, the 82443GX sets its internal configuration registers to predetermined default states.
However, there are a few exceptions to this rule.

1. When a reset occurs during the POS/STR state, several configuration bits are not reset to their

default state. These bits are noted in the following register description.

2. Some register values at reset are determined by external strapping options.

The default state represents the minimum functionality feature set required to successfully bring up
the system. Hence, it does not represent the optimal system configuration. It is the responsibility of
the system initialization software (usually BIOS) to properly determine the DRAM configurations,
operating parameters and optional system features that are applicable, and to program the
82443GX registers accordingly.

3.1

I/O Mapped Registers

The 82443GX contains three registers that reside in the CPU I/O address space - the Configuration
Address (CONFADD) Register, the Configuration Data (CONFDATA) Register, and the Power
Management Control Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window.

3.1.1

CONFADD--Configuration Address Register

I/O Address:

0CF8h Accessed as a Dword

Default Value:

00000000h

Access:

Read/Write

Size:

32 bits

CONFADD is a 32 bit register accessed only when referenced as a Dword. A Byte or Word
reference will "pass through" the Configuration Address Register onto the PCI bus as an I/O cycle.
The CONFADD register contains the Bus Number, Device Number, Function Number, and
Register Number for which a subsequent configuration access is intended.

82443GX Host Bridge Datasheet

3-3

3.1.2

CONFDATA--Configuration Data Register

I/O Address:

0CFCh

Default Value:

00000000h

Access:

Read/Write

Size:

32 bits

CONFDATA is a 32 bit read/write window into configuration space. The portion of configuration
space that is referenced by CONFDATA is determined by the contents of CONFADD.

Bit

Descriptions

Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are
enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled.

30:24

Reserved.

23:16

Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle
is either the 82443GX or the PCI Bus that is directly connected to the 82443GX, depending on the
Device Number field. A type 0 Configuration Cycle is generated on PCI if the Bus Number is
programmed to 00h and the 82443GX is not the target. If the Bus Number is non-zero a type 1
configuration cycle is generated on PCI or AGP with the Bus Number mapped to AD[23:16] during
the address phase.

15:11

Device Number. This field selects one agent on the PCI bus selected by the Bus Number. During
a Type 1 Configuration cycle this field is mapped to AD[15:11]. During a Type 0 Configuration
Cycle this field is decoded and one bit among AD[31:11] is driven to a 1. The 82443GX is always
Device Number 0 for the Host-to-PCI bridge entity and Device Number 1 for the Host- AGP entity.
Therefore, the 82443GX internally references the AD11 and AD12 pins as corresponding IDSELs
for the respective devices during PCI configuration cycles. NOTE: The AD11 and AD12 must not
be connected to any other PCI bus device as IDSEL signals.

10:8

Function Number. This field is mapped to AD[10:8] during PCIx configuration cycles. This allows
the configuration registers of a particular function in a multi-function device to be accessed. The
82443GX only responds to configuration cycles with a function number of 000b; all other function
number values attempting access to the 82443GX (Device Number = 0 and 1, Bus Number = 0)
will generate a master abort.

7:2

Register Number. This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2]
during PCI configuration cycles.

1:0

Reserved.

Bit

Descriptions

31:0

Configuration Data Window (CDW). If bit 31 of CONFADD is 1 any I/O reference that falls in the
CONFDATA I/O space will be mapped to configuration space using the contents of CONFADD.

3-4

82443GX Host Bridge Datasheet

3.1.3

PM2_CTL--ACPI Power Control 2 Control Register

I/O Address:

0022h

Default Value:

00h

Access:

Read/Write

Size:

8 bits

This register is used to disable both the PCI and AGP arbiters in the 82443GX to prevent any
external bus masters from acquiring the PCI or AGP bus. Any currently running PCI cycles will
terminate properly.

Accesses to this register are controlled by the Power Management Control Register (Offset 7Ah).
When bit 6 of the PMCR is set to `1', the ACPI Register at I/O location 0022h is enabled. When bit
6 is set to `0', I/O accesses to location 0022h are forwarded to PCI or AGP (if within programmable
IO range).

3.2

PCI Configuration Space Access

The 82443GX implementation manifests two PCI devices within a single physical component
body:

Device 0 = Host-to-PCI Bridge = PCI bus #0 interface, Main Memory Controller, Graphics
Aperture controller, 82443GX specific AGP control registers.

Device 1 = Host-to-AGP interface = "Virtual" PCI-to-PCI Bridge, including AGP address
space mapping, normal PCI interface, and associated AGP sideband signal control.

Corresponding configuration registers for both devices are mapped as devices residing on PCI (bus
0). Configuration register layout and functionality for the Device #0 should be inspected carefully,
as new features added to the 82443GX initiated a reasonable level of change relative to other
proliferation's of the Pentium

Pro processor AGPsets (i.e. 440FX, 440LX). Configuration

registers of the 82443GX Device #1 are based on the normal configuration space template of a
PCI-to-PCI Bridge as described in the PCI to PCI Bridge Architecture Specification.

Figure 3-1 shows the PCI bus hierarchy for the 82443GX. In the PCI bus hierarchy, the primary
PCI bus is the highest level bus in the hierarchy and is PCI bus #0. The PCI-to-PCI bridge function
provides access to the AGP/PCI bus 0. This bus is below the primary bus in the PCI bus hierarchy
and is represented as PCI Bus #1.

Bit

Description

7:1

Reserved

Primary PCI and AGP Arbiter Request Disable (ARB_DIS). When this bit is set to 1, the
82443GX will not respond to any PCI REQ# signals, AGP requests, or PHOLD# from PIIX4E going
active until this bit is set back to 0. Only External AGP and PCI requests are masked from the
arbiters. If the PIIX is in passive release mode, masking will not occur until an active release is seen
via PHLDA# assertion. This prevents possible deadlock.

ARB_DIS has no effect on AGP side band signals or AGP data transfer requests.

82443GX Host Bridge Datasheet

3-5

3.2.1

Configuration Space Mechanism Overview

The 82443GX supports two bus interfaces: PCI (referenced as Primary PCI) and AGP (referenced
as AGP). The AGP interface is treated as a second PCI bus from the configuration point of view.
The following sections describe the configuration space mapping mechanism associated with both
buses.

Note:

The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register.
When the AGP_DIS bit (PMCR[1]) is set to 0, the configuration space for device #1 is enabled, and
the registers for device #1 are accessible through the configuration mechanism defined below.
When the AGP_DIS bit (PMCR[1]) is set to 1, the configuration space for device #1 is disabled.
All configuration cycles (reads and writes) to device #1 of bus 0 will cause the master abort status
bit for device #0/ bus 0 to be set. Configuration read cycles will return data of all 1's. Configuration
write cycles will have no effect on the registers.

3.2.2

Routing the Configuration Accesses to PCI or AGP

Routing of configuration accesses to AGP is controlled via PCI-to-PCI bridge normal mechanism
using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS
NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-to-AGP internal
"virtual" PCI-to-PCI bridge device. Detailed description of the mechanism for translating CPU I/O
bus cycles to configuration cycles on one of the two buses is described below.

To distinguish between PCI configuration cycles targeting the two logical device register sets
supported in the 82443GX, this document refers to the Host-to-PCI bridge PCI interface as PCI and
the Host- AGP PCI interface as AGP.

Figure 3-1. 82443GX PCI Bus Hierarchy

CPU

Host-to-PCI Bridge

Virtual Host-to-PCI Bridge

AGP Device

PCI Bus #0

82443GX

Host Bridge

PCI Bus #1 AGP

3-6

82443GX Host Bridge Datasheet

3.2.3

PCI Bus Configuration Mechanism Overview

The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space: Configuration Read
and Configuration Write. Memory and I/O spaces are supported directly by the CPU.
Configuration space is supported by a mapping mechanism implemented within the chip-set. The
PCI specification defines two mechanisms to access configuration space, Mechanism #1 and
Mechanism #2. The 82443GX supports only Mechanism #1.

The configuration access mechanism makes use of the CONFADD Register and CONFDATA
Register. To reference a configuration register a Dword I/O write cycle is used to place a value into
CONFADD that specifies the PCI bus, the device on that bus, the function within the device, and a
specific configuration register of the device function being accessed. CONFADD[31] must be 1 to
enable a configuration cycle. CONFDATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFADD. Any read or write to CONFDATA will
result in the Host Bridge translating CONFADD into a PCI configuration cycle.

3.2.3.1

Type 0 Access

If the Bus Number field of CONFADD is 0, a Type 0 Configuration cycle is performed on PCI (i.e.
bus #0). CONFADD[10:2] is mapped directly to AD[10:2]. The Device Number field of
CONFADD is decoded onto AD[31:11]. The Host-to-PCI Bridge entity within the 82443GX is
accessed as Device #0 on the PCI bus segment. The Host- /AGP Bridge entity within the 82443GX
is accessed as Device #1 on the PCI bus segment. To access Device #2, the 82443GX will assert
AD13, for Device #3 will assert AD14, and so forth up to Device #20 for which will assert AD31.
Only one AD line is asserted at a time. All device numbers higher than 20 cause a type 0
configuration access with no IDSEL asserted, which will result in a Master Abort.

3.2.3.2

Type 1 Access

If the Bus Number field of CONFADD is non-zero, then a Type 1 Configuration cycle is performed
on PCI bus (i.e. bus #0). CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to
01 to indicate a Type 1 Configuration cycle. All other lines are driven to 0.

3.2.4

AGP Bus Configuration Mechanism Overview

This mechanism is compatible with PCI mechanism #1 supported for the PCI bus as defined above.
The configuration mechanism is the same for both accessing AGP or PCI-only devices attached to
the AGP interface.

82443GX Host Bridge Datasheet

3-7

3.2.5

Mapping of Configuration Cycles on AGP

From the AGPset configuration perspective, AGP is seen as another PCI bus interface residing on a
Secondary Bus side of the "virtual" PCI-to-PCI bridge referred to as the 82443GX Host- AGP
bridge. On the Primary bus side, the "virtual" PCI-to-PCI bridge is attached to the BUS #0 referred
to in this document as the PCI interface. The "virtual" PCI-to-PCI bridge entity is used to map
Type #1 PCI Bus Configuration cycles on PCI onto Type #0 or Type #1 configuration cycles on the
AGP interface.

Type 1 configuration cycles on PCI that have a BUS-NUMBER that matches the SECONDARY-
BUS-NUMBER of the "virtual" PCI to PCI bridge will be translated into Type 0 configuration
cycles on the AGP interface. Type 1 configuration cycles on PCI that have a BUS-NUMBER that is
behind the "virtual" P2P bridge will be translated into Type 1 configuration cycles on the AGP
interface.

Note:

The PCI bus supports a total of 21 devices by mapping bits 15:11 of the CONFADD to the IDSEL
lines on AD[31:11]. For secondary PCI busses (including the AGP bus), only 16 devices are
supported by mapping bits 15:11 of the CONFADD to the IDSEL lines (AD[31:16]).

To prepare for mapping of the configuration cycles on AGP the initialization software will go
through the following sequence:

1. Scan all devices residing on the PCI bus (i.e., Bus #0) using Type 0 configuration accesses.

2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will

configure the secondary bus of the bridge with the appropriate number and scan further down
the hierarchy. This process will include the configuration of the "virtual" PCI-to-PCI Bridge
within the 82443GX used to map the AGP address space in a software specific manner.

3-8

82443GX Host Bridge Datasheet

3.3

Host-to-PCI Bridge Registers (Device 0)

Table 3-1 shows the 82443GX configuration space for device #0.

Table 3-1. 82443GX Register Map -- Device 0 (Sheet 1 of 2)

Address

Offset

Register

Symbol

Register Name

Default Value

Access

0001h

VID

Vendor Identification

8086h

0203h

DID

Device Identification

71A0h/71A2h

0405h

PCICMD

PCI Command Register

0006h

R/W

0607h

PCISTS

PCI Status Register

0210h/0200h

RO, R/WC

RID

Revision Identification

00h

Reserved

00h

0Ah

SUBC

Sub-Class Code

00h

0Bh

BCC

Base Class Code

06h

0Ch

Reserved

00h

0Dh

MLT

Master Latency Timer

00h

R/W

0Eh

HDR

Header Type

00h

1013h

APBASE

Aperture Base Address

00000008h

R/W,RO

142Bh

Reserved

00h

2C2Dh

SVID

Subsystem Vendor Identification

00h

R/WO

2E2Fh

SID

Subsystem Identification

00h

R/WO

3033h

Reserved

00h

34h

CAPPTR

Capabilities Pointer

A0h/00h

354Fh --

Reserved

00h

5053h

NBXCFG

440GX Configuration

[0000h]:[00S0_00
00_000S_0S00b]

R/W

5456h

Reserved

00h

57h

DRAMC

DRAM Control

00S0_0000b

R/W

58h

Intel Reserved

03h

595Fh

PAM[6:0]

Programmable Attribute Map (7 registers)

00h

R/W

6067h

DRB[7:0]

DRAM Row Boundary (8 registers)

01h

R/W

68h

FDHC

Fixed DRAM Hole Control

00h

R/W

696Eh

MBSC

Memory Buffer Strength Control

0000-0000-0000h

R/W

6F70h

Reserved

00h

71h

Intel Reserved

1Fh

72h

SMRAM

System Management RAM Control

02h

R/W

73h

ESMRAMC

Extended System Management RAM Control.

38h

R/W

7475h

RPS

SDRAM Row Page Size

0000h

R/W

7677h

SDRAMC

SDRAM Control Register

0000h

R/W

7879h

PGPOL

Paging Policy Register

00h

R/W

7Ah

PMCR

Power Management Control Register

0000_S0S0b

R/W

7B7Ch

SCRR

Suspend CBR Refresh Rate Register

0038h

R/W

7D7Fh

Reserved

00h

82443GX Host Bridge Datasheet

3-9

NOTES:

1. The `S' symbol represents the strapping option.
2. Write operations must not be attempted to the Intel Reserved registers.

8083h

EAP

Error Address Pointer Register

00000000h

RO, R/WC

848Fh

Reserved

00h

90h

ERRCMD

Error Command Register

80h

R/W

9192h

ERRSTS

Error Status Register

0000h

R/WC, RO

93h

Reserved

00h

R/W

9497h

Intel Reserved

00006104h

9899h

Intel Reserved

0500h

9Ah

Intel Reserved

00h

9B9Fh

Reserved

A0A3h

ACAPID

AGP Capability Identifier

00100002h
00000000h

A4A7h

AGPSTAT

AGP Status Register

1F000203h

A8ABh

AGPCMD

AGP Command Register

00000000h

ACAFh

Reserved

00h

B0B3h

AGPCTRL

AGP Control Register)

00000000h

R/W

B4h

APSIZE

Aperture Size Control Register

00h

R/W

B5B7h

Reserved

00h

B8BBh

ATTBASE

Aperture Translation Table

00000000h

R/W

BCh

Reserved

BDh

Reserved

BEBFh

Reserved

00h

C0C3h

Intel Reserved

00000000h

C4C7h

Intel Reserved

00000000h

C8h

Intel Reserved

18h

C9h

Intel Reserved

0Ch

CACCh

MBFS

Memory Buffer Frequency Select

000000h

R/W

CDCFh

Reserved

00h

D0D7h

BSPAD

BIOS Scratch Pad

00...00h

R/W

D8DFh

Intel Reserved

000....000h

E0E7h

DWTC

DRAM Write Thermal Throttling Control

000....000h

R/W/L

E8EFh

DRTC

DRAM Read Thermal Throttling Control

000....000h

R/W/L

F0F1h

BUFFC

Buffer Control Register

0000h

R/W/L

F2F7h

Intel Reserved

0000F800h

F8FBh

Intel Reserved

00000F20h

FCFFh

Intel Reserved

00000000h

Table 3-1. 82443GX Register Map -- Device 0 (Sheet 2 of 2)

Address

Offset

Register

Symbol

Register Name

Default Value

Access

3-10

82443GX Host Bridge Datasheet

3.3.1

VID--Vendor Identification Register (Device 0)

Address Offset:

0001h

Default Value:

8086h

Attribute:

Read Only

Size:

16 bits

The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identify any PCI device. Writes to this register have no
effect.

3.3.2

DID--Device Identification Register (Device 0)

Address Offset:

0203h

Default Value:

71A0h/71A2h

Attribute:

Read Only

Size:

16 bits

This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device. Writes to this register have no effect.

Bit

Description

15:0

Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h.

Bit

Description

15:0

Device Identification Number. This is a 16 bit value assigned to the 82443GX Host-to-PCI
Bridge Function #0.

71A0h = When the AGP_DIS bit (PMCR[1]) is set to 0, the DID =71A0h.

71A2h = When the AGP_DIS bit is set to 1, the DID = 71A2h.

82443GX Host Bridge Datasheet

3-11

3.3.3

PCICMD--PCI Command Register (Device 0)

Address Offset:

0405h

Default:

0006h

Access:

Read/Write

Size

16 bits

This 16-bit register provides basic control over the 82443GX PCI interface ability to respond to
PCI cycles. The PCICMD Register enables and disables the SERR# signal, 82443GX response to
PCI special cycles, and enables and disables PCI bus master accesses to main memory.

Bit

Descriptions

15:10

Reserved.

Fast Back-to-Back. Fast back-to-back cycles to different PCI targets are not implemented by the
82443GX.

0 = Hardwired to 0.

SERR# Enable (SERRE). Note that this bit only controls SERR# for the PCI bus. Device #1 has
its own SERRE bit to control error reporting for the bus conditions occurred on the AGP bus. Two
control bits are used in a logical OR manner to control SERR# pin driver.

1 = If this bit is set to a 1, the 82443GX's SERR# signal driver is enabled and SERR# is asserted

when an error condition occurs, and the corresponding bit is enabled in the ERRCMD
register. The error status is reported in the ERRSTS and PCISTS registers. Also, if this bit is
set and the 82443GX's PCI parity error reporting is enabled by the PERRE bit located in this
register, then the 82443GX will report address and data parity errors (when it is potential
target).

0 = SERR# is never driven by the 82443GX.

Address/Data Stepping. Not implemented (hardwired to 0).

Parity Error Enable (PERRE). Note that the PERR# signal is not implemented by the 82443GX.

1 = Enable. Address and data parity errors are reported via SERR# mechanism (if enabled via

SERRE bit).

0 = Disable. Address and data parity errors are not reported via the 82443GX SERR# signal.

(NOTE: Other types of error conditions can be still signaled via SERR# mechanism.)

NOTE: The 82443GX PCI bus interface is still required to generate parity even if parity error
reporting is disabled via this bit.

Reserved.

Memory Write and Invalidate Enable. The 82443GX never uses this command.

0 = Hardwired to 0.

Special Cycle Enable. The 82443GX ignores all special cycles generated on the PCI.

0 = Hardwired to 0.

Bus Master Enable (BME). The 82443GX does not support disabling of its bus master
capability on the PCI Bus.

1 = Hardwired to 1, permitting the 82443GX to function as a PCI Bus master.

Memory Access Enable (MAE). This bit enables/disables PCI master access to main memory
(DRAM). The 82443GX always allows PCI master access to main memory.

1 = Hardwired to 1.

I/O Access Enable (IOAE). The 82443GX does not respond to PCI bus I/O cycles.

0 = Hardwired to 0.

3-12

82443GX Host Bridge Datasheet

3.3.4

PCISTS--PCI Status Register (Device 0)

Address Offset:

0607h

Default Value:

0210h/0200h

Access:

Read Only, Read/Write Clear

Size:

16 bits

PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target
abort on the PCI bus. PCISTS also indicates the DEVSEL# timing that has been set by the
82443GX hardware for target responses on the PCI bus. Bits [15:12] and bit 8 are read/write clear
and bits [10:9] are read only.

Bit

Descriptions

Detected Parity Error (DPE). Note that the function of this bit is not affected by the PERRE bit.
PERR# is not implemented in the 82443GX.

1 = Indicates 82443GX's detection of a parity error in the address or data phase of PCI bus

transactions.

0 = Software sets DPE to 0 by writing a 1 to this bit.

Signaled System Error (SSE).

1 = This bit is set to 1 when the 82443GX asserts SERR# for any enabled error condition under

device 0.

0 = Software sets SSE to 0 by writing a 1 to this bit.

Received Master Abort Status (RMAS). Note that Master abort is the normal and expected
termination of PCI special cycles.

1 = When the 82443GX terminates a PCI bus transaction (82443GX is a PCI master) with an

unexpected master abort, this bit is set to 1.

0 = Software resets this bit to 0 by writing a 1 to it.

Received Target Abort Status (RTAS).

1 = When a 82443GX-initiated PCI transaction is terminated with a target abort, RTAS is set to 1.

The 82443GX also asserts SERR# if enabled in the ERRCMD register.

0 = Software resets RTAS to 0 by writing a 1 to it.

Signaled Target Abort Status (STAS). The 82443GX does not generate target abort.

0 = Hardwired to a 0

10:9

DEVSEL# Timing (DEVT). This 2-bit field indicates the timing of the DEVSEL# signal when the
82443GX responds as a target on PCI, and indicates the time when a valid DEVSEL# can be
sampled by the initiator of the PCI cycle.

01 = Medium (hardwired to 01)

Data Parity Detected (DPD). 82443GX does not implement the PERR# pin. However, data
parity errors are still detected and reported on SERR# (if enabled by SERRE and PERRE).

0 = Hardwired to 0

Fast Back-to-Back (FB2B). The 82443GX as a target does not support fast back-to-back
transactions on the PCI bus.

0 = Hardwired to 0

6:5

Reserved.

Capability List (CLIST).

1 = When the AGP DIS bit (PMCR[1]) is set to 0, this bit is set to 1.

0 = When the AGP DIS bit (PMCR[1]) is set to 1, this bit is set 0.

3:0

Reserved.

82443GX Host Bridge Datasheet

3-13

3.3.5

RID--Revision Identification Register (Device 0)

Address Offset:

08h

Default Value:

00h

Access:

Read Only

Size:

8 bits

This register contains the revision number of the 82443GX Function #0. These bits are read only
and writes to this register have no effect.

3.3.6

SUBC--Sub-Class Code Register (Device 0)

Address Offset:

0Ah

Default Value:

00h

Access:

Read Only

Size:

8 bits

This register contains the Sub-Class Code for the 82443GX Function #0. This code is 00h
indicating a Host Bridge device. The register is read only.

3.3.7

BCC--Base Class Code Register (Device 0)

Address Offset:

0Bh

Default Value:

06h

Access:

Read Only

Size:

8 bits

This register contains the Base Class Code of the 82443GX Function #0. This code is 06h
indicating a Bridge device. This register is read only.

Bit

Description

7:0

Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for the 82443GX Function #0.

A-0 = 00h

Bit

Description

7:0

Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which
the 82443GX falls. The code is 00h indicating a Host Bridge.

Bit

Description

7:0

Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the
82443GX. This code has the value 06h, indicating a Bridge device.

3-14

82443GX Host Bridge Datasheet

3.3.8

MLT--Master Latency Timer Register (Device 0)

Address Offset:

0Dh

Default Value:

00h

Access:

Read/Write

Size:

8 bits

This register controls the amount of time that 82443GX can burst data on the PCI Bus as a PCI
master. The MLT[2:0] bits are reserved and assumed to be 0 when determining the Count Value.

3.3.9

HDR--Header Type Register (Device 0)

Offset:

0Eh

Default:

00h

Access:

Read Only

Size:

8 bits

This register identifies the header layout of the configuration space.

3.3.10

APBASE--Aperture Base Configuration Register (Device 0)

Offset:

1013h

Default:

00000008h

Access:

Read/Write, Read Only

Size:

32 bits

The APBASE is a normal PCI Base Address register that is used to request the base of the Graphics
Aperture. The normal PCI Configuration mechanism defines the base address configuration
register such that only a fixed amount of space can be requested (dependent on which bits are
hardwired to "0" or behave as hardwired to "0"). To allow for flexibility (of the aperture) an
additional register called APSIZE is used as a "back-end" register to control which bits of the
APBASE will behave as hardwired to "0". This register will be programmed by the 82443GX
specific BIOS code that will run before any of the generic configuration software is run.

Note:

Bit 9 of the NBXCFG register is used to prevent accesses to the aperture range before this register
is initialized by the configuration software and appropriate translation table structure has been
established in the main memory.

Bit

Description

7:3

Master Latency Timer Count Value for PCI Bus Access. MLT is an 8-bit register that controls
the amount of time the 82443GX, as a PCI bus master, can burst data on the PCI Bus. The
default value of MLT is 00h and disables this function. For example, if the MLT is programmed to
18h, then the value is 24 PCI clocks.

2:0

Reserved.

Bit

Descriptions

7:0

Header Type (HEADT). This read only field always returns 0 when read. Writes have no affect
on this field.

82443GX Host Bridge Datasheet

3-15

3.3.11

SVID--Subsystem Vendor Identification Register (Device 0)

Offset:

2C2Dh

Default:

0000h

Access:

Read/Write Once

Size:

16 bits

Bit

Description

31:28

Upper Programmable Base Address bits (R/W). These bits are used to locate the range size
selected via lower bits 27:4.

Default = 0000b

27:22

Lower "Hardwired"/Programmable Base Address bits. These bits behave as a "hardwired" or
as a programmable depending on the contents of the APSIZE register as defined below:

Aperture Size

r/w

4 MB

r/w

8 MB

r/w

16 MB

r/w

32 MB

r/w

0 0 0 0 64

r/w

0 0 0 0 0 128

0 0 0 0 0 256

Bits 27:22 are controlled by the bits 5:0 of the APSIZE register in the following manner:

If bit APSIZE[5]=0 then APBASE[27]=0 and if APSIZE[5]=1 then APBASE[27]=r/w (read/write).
The same applies correspondingly to other bits.

Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond
as "hardwired" to 0). This provides a default to the maximum aperture size of 256 MB. The
82443GX specific BIOS is responsible for selecting smaller size (if required) before PCI
configuration software runs and establishes the system address map.

21:4

Hardwired to "0". This forces minimum aperture size selected by this register to be 4MB.

Prefetchable (RO). This bit is hardwired to "1" to identify the Graphics Aperture range as a
prefetchable ( i.e., the device returns all bytes on reads regardless of the byte enables), and the
82443GX may merge processor writes into this range without causing errors.

2:1

Type (RO). These bits determine addressing type and they are hardwired to "00" to indicate that
address range defined by the upper bits of this register can be located anywhere in the 32-bit
address space.

Memory Space Indicator (RO). Hardwired to "0" to identify aperture range as a memory range.

Bit

Description

15:0

Subsystem Vendor ID (R/WO). This value is used to identify the vendor of the subsystem. The
default value is 00h. This field should be programmed during boot-up. After this field is written
once, it becomes read only.

3-16

82443GX Host Bridge Datasheet

3.3.12

SID--Subsystem Identification Register (Device 0)

Offset:

2E2Fh

Default:

0000h

Access:

Read/Write Once

Size:

16 bits

3.3.13

CAPPTR--Capabilities Pointer Register (Device 0)

Offset:

34h

Default:

A0h/00h

Access:

Read Only

Size:

8 bits

The CAPPTR provides the offset that is the pointer to the location where the AGP normal registers
are located.

3.3.14

NBXCFG--NBX Configuration Register (Device 0)

Offset:

5053h

Default:

bits 3116: 0000h
bits 150: 00S0-0000-000S-0S00b

Access:

Read/Write, Read Only for strapping options

Size:

32 bits

Bit

Description

15:0

Subsystem ID (R/WO). This value is used to identify a particular subsystem. The default value is
00h. This field should be programmed during boot-up. After this field is written once, it becomes
read only.

Bit

Description

7:0

Pointer to the start of AGP normal register block.

A0h = When the AGP_DIS bit (PMCR[1]) is set to 0, the value in this field is A0h.

00h = When the AGP_DIS bit (PMCR[1]) is set to 1, this field is set to 00h.

Bit

Description

31:24

SDRAM Row Without ECC. Bit[n] of this 8 bit array corresponds to row[n] of the SDRAM array.
When reading a SDRAM row (DIMM) which is none-ECC, the 82443GX drives the ECC data lines
during the first data transfer in a burst read.

0 = ECC components are populated in this row. The 82443GX will not drive the ECC signals.

1 = ECC components are not populated in this row. The 82443GX will drive the ECC lines in the

first read data transferred when this row is addressed.

23:19

Reserved.

Host Bus Fast Data Ready Enable (HBFDRE).

0 = Assertion of DRAM data on host bus occurs one clock after sampling snoop results. (default)

1 = Assertion of DRAM data on host bus occurs on the same clock the snoop result is being

sampled. This mode is faster by one clock cycle.

Intel Reserved

82443GX Host Bridge Datasheet

3-17

IDSEL_REDIRECT. This is a programmable option to make the 82443GX compatible with 430TX
base design. For CPU initiated configuration cycles to PCI, Device 1 which are targeted to the
82443GX's host to AGP bridge:

0 = When set to `0' (default), IDSEL1 (or AD12) is allocated to this bridge. The external AD12 is

never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus
device that its IDSEL input is connected to IDSEL7 (AD18).

1 = When set to `1', IDSEL7 (or AD18) is allocated to this bridge. Since it is internal in the

82443GX, the external AD18 is never activated. CPU initiated configuration cycles to BUS0,
DEVICE7 are targeted a PCI bus device that its IDSEL input is connected to IDSEL1 (AD12).
In some 430TX based systems, this is connected to PIIX4E.

Note that CPU initiated configuration cycles to other PCI buses or other devices are normally
mapped and are not affected.

WSC# Handshake Disable. In the Uni-Processor mode, this bit should be set to `1'. In the Dual-
Processor mode where external IOAPIC is used, this bit should be set to `0' (default). Setting this
bit to `0', enables the WSC# handshake mechanism.

Intel Reserved.

13:12

Host/DRAM Frequency. These bits are used to determine the host and DRAM frequency. Bit 13
is set by an external strapping option at reset.

00 = 100 MHz

01 = Reserved

10 = Reserved

11 = Reserved

AGP to PCI Access Enable. When PHLDA# is active or there is an outstanding passive release
transaction pending: 1) this bit is set to 1 and the 82443GX allows AGP to PCI traffic, or 2) this bit
is set to 0 (default) and the 82443GX blocks AGP to PCI traffic. The AGP to PCI traffic must not
target the ISA bus.

1 = Enable

0 =Disable

PCI Agent to Aperture Access Disable. This bit is used to prevent access to the aperture from
the PCI side.

1 = Disable

0 = Enable (default). If this bit is "0" (default) and bit 9 = 1, accesses to the aperture are enabled

for the PCI side.

Note: This bit is don't care if bit 9 of this register = 0.

Aperture Access Global Enable. This bit is used to prevent access to the aperture from any port
(CPU, PCI or AGP) before aperture range is established by the configuration software and
appropriate translation table in the main DRAM has been initialized. Default is "0". It must be set
after system is fully configured for aperture accesses.

1 = Enable. Note that this bit globally controls accesses to the aperture. Once enabled, bit 10

provides the next level of control for accesses originated from the PCI side.

0 = Disable

8:7

DRAM Data Integrity Mode (DDIM) (R/W). These bits select one of 4 DRAM data integrity
modes.

00 = Non-ECC (Byte-Wise Writes supported) (Default)

01 = EC-only - Error Checking with No correction

10 = ECC Mode (Error Checking/Correction)

11 = ECC Mode with hardware scrubbing enabled

ECC Diagnostic Mode Enable (EDME) (R/W).

1 = Enable. When this bit is set to 1, the 82443GX will enter ECC Diagnostic test mode and the

82443GX forces the MECC[7:0] lines to 00h for all writes to memory. During reads, the read
MECC[7:0] lines are compared against internally generated ECC. Recognized errors are
indicated via the ERRSTS register as in normal ECC operation.

0 = Normal operation mode (default).

Bit

Description

3-18

82443GX Host Bridge Datasheet

MDA Present (MDAP).

This bit is used to indicate the presence of a secondary monochrome adapter on the PCI bus,
while the primary graphics controller is on the AGP bus. This bit works in conjunction with the
VGA_EN bit (Register 3E, bit 3 of device 1) as follows:

VGA_EN

MDAP

Description

All VGA cycles are sent to PCI. PCI master cycles to the VGA range

are not claimed by the 82443GX.

All VGA cycles are sent to AGP. PCI master writes to VGA range are

claimed by the 82443GX and forwarded to the AGP bus.

All VGA cycles are sent to AGP, except for cycles in the MDA range

(or the aliased ranges defined below). PCI master writes in the VGA
range (outside of the MDA range) are claimed by the 82443GX and
forwarded to AGP. PCI and AGP master read/writes to the MDA range
are ignored by the 82443GX.

The MDA ranges are a subset of the VGA ranges as follows:

Memory: 0B0000h0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh

Reserved.

USWC Write Post During I/O Bridge Access Enable (UWPIO) (R/W).

1 = Enable. Host USWC writes to PCI memory are posted.

0 = Disable. Posting of USWC is not allowed.

In-Order Queue Depth (IOQD) (RO). This bit reflects the value sampled on A7# on the
deassertion of the CPURST#. It indicates the depth of the Pentium

Pro processor bus in-order

queue (i.e., level of Pentium Pro processor bus pipelining).

1 = In-order queue = maximum. If A7# is sampled "1" (i.e,. undriven on the Pentium Pro

processor bus), the depth of the Pentium Pro processor bus in-order queue is configured to
the maximum allowed by the Pentium Pro processor protocol (i.e., 8). However, the actual
maximum supported by the 82443GX is 4, and it is controlled by the 82443GX's Pentium Pro
processor interface logic using the BNR# signaling mechanism.

0 = A7# is sampled asserted (i.e., "0"). The depth of the Pentium Pro processor bus in-order

queue is set to 1 (i.e., no pipelining support on the Pentium Pro processor bus).

NOTE: During reset, A7# can be driven either by the 82443GX or by an external source as
defined by the strapping option on the MAB11# pin.

1:0

Reserved.

Bit

Description

82443GX Host Bridge Datasheet

3-19

3.3.15

DRAMC--DRAM Control Register (Device 0)

Address Offset:

57h

Default Value:

0000_0000b

Access:

Read/Write

Size:

8 bits

Bit

Description

7:6

Reserved.

Intel Reserved

4:3

DRAM Type (DT). This field indicates the DRAM type used to populate the entire array. When
set to 01, SDRAM timings are used for all cycles to memory. When set to 10, timings for
memory cycles accommodate Registered SDRAMs. For registered SDRAM timings, all address
and control lines to the SDRAMs are assumed to be registered, while memory data and ECC
bits are not registered. SDRAM and Registered SDRAM cannot be mixed within a system.

00 = Reserved

01 = SDRAM

10 = Registered SDRAM

11 = Reserved

NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to `0'.

2:0

DRAM Refresh Rate (DRR). The DRAM refresh rate is adjusted according to the frequency
selected by this field. Disabling the refresh cycle (000) results in the eventual loss of DRAM
data. Changing DRR value will reset the refresh request timer. This field is used in conjunction
with the SDRAM frequency bits in the NBXCFG register to determine the correct load value for
the refresh timer.

000 = Refresh Disabled

001 = 15.6 us

010 = 31.2 us

011 = 62.4 us

100 = 124.8 us

101 = 7.8 us

110 = Reserved

111 = Reserved

NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to `0'.

3-20

82443GX Host Bridge Datasheet

3.3.16

PAM[6:0]--Programmable Attribute Map Registers
(Device 0)

Address Offset:

59h (PAM0) 5Fh (PAM6)

Default Value:

00h

Attribute:

Read/Write

The 82443GX allows programmable memory attributes on 13 Legacy memory segments of various
sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers
are used to support these features. Cacheability of these areas is controlled via the MTRR registers
in the Pentium Pro processor. Two bits are used to specify memory attributes for each memory
segment. These bits apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:

Read Enable. When RE = 1, the host read accesses to the corresponding memory segment
are claimed by the 82443GX and directed to main memory. Conversely, when RE = 0, the
host read accesses are directed to PCI.

Write Enable. When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the 82443GX and directed to main memory. Conversely, when
WE = 0, the host write accesses are directed to PCI.

The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.

Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and are defined in Table 3-2.

As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, the BIOS can be shadowed in main memory to increase the system
performance. When BIOS is shadowed in main memory, it should be copied to the same address
location. To shadow the BIOS, the attributes for that address range should be set to write only. The
BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus.

Table 3-2. Attribute Bit Assignment

Bits [7, 3]
Reserved

Bits [6, 2]
Reserved

Bits [5, 1]

Bits [4, 0]

Description

Disabled. DRAM is disabled and all accesses are
directed to PCI. The 82443GX does not respond as a
PCI target for any read or write access to this area.

Read Only. Reads are forwarded to DRAM and writes
are forwarded to PCI for termination. This write protects
the corresponding memory segment. The 82443GX will
respond as a PCI target for read accesses but not for
any write accesses.

Write Only. Writes are forwarded to DRAM and reads
are forwarded to the PCI for termination. The 82443GX
will respond as a PCI target for write accesses but not
for any read accesses.

Read/Write. This is the normal operating mode of main
memory. Both read and write cycles from the host are
claimed by the 82443GX and forwarded to DRAM. The
82443GX will respond as a PCI target for both read and
write accesses.

82443GX Host Bridge Datasheet

3-21

The host then does a write of the same address, which is directed to main memory. After the BIOS
is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded
to the expansion bus. Table 3-3 shows the PAM registers and the associated attribute bits:

NOTE:

1. The C0000h to CFFFFh segment can be used for SMM space if enabled by the SMRAM register

DOS Application Area (00000h9FFFh)

The DOS area is 640 KB and it is further divided into two parts. The 512 KB area at 0 to 7FFFFh is
always mapped to the main memory controlled by the 82443GX, while the 128 KB address range
from 080000 to 09FFFFh can be mapped to PCI or to main DRAM. By default this range is
mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI)
via 82443GX's FDHC configuration register.

Video Buffer Area (A0000hBFFFFh)

This 128 KB area is not controlled by attribute bits. The host-initiated cycles in this region are
always forwarded to either PCI or AGP unless this range is accessed in SMM mode. Routing of
accesses is controlled by the Legacy VGA control mechanism of the "virtual" PCI-to-PCI bridge
device embedded within the 82443GX.

This area can be programmed as SMM area via the SMRAM register. When used as a SMM space
this range can not be accessed from PCI or AGP.

Expansion Area (C0000hDFFFFh)

This 128 KB area is divided into eight 16 KB segments which can be assigned with different
attributes via PAM control register as defined by Table 3-3.

Extended System BIOS Area (E0000hEFFFFh)

This 64 KB area is divided into four 16 KB segments which can be assigned with different
attributes via PAM control register as defined by the Table 3-3.

System BIOS Area (F0000hFFFFFh)

This area is a single 64 KB segment which can be assigned with different attributes via PAM
control register as defined by the Table 3-3.

Table 3-3. PAM Registers and Associated Memory Segments

PAM Reg

Attribute Bits

Memory Segment

Comments

Offset

PAM0[3:0]

Reserved

59h

PAM0[7:4]

0F0000h 0FFFFFh

BIOS Area

59h

PAM1[3:0]

0C0000h 0C3FFFh

ISA Add-on BIOS¹

5Ah

PAM1[7:4]

0C4000h 0C7FFFh

ISA Add-on BIOS¹

5Ah

PAM2[3:0]

0C8000h 0CBFFFh

ISA Add-on BIOS¹

5Bh

PAM2[7:4]

0CC000h 0CFFFFh

ISA Add-on BIOS¹

5Bh

PAM3[3:0]

0D0000h 0D3FFFh

ISA Add-on BIOS

5Ch

PAM3[7:4]

0D4000h 0D7FFFh

ISA Add-on BIOS

5Ch

PAM4[3:0]

0D8000h 0DBFFFh

ISA Add-on BIOS

5Dh

PAM4[7:4]

0DC000h 0DFFFFh

ISA Add-on BIOS

5Dh

PAM5[3:0]

0E0000h 0E3FFFh

BIOS Extension

5Eh

PAM5[7:4]

0E4000h 0E7FFFh

BIOS Extension

5Eh

PAM6[3:0]

0E8000h 0EBFFFh

BIOS Extension

5Fh

PAM6[7:4]

0EC000h 0EFFFFh

BIOS Extension

5Fh

3-22

82443GX Host Bridge Datasheet

3.3.17

DRB[0:7]--DRAM Row Boundary Registers (Device 0)

Address Offset:

60h (DRB0) 67h (DRB7)

Default Value:

01h

Access:

Read/Write

Size:

8 bits/register

The 82443GX supports 8 physical rows of DRAM. The width of a row is 64 bits. The DRAM Row
Boundary Registers define upper and lower addresses for each DRAM row. Contents of these 8-bit
registers represent the boundary addresses in 8 MB granularity. For example, a value of 01h
indicates 8 MB.

60h

DRB0 = Total memory in row0 (in 8 MB)

61h

DRB1 = Total memory in row0 + row1 (in 8 MB)

62h

DRB2 = Total memory in row0 + row1 + row2 (in 8 MB)

63h

DRB3 = Total memory in row0 + row1 + row2 + row3 (in 8 MB)

64h

DRB4 = Total memory in row0 + row1 + row2 + row3 + row4 (in 8 MB)

65h

DRB5 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 (in 8 MB)

66h

DRB6 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 (in 8 MB)

67h

DRB7 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 + row7
(in 8 MB)

The DRAM array can be configured with single or double-sided DIMMs using parts listed in
Table 4-9. The array also supports x4 width DRAM components on registered DIMMs. Each
register defines an address range that will cause a particular CS# line to be asserted (e.g., if the first
DRAM row is minus 8 MB, then accesses within the 0 to 8 MByte range will cause CSx0#/
RASx0# to be asserted). The DRAM Row Boundary (DRB) Registers are programmed with an 8-
bit upper address limit value. This upper address limit is compared to bits [30:23] of the requested
address, for each row, to determine if DRAM is being targeted.

To specify a memory size of 2 GB, the DRB7 must be set to 00h. When this value is set, the
82443GX internally detects this value and sets the internal "2 GB system memory size" signal. It is
cleared otherwise.

Note:

DRBx and 2GB Decoding. The ability to detect a total system memory of 2 GB is possible for
DRB7 only. It is possible, however, to achieve 2 GB of memory in lower DRAM rows when some
or all the populated rows are 512 MB each. If the total memory size at DRBx, where x<7, is 2 GB,
then BIOS must set DBRx to 0FFh and the total memory available is 2 GB minus 8 MB. For the
following rows (from x+1 to 7), the DRB is set to 0FFh.

Note:

DRAM is selected only if address[31:30] are zero.

Bit

Description

7:0

Row Boundary Address. This 8-bit value is compared against address lines A[30:23] to
determine the upper address limit of a particular row (i.e., DRB minus previous DRB = row size).

NOTE: When PCIRST# assertion occurs during POS/STR, these bits are not reset to 01h.

82443GX Host Bridge Datasheet

3-23

Row Boundary Address

These 8 bit values represent the upper address limits of the eight rows (i.e., this row minus previous
row = row size). Unpopulated rows have a value equal to the previous row (row size = 0). DRB7
reflects the maximum amount of DRAM in the system. The top of memory is determined by the
value written into DRB7.

Note:

The 82443GX supports a maximum of 2 GB of DRAM.

As an example of a general purpose configuration where eight physical rows are configured for
either single-sided or double-sided DIMMs, the memory array would be configured like the one
shown in Figure 3-2. In this configuration, the 82443GX drives eight CS# signals directly to the
DIMM rows. If single-sided DIMMs are populated, the even CS# signals are used and the odd
CS#s are not connected. If double-sided DIMMs are used, all four CS# signals are used per DIMM.

The following 2 examples describe how the DRB Registers are programmed for cases of single-
sided and double-sided DIMMs on a motherboard.

Example #1 Single-sided DIMMs

Assume a total of 32 MB of DRAM are required using single-sided 2 MB x 64 DIMMs. In this
configuration, two DIMMs are required.

DRB0 = 02h

populated (1 DIMM, 16 Mbyte this row)

DRB1 = 02h

empty row

DRB2 = 04h

populated (1 DIMM, 16 Mbyte this row)

DRB3 = 04h

empty row

DRB4 = 04h

empty row

DRB5 = 04h

empty row

DRB6 = 04h

empty row

DRB7 = 04h

empty row

Figure 3-2. SDRAM DIMMs and Corresponding DRB Registers

CSA7#/CSB7#

DIMM3 Back

DIMM3 Front

DIMM2 Back

DIMM2 Front

DIMM1 Back

DIMM1 Front

DIMM0 Back

DIMM0 Front

CSA6#/CSB6#

CSA5#/CSB5#

CSA4#/CSB4#

CSA3#/CSB3#

CSA2#/CSB2#

CSA1#/CSB1#

CSA0#/CSB0#

DRB7

DRB6

DRB5

DRB4

DRB3

DRB2

DRB1

DRB0

3-24

82443GX Host Bridge Datasheet

Example #2 Mixed Single-/Double-sided DIMMs

As another example, consider a system that is initially shipped with 16 MB of memory using a
2M x 64 DIMM and that rest of the memory array should be upgradable up to a maximum
supported memory of 208 MB. This can be handled by further populating the array with one
16M x 64 single-sided DIMM (one row) and one 8M x 64 double-sided DIMM (two rows),
yielding a total of 208 MB of DRAM. The DRB Registers are programmed as follows:

DRB0 = 02h

populated with 8MB, 2 MB x 64 single-sided DIMM

DRB1 = 02h

empty row

DRB2 = 06h

populated with 32 MB, 1/2 of 8M x 64 DIMM

DRB3 = 10h

populated with 32 MB, the other 1/2 of 8M x 64 DIMM

DRB4 = 20h

populated with 128 MB, 16M x 64 single-sided DIMM

DRB5 = 20h

empty row

DRB6 = 20h

empty row

DRB7 = 20h

empty row

3.3.18

FDHC--Fixed DRAM Hole Control Register (Device 0)

Address Offset:

68h

Default Value:

00h

Access:

Read/Write

Size:

8 bits

This 8-bit register controls 2 fixed DRAM holes: 512 KB 640 KB and 15 MB 16 MB.

3.3.19

MBSC--Memory Buffer Strength Control Register
(Device 0)

Address Offset:

696Eh

Default Value:

000000000000h

Access:

Read/Write

Size:

48 bits

This register programs the various DRAM interface signal buffer strengths, based on non-mixed
memory configurations of DRAM type (SDRAM or Registered SDRAM), DRAM density (x4, x8
or x16), DRAM technology (16Mbit, 64Mbit, 128Mbit, or 256Mbit

), and rows populated. Note

that x4 DRAM are only supported when used on registered DIMMs.

Bit

Description

7:6

Hole Enable (HEN). This field enables a memory hole in DRAM space. Host cycles matching an
enabled hole are passed on to PCI. PCI cycles matching an enabled hole will be ignored by the
82443GX (no DEVSEL#). NOTE: A selected hole is not remapped.

00 = None

01 = 512 KB640 KB (128 KB bytes)

10 = 15 MB 16 MB (1 MB byte)

11 = Reserved

5:0

Reserved.

82443GX Host Bridge Datasheet

3-25

Bit

Description

47:40

Reserved