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Электронный компонент: 80960CF-33

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INTEL CORPORATION, 1996
June 1996
Order Number: 272886-001
A
PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
Socket and Object Code Compatible with 80960CA
Two Instructions/Clock Sustained Execution
Four 71 Mbytes/s DMA Channels with Data Chaining
Demultiplexed 32-Bit Burst Bus with Pipelining
s
32-Bit Parallel Architecture
-- Two Instructions/clock Execution
-- Load/Store Architecture
-- Sixteen 32-Bit Global Registers
-- Sixteen 32-Bit Local Registers
-- Manipulates 64-Bit Bit Fields
-- 11 Addressing Modes
-- Full Parallel Fault Model
-- Supervisor Protection Model
s
Fast Procedure Call/Return Model
-- Full Procedure Call in 4 Clocks
s
On-Chip Register Cache
-- Caches Registers on Call/Ret
-- Minimum of 6 Frames Provided
-- Up to 15 Programmable Frames
s
On-Chip Instruction Cache
-- 4 Kbyte Two-Way Set Associative
-- 128-Bit Path to Instruction Sequencer
-- Cache-Lock Modes
-- Cache-Off Mode
s
High Bandwidth On-Chip Data RAM
-- 1 Kbyte On-Chip Data RAM
-- Sustains 128 bits per Clock Access
s
Selectable Big or Little Endian Byte
Ordering
s
Four On-Chip DMA Channels
-- 71 Mbytes/s Fly-by Transfers
-- 40 Mbytes/s Two-Cycle Transfers
-- Data Chaining
-- Data Packing/Unpacking
-- Programmable Priority Method
s
32-Bit Demultiplexed Burst Bus
-- 128-Bit Internal Data Paths to
and
from
Registers
-- Burst Bus for DRAM Interfacing
-- Address Pipelining Option
-- Fully Programmable Wait States
-- Supports 8-, 16- or 32-Bit Bus Widths
-- Supports Unaligned Accesses
-- Supervisor Protection Pin
s
High-Speed Interrupt Controller
-- Up to 248 External Interrupts
-- 32 Fully Programmable Priorities
-- Multi-mode 8-Bit Interrupt Port
-- Four Internal DMA Interrupts
-- Separate, Non-maskable Interrupt Pin
-- Context Switch in 625 ns Typical
s
On-Chip Data Cache
-- 1 Kbyte Direct-Mapped, Write Through
-- 128 bits per Clock Access on Cache Hit
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
PRELIMINARY
iii
A
CONTENTS
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
1.0 PURPOSE .................................................................................................................................................. 1
2.0 80960CF OVERVIEW ................................................................................................................................ 1
2.1 The 80960C-Series Core .................................................................................................................... 3
2.2 Pipelined, Burst Bus ........................................................................................................................... 3
2.3 Instruction Set Summary .................................................................................................................... 3
2.4 Flexible DMA Controller ...................................................................................................................... 3
2.5 Priority Interrupt Controller .................................................................................................................. 4
3.0 PACKAGE INFORMATION ........................................................................................................................ 5
3.1 Package Introduction .......................................................................................................................... 5
3.2 Pin Descriptions .................................................................................................................................. 5
3.3 80960CF Mechanical Data ............................................................................................................... 12
3.3.1 80960CF PGA PINOUT ......................................................................................................... 12
3.3.2 80960CF PQFP Pinout (80960CF-33, -25, -16 Only) ............................................................ 16
3.4 Package Thermal Specifications ...................................................................................................... 19
3.5 Stepping Register Information .......................................................................................................... 22
3.6 Sources for Accessories ................................................................................................................... 22
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................ 23
4.1 Absolute Maximum Ratings .............................................................................................................. 23
4.2 Operating Conditions ........................................................................................................................ 23
4.3 Recommended Connections ............................................................................................................ 24
4.4 DC Specifications ............................................................................................................................. 24
4.5 AC Specifications .............................................................................................................................. 26
4.5.1 AC TEST CONDITIONS ........................................................................................................ 36
4.5.2 AC TIMING WAVEFORMS .................................................................................................... 37
4.5.3 DERATING CURVES ............................................................................................................. 41
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................ 42
6.0 BUS WAVEFORMS .................................................................................................................................. 44
7.0 REVISION HISTORY ............................................................................................................................... 71
iv
PRELIMINARY
CONTENTS
A
FIGURES
Figure 1.
80960CF Block Diagram ............................................................................................................ 2
Figure 2.
80960CF PGA Pinout--View from Top (Pins Facing Down) .................................................... 12
Figure 3.
80960CF PGA Pinout -- View from Bottom (Pins Facing Up) ................................................. 13
Figure 4.
80960CF PQFP Pinout--Top View (80960CF-33, -25, -16 Only) ............................................ 19
Figure 5.
Measuring 80960CF PGA and PQFP Case Temperature ....................................................... 20
Figure 6.
Register g0 ............................................................................................................................... 22
Figure 7.
AC Test Load ........................................................................................................................... 37
Figure 8.
Input and Output Clocks Waveform ......................................................................................... 37
Figure 9.
CLKIN Waveform ..................................................................................................................... 37
Figure 10.
Output Delay and Float Waveform ........................................................................................... 38
Figure 11.
Input Setup and Hold Waveform .............................................................................................. 38
Figure 12.
NMI, XINT7:0 Input Setup and Hold Waveform ....................................................................... 39
Figure 13.
Hold Acknowledge Timings ...................................................................................................... 39
Figure 14.
Bus Backoff (BOFF) Timings ................................................................................................... 40
Figure 15.
Relative Timings Waveforms ................................................................................................... 40
Figure 16.
Output Delay or Hold vs. Load Capacitance ............................................................................ 41
Figure 17.
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
............... 41
Figure 18.
I
CC
vs. Frequency and Temperature--80960CF-33, -25, -16 .................................................. 42
Figure 19.
I
CC
vs. Frequency and Temperature--80960CF-40 ................................................................ 42
Figure 20.
Cold Reset Waveform .............................................................................................................. 44
Figure 21.
Warm Reset Waveform ............................................................................................................ 45
Figure 22.
Entering the ONCE State ......................................................................................................... 46
Figure 23.
Clock Synchronization in the 2-x Clock Mode .......................................................................... 47
Figure 24.
Clock Synchronization in the 1-x Clock Mode .......................................................................... 47
Figure 25.
Non-Burst, Non-Pipelined Requests Without Wait States ........................................................ 48
Figure 26.
Non-Burst, Non-Pipelined Read Request With Wait States ..................................................... 49
Figure 27.
Non-Burst, Non-Pipelined Write Request With Wait States ..................................................... 50
Figure 28.
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ..................................... 51
Figure 29.
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus .......................................... 52
Figure 30.
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ..................................... 53
Figure 31.
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus .......................................... 54
Figure 32.
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus .......................................... 55
Figure 33.
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................ 56
Figure 34.
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ..................................... 57
Figure 35.
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus .......................................... 58
Figure 36.
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................. 59
Figure 37.
Burst, Pipelined Read Request With Wait States, 32-Bit Bus .................................................. 60
Figure 38.
Burst, Pipelined Read Request With Wait States, 16-Bit Bus .................................................. 61
Figure 39.
Burst, Pipelined Read Request With Wait States, 8-Bit Bus .................................................... 62
PRELIMINARY
v
A
CONTENTS
Figure 40.
Using External READY ............................................................................................................ 63
Figure 41.
Terminating a Burst with BTERM ............................................................................................. 64
Figure 42.
BOFF Functional Timing .......................................................................................................... 65
Figure 43.
HOLD Functional Timing .......................................................................................................... 66
Figure 44.
DREQ and DACK Functional Timing ....................................................................................... 67
Figure 45.
EOP Functional Timing ............................................................................................................ 67
Figure 46.
Terminal Count Functional Timing ........................................................................................... 68
Figure 47.
FAIL Functional Timing ............................................................................................................ 68
Figure 48.
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................. 69
Figure 49.
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ......... 70
Figure 50.
Idle Bus Operation ................................................................................................................... 71
TABLES
Table 1.
80960CF Instruction Set ............................................................................................................ 4
Table 2.
80960CF Pin Description -- External Bus Signals .................................................................... 6
Table 3.
80960CF Pin Description -- Processor Control Signals ............................................................ 9
Table 4.
80960CF Pin Description -- DMA and Interrupt Unit Control Signals ..................................... 11
Table 5.
80960CF PGA Pinout -- In Signal Order ................................................................................ 14
Table 6.
80960CF PGA Pinout -- In Pin Order ..................................................................................... 15
Table 7.
80960CF PQFP Pinout -- In Signal Order (80960CF-33, -25, -16 Only) ................................ 17
Table 8.
80960CF PQFP Pinout -- In Pin Order (80960CF-33, -25, -16 Only) ..................................... 18
Table 9.
Maximum T
A
at Various Airflows in
o
C (PGA Package Only) ................................................... 20
Table 10.
80960CF PGA Package Thermal Characteristics ................................................................... 21
Table 11.
80960CF PQFP Package Thermal Characteristics ................................................................. 21
Table 12.
Die Stepping Cross Reference ................................................................................................ 22
Table 13.
Operating Conditions ............................................................................................................... 23
Table 14.
DC Characteristics ................................................................................................................... 24
Table 15.
80960CF AC Characteristics (40 MHz) ................................................................................... 26
Table 16.
80960CF AC Characteristics (33 MHz) ................................................................................... 29
Table 17.
80960CF AC Characteristics (25 MHz) ................................................................................... 32
Table 18.
80960CF AC Characteristics (16 MHz) ................................................................................... 34
Table 19.
Reset Conditions ..................................................................................................................... 43
Table 20.
Hold Acknowledge and Backoff Conditions ............................................................................. 43