Document Outline
- 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet
- Contents
- Figures
- Figure 1. 80960Jx Microprocessor Package Options
- Figure 2. 80960Jx Block Diagram
- Figure 3. 132-Lead Pin Grid Array Top View-Pins Facing Down
- Figure 4. 132-Lead Pin Grid Array Bottom View-Pins Facing Up
- Figure 5. 132-Lead PQFP - Top View
- Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down
- Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up
- Figure 8. VCC5 Current-Limiting Resistor
- Figure 9. VCCPLL Lowpass Filter
- Figure 10. A.C. Test Load
- Figure 11. Output Delay or Hold vs. Load Capacitance80960JS/JC/JT (3.3 V Signals)
- Figure 12. Output Delay or Hold vs. Load Capacitance80960JS/JC/JT (5 V Signals)
- Figure 13. Output Delay or Hold vs. Load Capacitance80960JA/JF/JD
- Figure 14. TLX vs. AD Bus Load Capacitance80960JS/JC/JT (3.3 V Signals)
- Figure 15. TLX vs. AD Bus Load Capacitance80960JS/JC/JT (5 V Signals)
- Figure 16. TLX vs. AD Bus Load Capacitance80960JA/JF/JD
- Figure 17. ICC Active (Power Supply) vs. Frequency80960JA/JF
- Figure 18. 80960JA/JF ICC Active (Thermal) vs. Frequency
- Figure 19. 80960JD ICC Active (Power Supply) vs. Frequency
- Figure 20. 80960JD ICC Active (Thermal) vs. Frequency
- Figure 21. 80960JC ICC Active (Power Supply) vs. Frequency
- Figure 22. 80960JC ICC Active (Thermal) vs. Frequency
- Figure 23. 80960JS ICC Active (Power Supply) vs. Frequency
- Figure 24. 80960JS ICC Active (Thermal) vs. Frequency
- Figure 25. CLKIN Waveform
- Figure 26. TOV1 Output Delay Waveform
- Figure 27. TOF Output Float Waveform
- Figure 28. TIS1 and TIH1 Input Setup and Hold Waveform
- Figure 29. TIS2 and TIH2 Input Setup and Hold Waveform
- Figure 30. TIS3 and TIH3 Input Setup and Hold Waveform
- Figure 31. TIS4 and TIH4 Input Setup and Hold Waveform
- Figure 32. TLX, TLXL and TLXA Relative Timings Waveform
- Figure 33. DT/R# and DEN# Timings Waveform
- Figure 34. TCK Waveform
- Figure 35. TBSIS1 and TBSIH1 Input Setup and Hold Waveforms
- Figure 36. TBSOV1 and TBSOF1 Output Delay and Output Float Waveform
- Figure 37. TBSOV2 and TBSOF2 Output Delay and Output Float Waveform
- Figure 38. TBSIS2 and TBSIH2 Input Setup and Hold Waveform
- Figure 39. 80960JS/JC/JT Device Identification Register Fields
- Figure 40. 80960JD Device Identification Register Fields
- Figure 41. 80960JA/JF Device Identification Register Fields
- Figure 42. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
- Figure 43. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
- Figure 44. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
- Figure 45. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
- Figure 46. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus
- Figure 47. Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
- Figure 48. HOLD/HOLDA Waveform For Bus Arbitration
- Figure 49. Cold Reset Waveform
- Figure 50. Warm Reset Waveform
- Figure 51. Entering the ONCE State
- Figure 52. Bus States with Arbitration
- Figure 53. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
- Figure 54. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
- Tables
- Revision History
- 1.0 Introduction
- 2.0 80960Jx Overview
- 3.0 Packaging Information
- 4.0 Electrical Specifications
- 5.0 Device Identification
- 6.0 Thermal Specifications
- 7.0 Bus Functional Waveforms
80960JA/JF/JD/JS/JC/JT 3.3 V
Embedded 32-Bit Microprocessor
Datasheet
Product Features
s
Code Compatible with all 80960Jx
Processors
s
High-Performance Embedded Architecture
-- One Instruction/Clock Execution
-- Core Clock Rate is:
1x the Bus Clock for 80960JA/JF/JS
2x the Bus Clock for 80960JD/JC
3x the Bus Clock for 80960JT
-- Load/Store Programming Model
-- Sixteen 32-Bit Global Registers
-- Sixteen 32-Bit Local Registers (8 sets)
-- Nine Addressing Modes
-- User/Supervisor Protection Model
s
Two-Way Set Associative Instruction
Cache
-- 80960JA - 2 Kbyte
-- 80960JF/JD - 4 Kbyte
-- 80960JS/JC/JT - 16 Kbyte
-- Programmable Cache-Locking
Mechanism
s
Direct Mapped Data Cache
-- 80960JA - 1 Kbyte
-- 80960JF/JD - 2 Kbyte
-- 80960JS/JC/JT - 4 Kbyte
-- Write Through Operation
s
On-Chip Stack Frame Cache
-- Seven Register Sets May Be Saved
-- Automatic Allocation on Call/Return
-- 0-7 Frames Reserved for High-Priority
Interrupts
s
On-Chip Data RAM
-- 1 Kbyte Critical Variable Storage
-- Single-Cycle Access
s
3.3 V Supply Voltage
-- 5 V Tolerant Inputs
-- TTL Compatible Outputs
s
High Bandwidth Burst Bus
-- 32-Bit Multiplexed Address/Data
-- Programmable Memory Configuration
-- Selectable 8-, 16-, 32-Bit Bus Widths
-- Supports Unaligned Accesses
-- Big or Little Endian Byte Ordering
s
High-Speed Interrupt Controller
-- 31 Programmable Priorities
-- Eight Maskable Pins plus NMI#
-- Up to 240 Vectors in Expanded Mode
s
Two On-Chip Timers
-- Independent 32-Bit Counting
-- Clock Prescaling by 1, 2, 4 or 8
-- Internal Interrupt Sources
s
Halt Mode for Low Power
s
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s
Packages
-- 132-Lead Pin Grid Array (PGA)
-- 132-Lead Plastic Quad Flat Pack
(PQFP)
-- 196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Order Number: 273159-005
September 2002
2
Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright Intel Corporation, 2002
Datasheet
3
Contents
Contents
1.0
Introduction.................................................................................................................................... 7
2.0
80960Jx Overview.......................................................................................................................... 9
2.1
80960 Processor Core ........................................................................................................ 10
2.2
Burst Bus ............................................................................................................................ 11
2.3
Timer Unit ........................................................................................................................... 11
2.4
Priority Interrupt Controller.................................................................................................. 11
2.5
Instruction Set Summary .................................................................................................... 12
2.6
Faults and Debugging......................................................................................................... 12
2.7
Low Power Operation ......................................................................................................... 12
2.8
Test Features...................................................................................................................... 12
2.9
Memory-Mapped Control Registers .................................................................................... 13
2.10
Data Types and Memory Addressing Modes...................................................................... 13
3.0
Packaging Information ................................................................................................................ 15
3.1
Available Processors and Packages ..................................................................................15
3.2
Pin Descriptions .................................................................................................................. 16
3.2.1
Functional Pin Definitions ...................................................................................... 16
3.2.2
80960Jx 132-Lead PGA Pinout ............................................................................. 23
3.2.3
80960Jx 132-Lead PQFP Pinout ........................................................................... 27
3.2.4
80960Jx 196-Ball MPBGA Pinout .......................................................................... 30
4.0
Electrical Specifications ............................................................................................................. 35
4.1
Absolute Maximum Ratings ................................................................................................ 35
4.2
Operating Conditions .......................................................................................................... 35
4.3
Connection Recommendations........................................................................................... 36
4.4
VCC5 Pin Requirements (VDIFF) ....................................................................................... 36
4.5
VCCPLL Pin Requirements ................................................................................................ 37
4.6
D.C. Specifications ............................................................................................................. 38
4.7
A.C. Specifications.............................................................................................................. 42
4.7.1
A.C. Test Conditions and Derating Curves ............................................................ 45
4.7.1.1
Output Delay or Hold vs. Load Capacitance .......................................... 46
4.7.1.2
T
LX
vs. AD Bus Load Capacitance......................................................... 47
4.7.1.3
ICC Active vs. Frequency ...................................................................... 49
4.7.2
A.C. Timing Waveforms .........................................................................................53
5.0
Device Identification.................................................................................................................... 59
5.1
80960JS/JC/JT Device Identification Register.................................................................... 60
5.2
80960JD Device Identification Register .............................................................................. 61
5.3
80960JA/JF Device Identification Register ......................................................................... 62
6.0
Thermal Specifications ............................................................................................................... 63
6.1
Thermal Management Accessories .................................................................................... 68
6.1.1
Heatsinks ............................................................................................................... 68
7.0
Bus Functional Waveforms ........................................................................................................ 69
7.1
Basic Bus States................................................................................................................. 79
7.2
Boundary-Scan Register..................................................................................................... 80
Contents
4
Datasheet
Figures
1
80960Jx Microprocessor Package Options .................................................................................. 7
2
80960Jx Block Diagram.............................................................................................................. 10
3
132-Lead Pin Grid Array Top View-Pins Facing Down............................................................... 23
4
132-Lead Pin Grid Array Bottom View-Pins Facing Up .............................................................. 24
5
132-Lead PQFP - Top View ....................................................................................................... 27
6
196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down ............................................ 30
7
196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up ........................................... 31
8
VCC5 Current-Limiting Resistor ................................................................................................. 36
9
VCCPLL Lowpass Filter ............................................................................................................. 37
10
A.C. Test Load............................................................................................................................ 45
11
Output Delay or Hold vs. Load Capacitance80960JS/JC/JT (3.3 V Signals) .......................... 46
12
Output Delay or Hold vs. Load Capacitance80960JS/JC/JT (5 V Signals) ............................. 46
13
Output Delay or Hold vs. Load Capacitance80960JA/JF/JD .................................................... 47
14
T
LX
vs. AD Bus Load Capacitance80960JS/JC/JT (3.3 V Signals) ......................................... 47
15
T
LX
vs. AD Bus Load Capacitance80960JS/JC/JT (5 V Signals) ............................................ 48
16
T
LX
vs. AD Bus Load Capacitance80960JA/JF/JD................................................................... 48
17
I
CC
Active (Power Supply) vs. Frequency80960JA/JF ............................................................. 49
18
80960JA/JF I
CC
Active (Thermal) vs. Frequency ....................................................................... 49
19
80960JD I
CC
Active (Power Supply) vs. Frequency ................................................................... 50
20
80960JD I
CC
Active (Thermal) vs. Frequency ............................................................................ 50
21
80960JC I
CC
Active (Power Supply) vs. Frequency ................................................................... 51
22
80960JC I
CC
Active (Thermal) vs. Frequency ............................................................................ 51
23
80960JS I
CC
Active (Power Supply) vs. Frequency ................................................................... 52
24
80960JS I
CC
Active (Thermal) vs. Frequency ............................................................................ 52
25
CLKIN Waveform........................................................................................................................ 53
26
T
OV1
Output Delay Waveform .................................................................................................... 53
27
T
OF
Output Float Waveform ....................................................................................................... 54
28
T
IS1
and T
IH1
Input Setup and Hold Waveform .......................................................................... 54
29
T
IS2
and T
IH2
Input Setup and Hold Waveform .......................................................................... 54
30
T
IS3
and T
IH3
Input Setup and Hold Waveform .......................................................................... 55
31
T
IS4
and T
IH4
Input Setup and Hold Waveform .......................................................................... 55
32
T
LX
, T
LXL
and T
LXA
Relative Timings Waveform ........................................................................ 56
33
DT/R# and DEN# Timings Waveform......................................................................................... 56
34
TCK Waveform ........................................................................................................................... 57
35
T
BSIS1
and T
BSIH1
Input Setup and Hold Waveforms................................................................. 57
36
T
BSOV1
and T
BSOF1
Output Delay and Output Float Waveform ................................................. 57
37
T
BSOV2
and T
BSOF2
Output Delay and Output Float Waveform ................................................. 58
38
T
BSIS2
and T
BSIH2
Input Setup and Hold Waveform................................................................... 58
39
80960JS/JC/JT Device Identification Register Fields ................................................................. 60
40
80960JD Device Identification Register Fields ........................................................................... 61
41
80960JA/JF Device Identification Register Fields ...................................................................... 62
42
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus................................. 69
43
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ........................................ 70
44
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus .................................................. 71
45
Burst Read and Write Transactions Without Wait States, 8-Bit Bus .......................................... 72
46
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ..................................................................................... 73
47
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian ........................................................................ 74
Datasheet
5
Contents
48
HOLD/HOLDA Waveform For Bus Arbitration ............................................................................75
49
Cold Reset Waveform................................................................................................................. 76
50
Warm Reset Waveform .............................................................................................................. 77
51
Entering the ONCE State............................................................................................................78
52
Bus States with Arbitration.......................................................................................................... 80
53
Summary of Aligned and Unaligned Accesses (32-Bit Bus)....................................................... 84
54
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................... 85
Tables
1
80960Jx 3.3-V Microprocessor Family ......................................................................................... 7
2
80960Jx Instruction Set .............................................................................................................. 14
3
80960Jx Processors Available in 132-Pin PGA Package........................................................... 15
4
80960Jx Processors Available in 132-Pin PQFP Package......................................................... 15
5
80960Jx Processors Available in Extended Temperature ......................................................... 16
6
80960Jx Processors Available in 196-Ball MPBGA Package..................................................... 16
7
Pin Description Nomenclature .................................................................................................... 17
8
Pin Description--External Bus Signals....................................................................................... 18
9
Pin Description--Processor Control Signals, Test Signals, and Power .....................................21
10
Pin Description--Interrupt Unit Signals ...................................................................................... 22
11
132-Lead PGA Pinout--In Signal Order ..................................................................................... 25
12
132-Lead PGA Pinout--In Pin Order.......................................................................................... 26
13
132-Lead PQFP Pinout--In Signal Order................................................................................... 28
14
132-Lead PQFP Pinout--In Pin Order........................................................................................ 29
15
196-Ball MPBGA Pinout--In Signal Order..................................................................................32
16
196-Ball MPBGA Pinout--In Pin Order ...................................................................................... 33
17
Absolute Maximum Ratings ........................................................................................................ 35
18
80960Jx Operating Conditions ................................................................................................... 35
19
VDIFF Parameters...................................................................................................................... 37
20
80960Jx D.C. Characteristics ..................................................................................................... 38
21
80960Jx I
CC
Characteristics ....................................................................................................... 39
22
80960Jx A.C. Characteristics ..................................................................................................... 42
23
Note Definitions for Table 22, 80960Jx AC Characteristics........................................................ 45
24
80960Jx Device Type and Stepping Reference ......................................................................... 59
25
80960JS/JC/JT Device ID Register Field Definitions.................................................................. 60
26
80960JS/JC/JT Device ID Model Types ..................................................................................... 60
27
80960JD Device ID Field Definitions .......................................................................................... 61
28
80960JD Device ID Model Types ...............................................................................................61
29
80960JA/JF Device ID Field Definitions ..................................................................................... 62
30
80960JA/JF Device ID Model Types .......................................................................................... 62
31
Thermal Resistance for q
CA
and q
JC
Reference Table .............................................................. 63
32
Maximum Ambient Temperature Reference Table.....................................................................63
33
132-Lead PGA Package Thermal Characteristics ...................................................................... 64
34
80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics ......................................... 64
35
80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics ......................................... 65
36
132-Lead PQFP Package Thermal Characteristics.................................................................... 65
37
Maximum T
A
at Various Airflows in C (80960JT) ...................................................................... 66
38
Maximum T
A
at Various Airflows in C (80960JC)...................................................................... 66
39
Maximum T
A
at Various Airflows in C (80960JD)...................................................................... 67
40
Maximum T
A
at Various Airflows in C (80960JS) ...................................................................... 67
41
Maximum T
A
at Various Airflows in C (80960JA/JF) ................................................................. 68
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