Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
May 1993
INTEL CORPORATION, 1993
Order Number: 270775-005
80960KA
EMBEDDED 32-BIT MICROPROCESSOR
The 80960KA is a member of Intel's i960 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large
register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,
this high performance processor is capable of execution rates in excess of 9.4 million instructions per second
*
.
The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and
specialty instrumentation.
Figure 1. The 80960KA Processor's Highly Parallel Architecture
* Relative to Digital Equipment Corporation's VAX-11/780 at 1 MIPS (VAX-11TM is a trademark of Digital Equipment
Corporation)
s
High-Performance Embedded Architecture
-- 25 MIPS Burst Execution at 25 MHz
-- 9.4 MIPS* Sustained Execution at 25 MHz
s
512-Byte On-Chip Instruction Cache
-- Direct Mapped
-- Parallel Load/Decode for Uncached Instruc-
tions
s
Multiple Register Sets
-- Sixteen Global 32-Bit Registers
-- Sixteen Local 32-Bit Registers
-- Four Local Register Sets Stored On-Chip
-- Register Scoreboarding
s
4 Gigabyte, Linear Address Space
s
Pin Compatible with 80960KB
s
Built-in Interrupt Controller
-- 31 Priority Levels, 256 Vectors
-- 3.4 s Latency @ 25 MHz
s
Easy to Use, High Bandwidth 32-Bit Bus
-- 66.7 Mbytes/s Burst
-- Up to 16 Bytes Transferred per Burst
s
132-Lead Packages:
-- Pin Grid Array (PGA)
-- Plastic Quad Flat-Pack (PQFP)
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
ii
1.0 THE i960 PROCESSOR ................................ 1
1.1. Key Performance Features .......................... 2
1.1.1. Memory Space And Addressing Modes . 4
1.1.2. Data Types ............................................. 4
1.1.3. Large Register Set ................................. 4
1.1.4. Multiple Register Sets ............................ 5
1.1.5. Instruction Cache ................................... 5
1.1.6. Register Scoreboarding ......................... 5
1.1.7. High Bandwidth Local Bus ..................... 6
1.1.8. Interrupt Handling ................................... 6
1.1.9. Debug Features ..................................... 6
1.1.10. Fault Detection ..................................... 7
1.1.11. Built-in Testability ................................. 7
1.1.12. CHMOS ................................................ 7
2.0 ELECTRICAL SPECIFICATIONS .................. 10
2.1. Power and Grounding ................................ 10
2.2. Power Decoupling Recommendations ....... 10
2.3. Connection Recommendations .................. 11
2.4. Characteristic Curves ................................. 11
2.5. Test Load Circuit ........................................ 14
2.6. Absolute Maximum Ratings ....................... 15
2.7. DC Characteristics ..................................... 15
2.8. AC Specifications ....................................... 16
2.8.1. AC Specification Tables ....................... 17
3.0 MECHANICAL DATA ..................................... 21
3.1. Packaging .................................................. 21
3.1.1. Pin Assignment .................................... 21
3.2. Pinout ......................................................... 25
3.3. Package Thermal Specification ................. 29
4.0. WAVEFORMS ............................................... 33
5.0. REVISION HISTORY ..................................... 38
FIGURES
Figure 1.
The 80960KA Processor's Highly
Parallel Architecture ............................ i
Figure 2.
80960KA Programming
Environment ........................................ 1
Figure 3.
Instruction Formats ............................. 4
Figure 4.
Multiple Register Sets Are Stored
On-Chip ............................................... 6
Figure 5.
Connection Recommendations
for Low Current Drive Network .......... 11
Figure 6.
Connection Recommendations
for High Current Drive Network ......... 11
Figure 7.
Typical Supply Current vs.
Case Temperature ............................ 12
Figure 8.
Typical Current vs. Frequency
(Room Temp) .................................... 12
Figure 9.
Typical Current vs. Frequency
(Hot Temp) ........................................ 13
Figure 10.
Worst-Case Voltage vs. Output
Current on Open-Drain Pins .............. 13
Figure 11.
Capacitive Derating Curve ................ 13
Figure 12.
Test Load Circuit for Three-State
Output Pins ...................................... 14
Figure 13.
Test Load Circuit for Open-Drain
Output Pins ...................................... 14
Figure 14.
Drive Levels and Timing Relationships
for 80960KA Signals ......................... 16
Figure 15.
Processor Clock Pulse (CLK2) .......... 20
Figure 16.
RESET Signal Timing ....................... 20
Figure 17.
32-Lead Pin-Grid Array
(PGA) Package ................................. 21
Figure 18.
80960KA PGA Pinout--View from
Bottom (Pins Facing Up) ................... 22
Figure 19.
80960KA PGA Pinout--View from
Top (Pins Facing Down) .................... 23
Figure 20.
80960KA 132-Lead Plastic Quad
Flat-Pack (PQFP) Package ............... 23
Figure 21.
PQFP Pinout - View From Top .......... 24
Figure 22.
HOLD Timing .................................... 30
Figure 23.
16 MHz Maximum Allowable
Ambient Temperature ....................... 31
80960KA
EMBEDDED 32-BIT MICROPROCESSOR
CONTENTS
iii
Figure 24.
20 MHz Maximum Allowable
Ambient Temperature ....................... 31
Figure 25.
25 MHz Maximum Allowable
Ambient Temperature ....................... 32
Figure 26.
Maximum Allowable Ambient
Temperature for the Extended
Temperature TA-80960KA at
20 MHz in PGA Package .................. 32
Figure 27.
Non-Burst Read and Write
Transactions Without Wait States ..... 33
Figure 28.
Burst Read and Write Transaction
Without Wait States ......................... 34
Figure 29.
Burst Write Transaction with
2, 1, 1, 1 Wait States ........................ 35
Figure 30.
Accesses Generated by Quad Word
Read Bus Request, Misaligned Two
Bytes from Quad Word Boundary
(1, 0, 0, 0 Wait States) ...................... 36
Figure 31.
Interrupt Acknowledge Transaction .. 37
TABLES
Table 1.
80960KA Instruction Set ..................... 3
Table 2.
Memory Addressing Modes ................ 4
Table 3.
80960KA Pin Description:
L-Bus Signals ...................................... 8
Table 4.
80960KA Pin Description:
Support Signals ................................... 9
Table 5.
DC Characteristics ............................ 15
Table 6.
80960KA AC Characteristics
(16 MHz) ........................................... 17
Table 7.
80960KA AC Characteristics
(20 MHz) ........................................... 18
Table 8.
80960KA AC Characteristics
(25 MHz) ........................................... 19
Table 9.
80960KA PGA Pinout --
In Pin Order ....................................... 25
Table 10.
80960KA PGA Pinout --
In Signal Order .................................. 26
Table 11.
80960KA PQFP Pinout --
In Pin Order ....................................... 27
Table 12.
80960KA PQFP Pinout --
In Signal Order .................................. 28
Table 13.
80960KA PGA Package
Thermal Characteristics .................... 29
Table 14.
80960KA PQFP Package
Thermal Characteristics .................... 30
80960KA
1
1.0
THE i960 PROCESSOR
The 80960KA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
were especially designed to serve the needs of
embedded applications. The embedded market
includes applications as diverse as industrial
automation, avionics, image processing, graphics and
networking. These types of applications require high
integration, low power consumption, quick interrupt
response times and high performance. Since time to
market is critical, embedded microprocessors need to
be easy to use in both hardware and software
designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Software written for the 80960KA will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KB
which includes an integrated floating-point unit and
the 80960MC which is a military-grade version that
supports multitasking, memory management, multi-
processing and fault tolerance.
Figure 2. 80960KA Programming Environment
INSTRUCTION CACHE
INSTRUCTION
STREAM
FETCH
LOAD
STORE
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
SIXTEEN 32-BIT LOCAL REGISTERS
REGISTER CACHE
FOUR 80-BIT FLOATING POINT REGISTERS
r0
r15
CONTROL REGISTERS
INSTRUCTION
EXECUTION
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FFFF FFFFH
0000 0000H
ADDRESS SPACE
PROCESSOR STATE
REGISTERS
80960KA
2
1.1.
Key Performance Features
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel's long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KA's exceptional
performance:
1.
Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the
80960KA provides thirty-two 32-bit registers. (See
Figure 2.)
2.
Fast Instruction Execution. Simple functions
make up the bulk of instructions in most programs so
that execution speed can be improved by ensuring
that these core instructions are executed as quickly
as possible. The most frequently executed instruc-
tions such as register-register moves, add/subtract,
logical operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3.
Load/Store Architecture. One way to improve
execution speed is to reduce the number of times that
the processor must access memory to perform an
operation. As with other processors based on RISC
technology, the 80960KA has a Load/Store archi-
tecture. As such, only the LOAD and STORE instruc-
tions reference memory; all other instructions operate
on registers. This type of architecture simplifies
instruction decoding and is used in combination with
other techniques to increase parallelism.
4.
Simple Instruction Formats. All instructions in
the 80960KA are 32 bits long and must be aligned on
word boundaries. This alignment makes it possible to
eliminate the instruction alignment stage in the
pipeline. To simplify the instruction decoder, there are
only five instruction formats; each instruction uses
only one format. (See Figure 3.)
5.
Overlapped Instruction Execution. Load
operations allow execution of subsequent instructions
to continue before the data has been returned from
memory, so that these instructions can overlap the
load. The 80960KA manages this process transpar-
ently to software through the use of a register score-
board. Conditional instructions also make use of a
scoreboard so that subsequent unrelated instructions
may be executed while the conditional instruction is
pending.
6.
Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value is sent
immediately to its destination register. Yet at the same
time, the value is put on a bypass path to the ALU,
thereby saving the time that otherwise would be
required to retrieve the value for the next operation.
7.
Bandwidth Optimizations. The 80960KA gets
optimal use of its memory bus bandwidth because the
bus is tuned for use with the on-chip instruction
cache: instruction cache line size matches the
maximum burst size for instruction fetches. The
80960KB automatically fetches four words in a burst
and stores them directly in the cache. Due to the size
of the cache and the fact that it is continually filled in
anticipation of needed instructions in the program
flow, the 80960KA is relatively insensitive to memory
wait states. The benefit is that the 80960KA delivers
outstanding performance even with a low cost
memory system.
8.
Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then sends
it on to the instruction decoder at the same time it
updates the cache. Thus, no extra time is spent to
load and read the cache.
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