Document Outline
- 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT
INTEL CORPORATION, 1997
June, 1997
Order Number: 270565.007
80960KB
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
Figure 1. The 80960KB Processor's Highly Parallel Architecture
s
High-Performance Embedded
Architecture
-- 25 MIPS Burst Execution at 25 MHz
-- 9.4 MIPS* Sustained Execution at
25 MHz
s
512-Byte On-Chip Instruction Cache
-- Direct Mapped
-- Parallel Load/Decode for Uncached
Instructions
s
Multiple Register Sets
-- Sixteen Global 32-Bit Registers
-- Sixteen Local 32-Bit Registers
-- Four Local Register Sets Stored
On-Chip
-- Register Scoreboarding
s
4 Gigabyte, Linear Address Space
s
Pin Compatible with 80960KA
s
Built-in Interrupt Controller
-- 31 Priority Levels, 256 Vectors
-- 3.4 s Latency @ 25 MHz
s
Easy to Use, High Bandwidth 32-Bit Bus
-- 66.7 Mbytes/s Burst
-- Up to 16 Bytes Transferred per Burst
s
132-Lead Packages:
-- Pin Grid Array (PGA)
-- Plastic Quad Flat-Pack (PQFP)
s
On-Chip Floating Point Unit
-- Supports IEEE 754 Floating Point
Standard
-- Four 80-Bit Registers
-- 13.6 Million Whetstones/s (Single
Precision) at 25 MHz
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS CONTROL
LOGIC
32-BIT
BURST
BUS
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
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Copyright Intel Corporation 1997.
Contents
iii
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
1.0 THE i960 PROCESSOR .......................................................................................................................... 1
1.1 Key Performance Features ................................................................................................................. 2
1.1.1 Memory Space And Addressing Modes ................................................................................... 4
1.1.2 Data Types ............................................................................................................................... 4
1.1.3 Large Register Set ................................................................................................................... 4
1.1.4 Multiple Register Sets .............................................................................................................. 5
1.1.5 Instruction Cache ..................................................................................................................... 5
1.1.6 Register Scoreboarding ........................................................................................................... 5
1.1.7 High Bandwidth Local Bus ....................................................................................................... 6
1.1.8 Interrupt Handling .................................................................................................................... 6
1.1.9 Debug Features ....................................................................................................................... 6
1.1.10 Fault Detection ....................................................................................................................... 7
1.1.11 Built-in Testability ................................................................................................................... 7
2.0 ELECTRICAL SPECIFICATIONS ............................................................................................................ 10
2.1 Power and Grounding ....................................................................................................................... 10
2.2 Power Decoupling Recommendations ............................................................................................. 10
2.3 Connection Recommendations ........................................................................................................ 11
2.4 Characteristic Curves ....................................................................................................................... 11
2.5 Test Load Circuit ............................................................................................................................... 14
2.7 DC Characteristics ............................................................................................................................ 15
2.6 Absolute Maximum Ratings .............................................................................................................. 15
2.8 AC Specifications ............................................................................................................................. 16
2.8.1 AC Specification Tables ......................................................................................................... 17
3.0 MECHANICAL DATA ................................................................................................................................ 21
3.1 Packaging ......................................................................................................................................... 21
3.1.1 Pin Assignment ...................................................................................................................... 21
3.2 Pinout ............................................................................................................................................... 25
3.3 Package Thermal Specification ........................................................................................................ 29
4.0 WAVEFORMS .......................................................................................................................................... 33
5.0 REVISION HISTORY ............................................................................................................................... 38
iv
Contents
FIGURES
Figure 1.
80960KA Programming Environment ........................................................................................ 1
Figure 2.
Instruction Formats .................................................................................................................... 4
Figure 3.
Multiple Register Sets Are Stored On-Chip ............................................................................... 6
Figure 4.
Connection Recommendations for Low Current Drive Network .............................................. 11
Figure 5.
Connection Recommendations for High Current Drive Network .............................................. 11
Figure 6.
Typical Supply Current vs. Case Temperature ......................................................................... 12
Figure 7.
Typical Current vs. Frequency (Room Temp) .......................................................................... 12
Figure 8.
Typical Current vs. Frequency (Hot Temp) .............................................................................. 13
Figure 9.
Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 13
Figure 10.
Capacitive Derating Curve ....................................................................................................... 13
Figure 11.
Test Load Circuit for Three-State Output Pins ......................................................................... 14
Figure 12.
Test Load Circuit for Open-Drain Output Pins .......................................................................... 14
Figure 13.
Drive Levels and Timing Relationships for 80960KA Signals .................................................. 16
Figure 14.
Processor Clock Pulse (CLK2) ........................................................................................ ........ 20
Figure 15.
RESET Signal Timing ................................................................................................. ............. 20
Figure 16.
132-Lead Pin-Grid Array (PGA) Package ............................................................................... . 21
Figure 17.
80960KA PGA Pinout--View from Bottom (Pins Facing Up) ................................................... 22
Figure 18.
80960KA PGA Pinout--View from Top (Pins Facing Down) .................................................... 23
Figure 19.
80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package ................................................ 23
Figure 20.
PQFP Pinout - View From Top ................................................................................................. 24
Figure 21.
HOLD Timing ........................................................................................................................... 30
Figure 22.
16 MHz Maximum Allowable Ambient Temperature ................................................................ 31
Figure 23.
20 MHz Maximum Allowable Ambient Temperature ................................................................ 31
Figure 24.
25 MHz Maximum Allowable Ambient Temperature ................................................................ 32
Figure 25.
Maximum Allowable Ambient Temperature
for the Extended Temperature TA-80960KA at 20 MHz in PGA Package ............................... 32
Figure 27.
Burst Read and Write Transaction Without Wait States ........................................................... 34
Figure 28.
Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 35
Figure 29.
Accesses Generated by Quad Word Read Bus Request,
Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) .............................. 36
Figure 30.
Interrupt Acknowledge Transaction ......................................................................................... 37
v
Contents
TABLES
Table 1.
80960KA Instruction Set ............................................................................................................ 3
Table 2.
Memory Addressing Modes ....................................................................................................... 4
Table 3.
80960KA Pin Description: L-Bus Signals ................................................................................... 8
Table 4.
80960KA Pin Description: Support Signals ............................................................................... 9
Table 5.
DC Characteristics ................................................................................................................... 15
Table 6.
80960KA AC Characteristics (16 MHz) ................................................................................... 17
Table 7.
80960KA AC Characteristics (20 MHz) ................................................................................... 18
Table 9.
80960KA PGA Pinout -- In Pin Order ..................................................................................... 25
Table 10.
80960KA PGA Pinout -- In Signal Order ................................................................................ 26
Table 11.
80960KA PQFP Pinout -- In Pin Order ................................................................................... 27
Table 12.
80960KA PQFP Pinout -- In Signal Order .............................................................................. 28
Table 13.
80960KA PGA Package Thermal Characteristics ................................................................... 29
Table 14.
80960KA PQFP Package Thermal Characteristics ................................................................. 30
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