Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
INTEL CORPORATION, 2004 August 2004
Order Number: 272543-003
8XC196MH INDUSTRIAL MOTOR CONTROL
CHMOS MICROCONTROLLER
The 8XC196MH is a member of Intel's family of 16-bit MCS
96 microcontrollers. It is designed primarily to
control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
generator specifically designed for use in "inverter" motor-control applications. This peripheral provides pulse-
width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
complementary non-overlapping PWM pulses with resolutions of 0.125 s (edge triggered) or 0.250 s
(centered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of
40C to
+
85C
.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
High Performance CHMOS 16-bit CPU
16 MHz Operating Frequency
32 Kbytes of On-chip OTPROM/ROM
744 Bytes of On-chip Register RAM
Register-to-register Architecture
16 Prioritized Interrupt Sources
Peripheral Transaction Server (PTS) with 15
Prioritized Sources
Up to 52 I/O Lines
3-phase Complementary Waveform Generator
8-channel 8- or 10-bit A/D with Sample and
Hold
2-channel UART
Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
Two Programmable 16-bit Timers with
Quadrature Counting Inputs
Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
Flexible 8- or 16-bit External Bus
1.75 s 16 16 Multiply
3 s 32/16 Divide
Extended Temperature Available
Idle and Powerdown Modes
Watchdog Timer
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
3
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS IV
process. Additional process and reliability information
is available in Intel's
Components Quality and
Reliability
Handbook (order number 210997).
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel
Packaging
Handbook (order
number 240800) describes Intel's thermal impedance
test methodology.
Table 1. Thermal Characteristics
Package Type
JA
JC
84-lead PLCC
33C/W
11C/W
80-lead QFP
56C/W
12C/W
64-lead SDIP
56C/W
N/A
Figure 2. The 8XC196MH Family Nomenclature
X XX 8 X C 196 XX XX
Device Speed:
Product Family:
No Mark = 16 MHz
K
x, Mx, Nx
CHMOS Technology
Program Memory Options:
0 = ROMless, 3 = ROM, 7 = OTPROM
Package - Type Options:
Temperature and Burn In Options:
A2759-01
x = SDIP, x = PLCC, x = QFP
x = 40C +85C Ambient
with Intel Standard Burn-In
To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
NOTE:
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
4
Table 2. 8XC196MH Memory Map
Address
(1)
Description
Notes
0FFFFH
0A000H
External Memory
09FFFH
02080H
Internal ROM/OTPROM or External Memory
0207FH
0205EH
Reserved
1, 2
0205DH
02040H
PTS Vectors
0203FH
02030H
Interrupt Vectors (upper)
0202FH
02020H
ROM/OTPROM Security Key
0201FH
0201CH
Reserved
1, 2
0201BH
Reserved (must contain 20H)
0201AH
CCB1
02019H
Reserved (must contain 20H)
02018H
CCB0
02017H
02014H
Reserved
02013H
02000H
Interrupt Vectors (lower)
01FFFH
01F00H
Internal SFRs
1
1EFFH
300H
External Memory
2FFH
18H
Register RAM
3
17H
00H
CPU SFRs
1
NOTES:
1.
Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
2.
WARNING: The contents and/or function of reserved locations may change with future revisions of the
device.
3.
Code executed in locations 0000H to 02FFH will be forced external.
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