Intel Corporation
el
int
Intel
450NX PCIset
Order Number: 243771-004
June 1998
82454NX PCI Expander Bridge (PXB)
82453NX Data Path Multiplexor (MUX)
82452NX RAS/CAS Generator (RCG)
82451NX Memory & I/O Controller (MIOC)
1998
Information in this document is provided in connection with Intel products. No license, express or
implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except
as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatso-
ever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products
including liability or warranties relating to fitness for a particular purpose, merchantability, or infringe-
ment of any patent, copyright or other intellectual property right. Intel products are not intended for use
in medical, life saving, or life sustaining applications. Intel may make changes to specifications and prod-
uct descriptions at any time, without notice.
The Intel 450NX PCIset may contain design defects or errors known as errata which may cause the prod-
uct to deviate from the published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing
your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at
http://www.intel.com
Copyright Intel Corporation 1998.
* Third-party brands and names are the property of their respective owners.
Intel 450NX PCIset
-i-
CONTENTS
Chapter 1
Introduction ......................................................................................................................................... 1-1
1.1
Overview ..................................................................................................................................................... 1-1
1.2
Intel
450NX PCIset Components .............................................................................................................. 1-2
1.3
Intel
450NX PCIset Feature Summary ...................................................................................................... 1-3
1.4
Packaging & Power ..................................................................................................................................... 1-4
Chapter 2
Signal Descriptions ............................................................................................................................ 2-1
2.1
Conventions ................................................................................................................................................ 2-1
2.2
Summary ..................................................................................................................................................... 2-2
2.2.1
Signal Summary, By Component .................................................................................................. 2-2
2.2.1.1
MIOC Signal List .......................................................................................................... 2-3
2.2.1.2
PXB Signal List ............................................................................................................ 2-4
2.2.1.3
RCG Signal List ........................................................................................................... 2-5
2.2.1.4
MUX Signal List ........................................................................................................... 2-5
2.3
System Interface ......................................................................................................................................... 2-6
2.3.1
System / MIOC Interface ............................................................................................................... 2-6
2.3.2
Third-Party Agent / MIOC Interface .............................................................................................. 2-8
2.4
PCI Interface ............................................................................................................................................... 2-8
2.4.1
Primary Bus .................................................................................................................................. 2-8
2.4.2
64-bit Access Support ................................................................................................................. 2-10
2.4.3
Internal vs. External Arbitration ................................................................................................... 2-10
2.4.4
PIIX4E Interface .......................................................................................................................... 2-11
2.5
Memory Subsystem Interface .................................................................................................................... 2-12
2.5.1
External Interface ........................................................................................................................ 2-12
2.5.2
Internal Interface ......................................................................................................................... 2-14
2.5.2.1
RCG / DRAM Interface .............................................................................................. 2-14
2.5.2.2
DRAM / MUX Interface .............................................................................................. 2-15
2.5.2.3
RCG / MUX Interface ................................................................................................. 2-15
2.6
Expander Interface .................................................................................................................................... 2-15
2.7
Common Support Signals ......................................................................................................................... 2-17
2.7.1
JTAG Interface ............................................................................................................................ 2-17
2.7.2
Reference Signals ....................................................................................................................... 2-17
2.8
Component-Specific Support Signals ........................................................................................................ 2-18
2.8.1
MIOC ........................................................................................................................................... 2-18
2.8.2
PXB ............................................................................................................................................ 2-19
2.8.3
RCG ............................................................................................................................................ 2-19
2.8.4
MUX ............................................................................................................................................ 2-19
Chapter 3
Register Descriptions ......................................................................................................................... 3-1
3.1
Access Restrictions ..................................................................................................................................... 3-1
3.2
I/O Mapped Registers ................................................................................................................................. 3-1
3.2.1
CONFIG_ADDRESS: Configuration Address Register ............................................................... 3-1
-ii-
Intel 450NX PCIset
CONTENTS
3.2.2
CONFIG_DATA: Configuration Data Register .............................................................................. 3-2
3.3
MIOC Configuration Space .......................................................................................................................... 3-3
3.3.1
BUFSIZ: Buffer Sizes ................................................................................................................... 3-4
3.3.2
BUSNO[1:0]: Lowest PCI Bus Number, per PXB ......................................................................... 3-5
3.3.3
CHKCON: Check Connection ....................................................................................................... 3-5
3.3.4
CLASS: Class Code Register ....................................................................................................... 3-6
3.3.5
CONFIG: Software-Defined Configuration Register ..................................................................... 3-6
3.3.6
CVCR: Configuration Values Captured on Reset ......................................................................... 3-8
3.3.7
CVDR: Configuration Values Driven On Reset ............................................................................ 3-9
3.3.8
DBC[15:0]: DRAM Bank Configuration Registers ......................................................................... 3-9
3.3.9
DEVMAP: System Bus PCI Device Map .................................................................................... 3-10
3.3.10
DID: Device Identification Register ............................................................................................. 3-11
3.3.11
ECCCMD: ECC Command Register .......................................................................................... 3-11
3.3.12
ECCMSK: ECC Mask Register ................................................................................................... 3-12
3.3.13
ERRCMD: Error Command Register .......................................................................................... 3-12
3.3.14
ERRSTS: Error Status Register ................................................................................................. 3-13
3.3.15
GAPEN: Gap Enables ................................................................................................................ 3-14
3.3.16
HDR: Header Type Register ....................................................................................................... 3-15
3.3.17
HEL[1:0] Host Bus Error Log ...................................................................................................... 3-15
3.3.18
HXGB: High Expansion Gap Base ............................................................................................. 3-16
3.3.19
HXGT: High Expansion Gap Top ............................................................................................... 3-16
3.3.20
IOABASE: I/O APIC Base Address ............................................................................................ 3-16
3.3.21
IOAR: I/O APIC Ranges ............................................................................................................. 3-17
3.3.22
IOR: I/O Ranges ......................................................................................................................... 3-17
3.3.23
ISA: ISA Space ........................................................................................................................... 3-18
3.3.24
LXGB: Low Expansion Gap Base ............................................................................................... 3-18
3.3.25
LXGT: Low Expansion Gap Top ................................................................................................. 3-18
3.3.26
MAR[6:0]: Memory Attribute Region Registers ........................................................................... 3-19
3.3.27
MEA[1:0] Memory Error Effective Address ................................................................................. 3-20
3.3.28
MEL[1:0] Memory Error Log ....................................................................................................... 3-20
3.3.29
MMBASE: Memory-Mapped PCI Base ...................................................................................... 3-21
3.3.30
MMR[3:0]: Memory-Mapped PCI Ranges .................................................................................. 3-21
3.3.31
PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3-21
3.3.32
PME[1:0]: Performance Monitoring Event Selection .................................................................. 3-22
3.3.33
PMR[1:0]: Performance Monitoring Response ........................................................................... 3-23
3.3.34
RC: Reset Control Register ........................................................................................................ 3-24
3.3.35
RCGP: RCGs Present ................................................................................................................ 3-25
3.3.36
REFRESH: DRAM Refresh Control Register ............................................................................. 3-25
3.3.37
RID: Revision Identification Register .......................................................................................... 3-25
3.3.38
ROUTE[1:0]: Route Field Seed ................................................................................................. 3-26
3.3.39
SMRAM: SMM RAM Control Register ........................................................................................ 3-26
3.3.40
SUBA[1:0]: Bus A Subordinate Bus Number, per PXB .............................................................. 3-27
3.3.41
SUBB[1:0]: Bus B Subordinate Bus Number, per PXB .............................................................. 3-28
3.3.42
TCAP[0:3]: Target Capacity, per PXB/PCI Port .......................................................................... 3-28
3.3.43
TOM: Top of Memory ................................................................................................................. 3-29
3.3.44
VID: Vendor Identification Register ............................................................................................ 3-29
3.4
PXB Configuration Space .......................................................................................................................... 3-29
3.4.1
BUFSIZ: Buffer Sizes ................................................................................................................. 3-31
3.4.2
CLASS: Class Code Register ..................................................................................................... 3-31
3.4.3
CLS: Cache Line Size ................................................................................................................ 3-32
3.4.4
CONFIG: Configuration Register ................................................................................................ 3-32
3.4.5
DID: Device Identification Register ............................................................................................. 3-33
3.4.6
ERRCMD: Error Command Register .......................................................................................... 3-34
3.4.7
ERRSTS: Error Status Register ................................................................................................. 3-35
Intel 450NX PCIset
-iii-
CONTENTS
3.4.8
GAPEN: Gap Enables ................................................................................................................ 3-36
3.4.9
HDR: Header Type Register ...................................................................................................... 3-36
3.4.10
HXGB: High Expansion Gap Base ............................................................................................. 3-36
3.4.11
HXGT: High Expansion Gap Top ............................................................................................... 3-36
3.4.12
IOABASE: I/O APIC Base Address ............................................................................................ 3-37
3.4.13
ISA: ISA Space .......................................................................................................................... 3-37
3.4.14
LXGB: Low Expansion Gap Base .............................................................................................. 3-37
3.4.15
LXGT: Low Expansion Gap Top ................................................................................................ 3-37
3.4.16
MAR[6:0]: Memory Attribute Region Registers .......................................................................... 3-38
3.4.17
MLT: Master Latency Timer Register ......................................................................................... 3-38
3.4.18
MMBASE: Memory-Mapped PCI Base ..................................................................................... 3-38
3.4.19
MMT: Memory-Mapped PCI Top ............................................................................................... 3-39
3.4.20
MTT: Multi-Transaction Timer Register ..................................................................................... 3-39
3.4.21
PCICMD: PCI Command Register ............................................................................................. 3-39
3.4.22
PCISTS: PCI Status Register .................................................................................................... 3-40
3.4.23
PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3-41
3.4.24
PME[1:0]: Performance Monitoring Event Selection .................................................................. 3-42
3.4.25
PMR[1:0]: Performance Monitoring Response .......................................................................... 3-43
3.4.26
RID: Revision Identification Register ......................................................................................... 3-44
3.4.27
RC: Reset Control Register ....................................................................................................... 3-44
3.4.28
ROUTE: Route Field Seed ......................................................................................................... 3-45
3.4.29
SMRAM: SMM RAM Control Register ....................................................................................... 3-45
3.4.30
TCAP: Target Capacity .............................................................................................................. 3-46
3.4.31
TMODE: Timer Mode ................................................................................................................. 3-46
3.4.32
TOM: Top of Memory ................................................................................................................. 3-47
3.4.33
VID: Vendor Identification Register ............................................................................................ 3-47
Chapter 4
System Address Maps ....................................................................................................................... 4-1
4.1
Memory Address Map ................................................................................................................................. 4-1
4.1.1
Memory-Mapped I/O Spaces ........................................................................................................ 4-4
4.1.2
SMM RAM Support ....................................................................................................................... 4-4
4.2
I/O Space .................................................................................................................................................... 4-5
4.3
PCI Configuration Space ............................................................................................................................. 4-6
Chapter 5
Interfaces ............................................................................................................................................. 5-1
5.1
System Bus ................................................................................................................................................. 5-1
5.2
PCI Bus ....................................................................................................................................................... 5-1
5.3
Expander Bus .............................................................................................................................................. 5-1
5.3.1
Expander Electrical Signal and Clock Distribution ........................................................................ 5-2
5.4
Third-Party Agents ...................................................................................................................................... 5-2
5.5
Connectors .................................................................................................................................................. 5-3
Chapter 6
Memory Subsystem ............................................................................................................................ 6-1
6.1
Overview ..................................................................................................................................................... 6-1
6.1.1
Physical Organization ................................................................................................................... 6-1
6.1.2
Configuration Rules and Limitations ............................................................................................. 6-3
6.1.2.1
Interleaving .................................................................................................................. 6-3
6.1.2.2
Address Bit Permuting Rules and Limitations ............................................................. 6-4
6.1.2.3
Card to Card (C2C) Interleaving Rules and limitations ................................................ 6-4
6.1.3
Address Bit Permuting .................................................................................................................. 6-5
PDF 
ZIP