Intel
82540EP Gigabit
Ethernet Controller
High-Performance Gigabit Connection for Mobile Designs
Intel in
Communications
The Intelligent Way
to Connect
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Footprint compatibility with Intel's latest 10/100
connections allows for flexible designs
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Reduced power usage and heat generation for
lower system costs, higher density and longer
battery life for mobile implementations.
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Enhanced manageability and system health
monitoring with ASF 1.0 and SMBus 2.0
Product Description
The Intel
82540EP Gigabit Ethernet Controller
integrates Gigabit Ethernet MAC and PHY layer
functions in a single, compact component.
Packaged in a 15x15mm TFBGA, the Intel
82540EP Gigabit Ethernet Controller is footprint
compatible with the Intel
82551QM, 88551ER,
82562EZ and 82562EX Fast Ethernet
Controllers, allowing for a flexible, Gigabit
Ethernet or 10/100 Ethernet design.
The Intel 82540EP combines Intel's fourth-
generation Gigabit MAC design, with fully
integrated, physical-layer circuitry to provide a
standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-T
applications (802.3, 802.3u, 802.3ab). In
addition, the controller provides a direct
Peripheral Component Interconnect designed
to be compliant with (PCI) 2.3 bus up to 66MHz.
The Intel 82540EP incorporates new features
that are designed for this controller for mobile
designs. New features include clock run protocol
support, a LAN disable pin and hardware
supported downshift capability to two-pair
100 Mbps operation. In addition, the Intel
82540EP consumes less power in the lower
system states and allows mobile users the
ability to optimize power consumption based
on power source.
The Intel 82540EP's on-board SMBus port
enables enhanced manageability and system
health monitoring via the LAN: Management
packets can be routed to or from a management
processor. The SMBus port enables
Product Brief
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Product Brief
Intel
82540EP
Product Description (continued)
implementation of industry standards such as IPMI
(Intelligent Platform Management Interface). In addition,
ASF 1.0 (Alert Standard Format) circuitry provides
alerting and remote-control capabilities with
standardized interfaces.
The Intel 82540EP Gigabit Ethernet Controller
architecture is designed to deliver both high-
performance networking and PCI bus efficiency with
the lowest power and smallest size. Using state logic
design with a pipelined DMA Unit and 128-bit-wide
buses for the fastest performance, the 82540EP
controller handles Gigabit Ethernet traffic with low
network latency and minimal internal processing
overhead. The controller's architecture includes
independent transmit and receive queues to limit PCI
bus traffic, and a PCI interface that maximizes the use
of bursts for efficient bus usage. The Intel 82540EP
Gigabit Ethernet Controller prefetches up to 64 packet
descriptors in a single burst for efficient PCI-bandwidth
usage. A 64KB, on-chip packet buffer maintains
superior performance as available PCI bandwidth
changes. Advanced interrupt moderation hardware
manages interrupts generated by the 82540EP
controller to further improve system efficiency. In
addition, using hardware acceleration, the controller
also offloads tasks from the host processor,
such as TCP/UDP/IP checksum calculations and
TCP segmentation.
Applications
The Intel
82540EP Gigabit Ethernet Controller is
designed for use in the following applications:
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LAN on Motherboard (LOM) in desktop, mobile and
other space-constrained designs
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Communications and networking devices requiring
improved performance over 10/100 Ethernet
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Gigabit Ethernet connectivity for embedded clients
such as Web kiosks and POS terminals
Characteristics
Electrical
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PCI Signaling
3.3V and 5V
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Typical targeted power dissipation
1.4W at D0 1000Mbps
430 mW at D3 100Mbps
20 mW at D3 wake up disabled
Environmental
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Operating temperature
0C to 70C (maximum); Does not require a heat sink or forced airflow.
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Storage temperature
-65C to 140C
Physical
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Package
196-pin TFBGA, 1mm ball pitch, 15 X 15mm (Simplifies LOM board designs).
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Footprint-compatible with Intel
82551QM, 82551ER,
Enables a Gigabit Ethernet or 10/100 LOM implementation on the same board.
82562EZ and 82562EX Fast Ethernet Controllers
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Pin compatible with Intel
82540EM Gigabit
Enables easy migration
Ethernet Controller
NP2103-002.qxd 8/30/02 10:36 AM Page 2
Features
Benefits
PCI Bus Features
PCI revision 2.3, 32-bit, 33/66MHz
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Application flexibility in LOM or embedded use
CLKRUN# Signal
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PCI clock suspension for low power mobile design
Cardbus Information Services (CIS) Pointer
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Enables CardBus operation
MAC Specific Features
64KB configurable RX and TX packet FIFO
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No external FIFO memory requirements
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FIFO size tunable to the application
Low-latency transmit and receive queues
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Network packets handled without waiting or buffer overflow
IEEE 802.3x-compliant flow-control support with software-controllable
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Reduced frame loss due to receive FIFO overrun
Caches up to 64 packet descriptors in a single burst
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Efficient PCI-bandwidth usage
Programmable host memory receive buffers (256B to 16KB);
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Efficient usage of PCI bandwidth
Programmable cache line size from 16B to 256B
Gigabit PHY Specific Features
Integrated PHYs for 10/100/1000Mb/s full- and half-duplex operation
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Reduced board space and lower power dissipation
IEEE 802.3ab Auto-Negotiation
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Automatic link configuration including speed, duplex, and flow control
Proven PHY compatible with IEEE 802.3ab
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Robust operation over the installed base of CAT-5 twisted-pair cabling at
lengths greater than 100m
State-of-the-art DSP architecture implements digital adaptive
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Robust 1000Mb/s performance in noisy environments
equalization, echo, cross-talk and baseline wander cancellation
and despite severe cable installation problems
PHY detects polarity, MDI-X, 2 pair vs. 4 pair cables, and cable length
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Easier network installation and maintenance
Host Offloading Features
Transmit TCP segmentation IP, TCP, and UDP checksum off-loading
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Increased throughput and lower CPU utilization. Compatible with large send
offload capabilities on RX and TX
feature found in Windows* 2000 and Windows* XP
Advanced packet filtering
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16 exact matched (unicast or multicast)
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Promiscuous (unicast/multicast) transfer mode
IEEE 802.1Q VLAN support with VLAN tag insertion and stripping
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Enables IT staff to easily create multiple virtual LAN segments
and packet filtering for up to 4096 VLAN tags
Descriptor ring management hardware for TX and RX
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Improved fetching and write-back mechanisms for efficient system memory
and PCI bandwidth usage
Jumbo frame support up to 16KB
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High throughput for large data transfers on networks supporting jumbo frames
Interrupt moderation controls
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Reduces the number of interrupts generated by receive and transmit operations
Manageability Features
On-chip SMBus 2.0 port
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Enables IPMI and ASF implementations
ASF 1.0 alerting
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Provides alerting and remote-control capabilities with standardized interfaces
Compliance with PCI Power Management v1.1/ACPI v2.0
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PCI power management capability requirements for PC and embedded
applications
Wake on LAN
TM
(WoL)* support
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Packet recognition and wakeup for network adapter and LOM applications
without software configuration
Automatic link speed switching from 1000Mb/s down
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Low power in standby states
to 10 or 100Mb/s in standby
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Supports power-down states without software assistance
Smart Power Down mode when no signal is detected on the wire
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Enables very low power mobile or battery powered implementations
Two-pair and three-pair downshift
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Assures link under adverse cable configurations
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Supports modular hardware accessories
Power Save mode switches link speed from 1000Mb/s down to
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Manages power consumption based on power source
10 or 100Mb/s when on battery power
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Longer battery life for battery powered implementations
Additional Device Features
Four programmable LED outputs
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Indications for link speed, activity, duplex, collisions, pause by flow control,
PCI speed, PCI width, and port ID on each port
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Allows design customization without affecting software drivers
Internal PLL for clock generation using a 25MHz crystal or a 25MHz oscillator
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Lower component count and cost
On-chip power regulator control circuitry
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Fewer on-board power supply regulators
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Simplified power supply design
LAN Disable Pin
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Enables low power LAN disable for LOM applications
Intel
82540EP
Product Brief
NP2103-002.qxd 8/30/02 10:36 AM Page 3
Product Brief
Intel
82540EP
Intel Access
Developer's Site:
developer.intel.com
Embedded Intel
Architecture Home Page:
developer.intel.com/design/intarch
Other Intel Support:
Intel Literature Center developer.intel.com/design/litcentr/
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International locations please contact your local sales office.
General Information Hotline:
(800) 628-8686 or (916) 356-3104 5 a.m. to 5 p.m. PST
For more information, visit the Intel Web site at:
developer.intel.com
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