Overview
The Intel
82544EI and 82544GC Gigabit Ethernet Controllers with Integrated PHY are Intel's
single-chip Gigabit Ethernet Solutions. The Intel 82544EI Gigabit Ethernet Controller is available
in a 27x27mm package for standard servers or workstations, and the Intel 82544GC Gigabit
Ethernet Controller is available in a reduced-size, 21x21mm package, for ultra-dense or space-
constrained servers.
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Over 50% smaller than the smallest two-chip solution
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Consumes up to 50% less power than other solutions
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Supports PCI-X for faster network performance
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Integrated third-generation MAC and proven IEEE 803.3ab compatible PHY
Product Description
The Intel 82544EI and 82544GC Gigabit Ethernet Controllers are integrated, third-generation,
Ethernet-LAN components, capable of supporting 1000Mb/s, 100Mb/s, and 10Mb/s data rates. These
single-chip devices allow faster, smaller, simpler designs. The 82544EI and 82544GC manage both the
MAC and PHY layer functions, and are optimized for LAN on Motherboard (LOM) designs, enterprise
networking, and Internet appliances that use the Peripheral Component Interconnect (PCI) or PCI-X
bus. The controllers provide a direct 32/64 bit, 33/66MHz interface to the PCI bus that supports the PCI
Local Bus Specification (revision 2.2), as well as the emerging PCI-X extension to the PCI Local Bus
(revision 1.0a) at clock rates up to 133MHz.
The Intel 82544EI and 82544GC Gigabit Ethernet Controllers provide an interface to host processors
using on-chip command and status registers, and a shared host-memory area. The controller's descriptor
ring management architecture is optimized to deliver both high performance and PCI/PCI-X bus
efficiency. Using hardware acceleration, the controllers can offload various tasks from the host
processor, such as TCP/UDP/IP checksum calculations and TCP segmentation. The Intel 82544EI and
82544GC Gigabit Ethernet Controllers cache up to 64 packet descriptors in a single burst for efficient
PCI-bandwidth usage while the large 64KB on-chip packet buffer maintains superior performance as
available PCI bandwidth descriptors change.
Fully integrated physical-layer circuitry provides a standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3ab, 802.3u, 802.3). And, with the
addition of an appropriate serializer/deserializer (SERDES), the Intel 82544EI and 82544GC
Gigabit Ethernet Controllers alternatively provide an Ethernet interface for 1000BASE-SX or LX
applications (802.3z).
Applications
The Intel 82544EI and 82544GC Gigabit Ethernet Controllers are designed for use in the
following applications:
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LAN on Motherboard (LOM) for servers and workstations
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Industrial PCs including Compact-PCI and PMC designs
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Embedded designs that use a PCI bus (such as Ethernet switches, routers,
firewalls, NAS filers, and other server appliances)
The 82544EI and 82544GC single-chip Gigabit Ethernet (MAC/PHY) solutions take up less space,
making it easier to provide high-speed network connections as a standard part of a system.
Intel
82544 Gigabit
Ethernet Controllers
with Integrated PHY
Network Silicon
Product Brief
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Features
Benefits
PCI/PCI-X Features
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PCI revision 2.2 at 32/64 bit, 33/66MHz
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Application flexibility in LOM or embedded use
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64-bit addressing for systems with more than 4GB of physical memory
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PCI-X, rev.1.0a compliant host interface at clock rates up to 133MHz
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Optimized server bus performance
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Algorithms that optimally use advanced PCI MWI, MRM,
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Efficient bus operations
MRL and PCI-X MRD, MRB, and MWB commands
Network Interface (MAC) Features
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Low-latency transmit and receive queues
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Network packets handled without waiting or buffer overflow
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TBI interface, in addition to internal PHY, for
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Single device to interface with fiber or CAT-5 twisted-pair transmission
IEEE 802.3z full-duplex operation with SERDES
mediums
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IEEE 802.3x compliant flow control support with software controllable
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Control over the transmission of pause frames through software or
pause times and threshold values
hardware triggering
Internal Transceiver (PHY) Features
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Integrated PHY for 10/100/1000Mb/s full and half operation
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Reduced board space and lower power dissipation compared to
multichip MAC/PHY solutions
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IEEE 802.3ab Auto-Negotiation
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Automatic link configuration including speed, duplex, and flow control
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Proven PHY compatible with IEEE 802.3ab
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Robust operation over the installed base of CAT-5 twisted-pair cabling
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State-of-the-art DSP architecture implements digital adaptive
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Robust performance in noisy environments
equalization, echo cancellation, and cross-talk cancellation
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Tolerance of common electrical signal impairments
Host Offloading Features
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RX and TX IP and TCP/UDP checksum off-loading capabilities
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Reduced host CPU utilization
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Transmit TCP segmentation offloads host by sending up to 64K of
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Increased throughput and lower CPU utilization. Compatible with large
block TCP data to network controller
send offload feature found in Windows* XP
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Advanced packet filtering
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16 exact matched (unicast or multicast)
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4096-bit hash filter for multicast frames
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Promiscuous (unicast/multicast) transfer mode
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Optional filtering of erred frames
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IEEE 802.1Q VLAN support
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VLAN tag insertion and stripping
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Packet filtering for up to 4096 VLAN tags
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Descriptor ring management hardware for TX and RX
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Optimized fetching and write-back mechanisms for efficient system memory
and PCI bandwidth usage
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16KB jumbo frame support
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High throughput for large data transfers on compatible network segments
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Interrupt coalescing (more than one packet per interrupt)
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Reduced interrupts generated by RX and TX operations, increasing throughput
Memory Features
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Programmable host memory receive buffers (256B to 16KB)
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Efficient usage of PCI bandwidth
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Programmable cache line size from 16B to 256B
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128-bit internal data path architecture
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Superior DMA transfer rate performance
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Independent transmit and receive queues
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Enables simultaneous access by multiple CPUs
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64KB of configurable RX and TX Packet FIFOs
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No external FIFO memory requirements
Management Features
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SDG3.0, WfM 2.0, PC2001 compliance
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Remote network management capabilities via DMI 2.0 and SNMP software
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Pre-boot eXecution Environment (PXE) Flash interface support
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Local flash interface for a PXE image
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ACPI, PCI Power Management, Version 1.1 compliance
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PCI power management capability requirements for NIC and LOM applications
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SNMP and RMON statistic counters
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Ease of monitoring system status
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Wake on LAN* support
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Packet recognition and wakeup for NIC and LOM applications without
software configuration
Additional Items
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Six activity and link indication outputs that directly drive LEDs
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Indications for Link, RX, TX, and 10, 100, 1000Mb/s
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PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDI-X
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Easier network installation and maintenance at all speeds
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No need to know the difference between crossover and non-crossover cables
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End-to-end wiring tolerance
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Internal PLL for clock generation using a 25MHz crystal or a
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Lower component count and cost
25MHz oscillator
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JTAG (IEEE 1149.1) Test Access Port built in
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Simplified testing using boundary scan
Characteristics
Electrical
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PCI Signaling
3.3V or 5V environments
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Power Dissipation
2.1W (typical). Low power and heat optimized for space-constrained applications.
Environmental
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Operating temperature
82544EI: 0C to 70C (maximum); 82544GC: 0C to 55C (maximum). Does not require a heat sink or forced airflow.
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Storage temperature
-65C to 140C
Physical
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Two package sizes to simplify LOM
82544EI: 416 pin PBGA, 27x27mm
and embedded board designs
82544GC: 364 pin TFBGA, 21x21mm
For more information, contact your Intel
sales representative.
Intel Corporation 2001. All rights reserved.
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Intel may make changes to specifications and product descriptions at any time, without notice.
Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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