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Электронный компонент: 82545EM

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The Intelligent Way to Connect
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Footprint compatibility with Intel's latest Gigabit connections allows for flexible designs
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Reduced power usage and heat generation for lower system costs and higher density
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Enhanced manageability and system health monitoring with ASF 1.0 and SMBus 2.0
Product Description
The Intel
82545EM Gigabit Ethernet Controller incorporates integrated Gigabit Ethernet MAC and
PHY layer functions in a single, compact component. Packaged in a 21x21mm TFBGA, the Intel
82545EM Gigabit Ethernet Controller is physically and electrically compatible with the Intel
82546EB Dual Port Gigabit Ethernet Controller, allowing for a flexible, single-port or dual-port,
multipurpose design.
The Intel 82545EM integrates Intel's fourth-generation Gigabit MAC design with fully integrated,
physical-layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, 802.3ab). For fiber-optic applications, the
Intel 82545EM's integrated SERDES supports 1000BASE-X (802.3z). In addition, the controller
provides a direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant bus at clock
frequencies up to 133MHz.
The Intel 82545EM on-board SMBus port enables enhanced manageability and system health
monitoring via the LAN: management packets can be routed to or from a management processor.
The SMBus port enables implementation of industry standards, such as IPMI (Intelligent Platform
Management Interface). In addition, ASF 1.0 (Alert Standard Format) circuitry provides alerting and
remote-control capabilities with standardized interfaces.
The Intel 82545EM Gigabit Ethernet Controller architecture is optimized to deliver both high-
performance networking and PCI/PCI-X bus efficiency. Using state-logic design with a pipelined DMA
Unit and 128-bit-wide buses for the fastest performance, the 82545EM controller handles Gigabit
Ethernet traffic with low network latency and minimal internal processing overhead. The controller's
architecture includes independent transmit and receive queues to limit PCI bus traffic, and a PCI
interface that maximizes the use of bursts for efficient bus usage. The Intel 82545EM Gigabit Ethernet
Controller prefetches up to 64 packet descriptors in a single burst for efficient PCI-bandwidth usage. A
64KB on-chip packet buffer maintains superior performance as available PCI bandwidth changes.
Advanced interrupt moderation hardware manages interrupts generated by the 82545EM controller to
further improve system efficiency. In addition, using hardware acceleration, the controller also offloads
tasks from the host processor, such as TCP/UDP/IP checksum calculations and TCP segmentation.
Applications
The Intel
82545EM Gigabit Ethernet Controller is designed for use in LAN on Motherboard (LOM) in
high-performance workstations and servers.
Intel
82545EM
Gigabit Ethernet
Controller
High-Performance Gigabit Connectivity
for Servers and Workstations
Product Brief
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Intel Corporation 2003. All rights reserved.
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Information in this document is provided in connection with Intel
products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
* Other names and brands may be claimed as the property of others.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Features
Benefits
PCI/PCI-X Features
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133MHz PCI-X bus
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Supports bandwidth to allow wire-speed performance of a Gigabit Ethernet
connection
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PCI revision 2.2, 32/64-bit, 33/66MHz
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Application flexibility in LOM or embedded use
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64-bit addressing for systems with more than 4GB of physical memory
MAC Specific Features
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64KB configurable RX and TX packet FIFO
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No external FIFO memory requirements
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FIFO size tunable to the application
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Low-latency transmit and receive queues
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Network packets handled without waiting or buffer overflow
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IEEE 802.3x-compliant flow-control support with software controllable
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Reduced frame loss due to receive FIFO overrun
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Caches up to 64 packet descriptors in a single burst
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Efficient PCI-bandwidth usage
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Programmable host memory receive buffers (256B to 16KB);
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Efficient usage of PCI bandwidth
Programmable cache line size from 16B to 256B
Gigabit PHY Specific Features
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Integrated PHYs for 10/100/1000Mb/s full- and half-duplex operation
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Reduced board space and lower power dissipation
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IEEE 802.3ab Auto-Negotiation
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Automatic link configuration including speed, duplex, and flow control
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Proven PHY compatible with IEEE 802.3ab
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Robust operation over CAT-5 twisted-pair cabling at lengths over 100m
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State-of-the-art DSP architecture implements digital adaptive
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Robust 1000Mb/s performance in noisy environments and despite severe cable
equalization, echo, cross-talk and baseline wander cancellation
installation problems
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PHY detects polarity, MDI-X, 2 pair vs. 4 pair cables, and cable length
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Easier network installation and maintenance
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Internal Serializer-Deserializers (SERDES)
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Solution for server blade backplane connections and Fiber Gigabit Ethernet
Host Offloading Features
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Transmit TCP segmentation IP, TCP, and UDP checksum off-loading
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Increased throughput and lower CPU utilization. Compatible with large send
capabilities on RX and TX
offload feature found in Windows* 2000 and Windows* XP
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Advanced packet filtering
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16 exact matched (unicast or multicast)
`
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Promiscuous (unicast/multicast) transfer mode
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IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and
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Enables IT staff to easily create multiple virtual LAN segments
packet filtering for up to 4096 VLAN tags
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Descriptor ring management hardware for TX and RX
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Optimized fetching and write-back mechanisms for efficient system memory
and PCI bandwidth usage
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Jumbo frame support up to 16KB
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High throughput for large data transfers on networks supporting jumbo frames
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Interrupt moderation controls
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Reduces the number of interrupts generated by receive and transmit operations
Manageability Features (available on both ports)
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On-chip SMBus 2.0 port
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Enables IPMI, and ASF implementations
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ASF 1.0 alerting
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Provides alerting and remote-control capabilities with standardized interfaces
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Compliance with PCI Power Management v1.1/ACPI v2.0
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PCI power management capability requirements for PC and embedded
applications
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Wake on LAN (WoL) support
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Packet recognition and wakeup for network adapter and LOM applications
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Automatic link speed switching from 1000Mb/s down to 10 or 100Mb/s
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Low power in standby states
in standby
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Supports power-down states without software assistance
Additional Device Features
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Four programmable LED outputs
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Indications for link speed, activity, duplex, collisions, pause by flow control,
PCI speed, PCI width, and port ID on each port
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Allows design customization without affecting software drivers
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Internal PLL for clock generation using a 25MHz crystal or a
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Lower component count and cost
25MHz oscillator
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On-chip power regulator control circuitry
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Simplified power supply design
Characteristics
Electrical
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PCI Signaling
3.3V and 5V
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Power Dissipation
2.0W (typical)
Environmental
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Operating temperature
0C to 70C (maximum); Does not require a heat sink or forced airflow
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Storage temperature
-65C to 140C
Physical
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Package
364-pin TFBGA. 1mm ball pitch, 21 x 21mm (Saves critical space on LOM board designs).
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Footprint-compatible with Intel
82546EB
Enables a single-port or dual-port implementation on the same board.
dual-port Gigabit Ethernet Controller
For more information, contact your Intel
sales representative.
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