2
Intel
82801CA ICH3-S
Datasheet
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
I/O Controller Hub 3 (ICH3-S) component may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
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I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Intel, Pentium, Intel SpeedStep and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright 2002, Intel Corporation
Intel
82801CA ICH3-S
Datasheet
3
Intel
82801CA ICH3-S Features
s
PCI Bus Interface
-- Supports PCI Rev 2.2 Specification at 33 MHz
-- 133 MByte/sec maximum throughput
-- Supports up to 6 master devices on PCI
-- One PCI REQ/GNT pair can be given higher
arbitration priority (intended for external
IEEE 1394 host controller)
s
Integrated LAN Controller
-- WfM 2.0 Compliant
-- Interface to discrete Platform LAN Connect
component
-- 10/100 Mbit/sec Ethernet support
s
Integrated IDE Controller
-- New: Supports "Native Mode" Register and
Interrupt support
-- Independent timing of up to 4 drives, with separate
IDE connections for Primary and Secondary
cables
-- Ultra ATA/100/66/33, BMIDE and PIO modes
s
USB
-- New: Includes 3 UHCI Host Controllers,
increasing the number of external ports to six
-- Supports wake-up from sleeping states S1-S4
-- Supports legacy Keyboard/Mouse software
s
AC'97 Link for Audio and Telephony CODECs
-- Audio Codec '97, Revision 2.2 compliant
-- Independent bus master logic for 5 channels (PCM
In/Out, Mic Input, Modem In/Out)
-- Separate independent PCI functions for Audio and
Modem
-- Support for up to six channels of PCM audio
output (full AC3 decode)
-- Supports wake-up events
s
Interrupt Controller
-- Support up to 8 PCI interrupt pins
-- Supports PCI 2.2 Message Signaled Interrupts
-- Two cascaded 82C59 with 15 interrupts
-- Integrated I/O APIC capability with 24 interrupts
-- Supports Serial Interrupt Protocol
-- Supports Processor System Bus interrupt delivery
s
1.8 V operation with 3.3 V I/O
-- 5V tolerant buffers on IDE, PCI, USB Over-
current and Legacy signals
s
Timers Based on 82C54
-- System timer, Refresh request, Speaker tone
output
s
External Glue Integration
-- Integrated Pull-up, Pull-down and Series
Termination resistors on IDE, processor interface,
and USB
s
Power Management Logic
-- ACPI 1.0 compliant
-- ACPI-defined power states (C1C2, S3S5)
-- ACPI Power Management Timer
-- PME# support
-- SMI# generation
-- All registers readable/restorable for proper resume
from 0 V suspend states
-- Support for APM-based legacy power
management for non-ACPI implementations
s
Firmware Hub (FWH) Interface supports BIOS
Memory size up to 8 MB
s
Low Pin count (LPC) Interface
-- Allows connection of legacy ISA and X-Bus
devices such as Super I/O
-- Supports two Master/DMA devices.
s
Enhanced DMA Controller
-- Two cascaded 8237 DMA controllers
-- PCI DMA: Supports PC/PCI--Includes two
PC/PCI REQ#/GNT# pairs
-- Supports LPC DMA
-- Supports DMA Collection Buffer to provide
Type-F DMA performance for all DMA channels
s
Real-Time Clock
-- 256-byte battery-backed CMOS RAM
s
System TCO Reduction Circuits
-- Timers to generate SMI# and Reset upon detection
of system hang
-- Timers to detect improper processor reset
-- Integrated processor frequency strap logic
-- New: Supports ability to disable external devices
s
SMBus
-- Host interface allows processor to communicate
via SMBus
-- Slave interface allows an external Microcontroller
to access system resources
-- Compatible with most 2-Wire components that are
also I
2
C* compatible
-- New: Supports SMBus 2.0 Specification
s
GPIO
-- TTL, Open-Drain, Inversion
s
New: Package 31x31 mm 421 BGA
The Intel
82801CA ICH3-S may contain design defects or errors known as errata which may cause the products to deviate
from published specifications. Current characterized errata are available on request.
Intel
82801CA ICH3-S
Datasheet
5
Contents
1
Introduction
...........................................................................................................29
1.1
About This Datasheet ....................................................................................29
1.2
Overview ........................................................................................................31
2
Signal Description
..............................................................................................37
2.1
Hub Interface to Host Controller ....................................................................39
2.2
Link to LAN Connect ......................................................................................39
2.3
EEPROM Interface ........................................................................................39
2.4
Firmware Hub Interface .................................................................................40
2.5
PCI Interface ..................................................................................................40
2.6
IDE Interface ..................................................................................................43
2.7
LPC Interface .................................................................................................44
2.8
Interrupt Interface...........................................................................................44
2.9
USB Interface.................................................................................................45
2.10
Power Management Interface........................................................................45
2.11
Processor Interface........................................................................................46
2.12
SMBus Interface ............................................................................................48
2.13
System Management Interface ......................................................................48
2.14
Real Time Clock Interface..............................................................................48
2.15
Other Clocks ..................................................................................................49
2.16
Miscellaneous Signals ...................................................................................49
2.17
AC '97 Link.....................................................................................................49
2.18
General Purpose I/O ......................................................................................50
2.19
Power and Ground.........................................................................................51
2.20
Pin Straps ......................................................................................................52
2.20.1 Functional Straps ..............................................................................52
2.20.2 External RTC Circuitry ......................................................................53
2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................53
2.20.4 Test Signals ......................................................................................54
2.20.4.1 Test Mode Selection..........................................................54
3
Power Planes and Pin States
.........................................................................55
3.1
Power Planes.................................................................................................55
3.2
Integrated Pull-Ups and Pull-Downs ..............................................................56
3.3
IDE Integrated Series Termination Resistors.................................................56
3.4
Output and I/O Signals Planes and States ....................................................57
3.5
Power Planes for Input Signals......................................................................60
4
Intel
ICH3 and System Clock Domains
....................................................63
5
Functional Description
.....................................................................................65
5.1
Hub Interface to PCI Bridge (D30:F0)............................................................65
5.1.1
PCI Bus Interface..............................................................................65
5.1.2
PCI-to-PCI Bridge Model ..................................................................66
5.1.3
IDSEL to Device Number Mapping ...................................................66
5.1.4
SERR# Functionality.........................................................................66
5.1.5
Parity Error Detection........................................................................68
5.1.6
Standard PCI Bus Configuration Mechanism ...................................69
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