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Intel
82801DBM ICH4-M Datasheet
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
I/O Controller Hub 4 Mobile (ICH4-M) chipset component may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
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Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright 2002, Intel Corporation
Intel
82801DBM ICH4-M Datasheet
3
Intel
82801DBM ICH4 Features
PCI Bus Interface
-- Supports PCI Revision 2.2 Specification at
33 MHz
-- 133 MB/sec maximum throughput
-- Supports up to 6 master devices on PCI
-- One PCI REQ/GNT pair can be given higher
arbitration priority (intended for external 1394
host controller)
-- Support for 44-bit addressing on PCI using DAC
protocol
Integrated LAN Controller
-- WfM 2.0 and IEEE 802.3 compliant
-- LAN Connect Interface (LCI)
-- 10/100 Mbit/sec ethernet support
Integrated IDE Controller
-- Supports "Native Mode" register and interrupts
-- Independent timing of up to 4 drives, with separate
primary and secondary IDE cable connections
-- Ultra ATA/100/66/33, BMIDE and PIO modes
-- Tri-state modes to enable swap bay
USB
-- Includes 3 UHCI host controllers that support 6
external ports
-- New: Includes 1 EHCI high-speed USB 2.0 Host
Controller that supports all six ports
-- New: Supports a USB 2.0 high-speed debug port
-- Supports wake-up from sleeping states S1-MS5
-- Supports legacy keyboard/mouse software
AC'97 Link for Audio and Telephony CODECs
-- New: Third AC_SDATA_IN line for three codec
support
-- Supports AC '97 2.3
-- New: Independent bus master logic for 7 channels
(PCM In/Out, Mic 1 input, Mic 2 input, modem
in/out, S/PDIF out)
-- Separate independent PCI functions for audio and
modem
-- Support for up to six channels of PCM audio
output (full AC3 decode)
-- Supports wake-up events
Interrupt Controller
-- Support up to 8 PCI interrupt pins
-- Supports PCI 2.2 message signaled interrupts
-- Two cascaded 82C59 with 15 interrupts
-- Integrated I/O APIC capability with 24 interrupts
-- Supports serial interrupt protocol
-- Supports processor system bus interrupt delivery
New: 1.5 V operation with 3.3 V I/O
-- 5V tolerant buffers on IDE, PCI, USB over-current
and legacy signals
Timers Based on 82C54
-- System timer, refresh request, speaker tone output
Power Management Logic
-- ACPI 2.0 compliant
-- ACPI-defined power states (C1C4, S1-M,
S3S5)
-- ACPI power management timer
-- Support for "Intel
SpeedStep
TM
technology"
processor power control
-- (Support for "Deeper Sleep" power state
-- PCI CLKRUN# and PME# support
-- SMI# generation
-- All registers readable/restorable for proper resume
from 0 V suspend states
External Glue Integration
-- Integrated pull-up, pull-down and series
termination resistors on IDE, processor interface
-- Integrated Pull-down and Series resistors on USB
Enhanced Hub Interface buffers improve routing
flexibility (Not available with all Memory Controller
Hubs)
Firmware Hub (FWH) Interface supports BIOS
memory size up to 8 MB
Low Pin Count (LPC) Interface
-- Supports two Master/DMA devices.
Enhanced DMA Controller
-- Two cascaded 8237 DMA controllers
-- PCI DMA: Supports PC/PCI -- Includes two
PC/PCI REQ#/GNT# pairs
-- Supports LPC DMA
-- Supports DMA collection buffer to provide
Type-F DMA performance for all DMA channels
Real-Time Clock
-- 256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
-- Timers to generate SMI# and Reset upon detection
of system hang
-- Timers to detect improper processor reset
-- Supports ability to disable external devices
SMBus
-- New: Hardware packet error checking
-- New: Supports SMBus 2.0 Specification
-- Host interface allows processor to communicate
via SMBus
-- Slave interface allows an external microcontroller
to access system resources
-- Compatible with most 2-wire components that are
also I
2
C compatible
GPIO
-- TTL, open-drain, inversion
Package 31x31 mm 421 BGA
The Intel
82801DBM ICH4-M may contain design defects or errors known as errata which may cause the products to deviate
from published specifications. Current characterized errata are available on request.
Intel
82801DBM ICH4-M Datasheet
5
Contents
1
Introduction
...........................................................................................................33
1.1
About This Datasheet ....................................................................................33
1.2
Overview ........................................................................................................36
2
Signal Description
..............................................................................................43
2.1
Hub Interface to Host Controller ....................................................................45
2.2
Link to LAN Connect ......................................................................................45
2.3
EEPROM Interface ........................................................................................46
2.4
Firmware Hub Interface .................................................................................46
2.5
PCI Interface ..................................................................................................46
2.6
IDE Interface ..................................................................................................49
2.7
LPC Interface .................................................................................................50
2.8
Interrupt Interface...........................................................................................50
2.9
USB Interface.................................................................................................51
2.10
Power Management Interface........................................................................52
2.11
Processor Interface........................................................................................54
2.12
SMBus Interface ............................................................................................55
2.13
System Management Interface ......................................................................55
2.14
Real Time Clock Interface..............................................................................56
2.15
Other Clocks ..................................................................................................56
2.16
Miscellaneous Signals ...................................................................................56
2.17
AC'97 Link......................................................................................................57
2.18
General Purpose I/O ......................................................................................58
2.19
Power and Ground.........................................................................................59
2.20
Pin Straps ......................................................................................................60
2.20.1 Functional Straps ..............................................................................60
2.20.2 External RTC Circuitry ......................................................................61
2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................61
2.20.4 Test Signals ......................................................................................62
2.20.4.1 Test Mode Selection..........................................................62
3
Intel
ICH4-M Power Planes and Pin States
............................................63
3.1
Power Planes.................................................................................................63
3.2
Integrated Pull-Ups and Pull-Downs ..............................................................64
3.3
IDE Integrated Series Termination Resistors.................................................64
3.4
Output and I/O Signals Planes and States ....................................................65
3.5
Power Planes for Input Signals......................................................................69
4
Intel
ICH4-M System Clock Domains
........................................................71
5
Functional Description
.....................................................................................73
5.1
Hub Interface to PCI Bridge (D30:F0)............................................................73
5.1.1
PCI Bus Interface..............................................................................73
5.1.2
PCI-to-PCI Bridge Model ..................................................................74
5.1.3
IDSEL to Device Number Mapping ...................................................74
5.1.4
SERR# Functionality.........................................................................74
5.1.5
Parity Error Detection........................................................................76
5.1.6
Standard PCI Bus Configuration Mechanism ...................................77
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