82815EP and 82815P MCH

Datasheet

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The

Intel

82815EP and 82815P chipset MCH

may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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82815EP and 82815P MCH

Datasheet

Contents

Overview .................................................................................................................................... 11

1.1.

Related Documents....................................................................................................... 11

1.2.

The Intel

815EP Chipset Family .................................................................................. 12

1.3.

82815EP MCH Overview............................................................................................... 14

1.4.

Host Interface ................................................................................................................ 15

1.5.

System Memory Interface ............................................................................................. 15

1.6.

AGP Interface................................................................................................................ 16

1.7.

Hub Interface................................................................................................................. 16

1.8

System Clocking............................................................................................................ 17

1.9

MCH Power Delivery ..................................................................................................... 17

Signal Description ...................................................................................................................... 19

2.1.

Host Interface Signals ................................................................................................... 20

2.2.

System Memory Interface Signals................................................................................. 21

2.3.

AGP Interface Signals ................................................................................................... 22

2.3.1.

AGP Addressing Signals ............................................................................. 22

2.3.2.

AGP Flow Control Signals........................................................................... 23

2.3.3.

AGP Status Signals..................................................................................... 23

2.3.4.

AGP Clocking Signals (Strobes) ................................................................. 24

2.3.5.

AGP FRAME# Signals ................................................................................ 25

2.4.

Hub Interface Signals .................................................................................................... 27

2.5

Power Signals................................................................................................................ 28

2.5

Power Signals................................................................................................................ 28

2.5.

Clock Signals................................................................................................................. 28

2.6.

MCH Power-Up/Reset Strap Options............................................................................ 28

Configuration Registers.............................................................................................................. 31

3.1.

3.2.

PCI Configuration Space Access .................................................................................. 31

3.2.1.

PCI Bus Configuration Mechanism ............................................................. 32

3.2.2.

Logical PCI Bus #0 Configuration Mechanism ............................................ 32

3.2.3.

Primary PCI (PCI0) and Downstream Configuration Mechanism ............... 33

3.2.4.

MCH Register Introduction .......................................................................... 33

3.3.

I/O Mapped Registers ................................................................................................... 33

3.3.1.

CONF_ADDR

Configuration Address Register ........................................ 33

3.3.2.

CONF_DATA

Configuration Data Register .............................................. 35

3.4.

Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ................... 36

3.4.1.

VID--Vendor Identification Register (Device 0) .......................................... 38

3.4.2.

DID--Device Identification Register (Device 0)........................................... 38

3.4.3.

PCICMD--PCI Command Register (Device 0) ........................................... 39

3.4.4.

PCISTS--PCI Status Register (Device 0)................................................... 40

3.4.5.

RID--Revision Identification Register (Device 0)........................................ 41

3.4.6.

SUBC--Sub-Class Code Register (Device 0)............................................. 41

3.4.7.

BCC--Base Class Code Register (Device 0) ............................................. 41

3.4.8.

MLT--Master Latency Timer Register (Device 0)....................................... 42

3.4.9.

HDR--Header Type Register (Device 0) .................................................... 42

3.4.10.

APBASE--Aperture Base Configuration Register (Device 0: AGP Mode

Only) ........................................................................................................ 42

82815EP and 82815P MCH

Datasheet

3.4.11.

SVID--Subsystem Vendor Identification Register (Device 0) .....................44

3.4.12.

SID--Subsystem Identification Register (Device 0) ....................................44

3.4.13.

CAPPTR--Capabilities Pointer (Device 0) ..................................................44

3.4.14.

MCHCFG--MCH Configuration Register (Device 0) ...................................45

3.4.15.

APCONT--Aperture Control (Device 0) ......................................................47

3.4.16.

DRP--DRAM Row Population Register (Device 0) .....................................48

3.4.17.

DRAMT--DRAM Timing Register (Device 0) ..............................................49

3.4.18.

DRP2--DRAM Row Population Register 2 (Device 0) ................................50

3.4.19.

FDHC--Fixed DRAM Hole Control Register (Device 0) ..............................51

3.4.20.

PAM--Programmable Attributes Map Registers (Device 0)........................51

3.4.21.

SMRAM--System Management RAM Control Register (Device 0) ...........56

3.4.22.

MISCC--Miscellaneous Control Register (Device 0) ..................................58

3.4.23.

CAPID--Capability Identification (Device 0: AGP Mode Only) ....................60

3.4.24.

BUFF_SC--System Memory Buffer Strength Control Register (Device 0) .61

3.4.25.

BUFF_SC2--System Memory Buffer Strength Control Register 2 (Device 0)64

3.4.26.

SM_RCOMP--System Memory R Compensation Control Register (Device

0) ........................................................................................................65

3.4.27.

SM--System Memory Control Register .......................................................66

3.4.28.

ACAPID--AGP Capability Identifier Register (Device 0: AGP Mode Only) 67

3.4.29.

AGPSTAT--AGP Status Register (Device 0: AGP Mode Only)..................68

3.4.30.

AGPCMD--AGP Command Register (Device 0: AGP Mode Only) ............69

3.4.31.

AGPCTRL--AGP Control Register (Device 0: AGP Mode Only) ................70

3.4.32.

APSIZE--Aperture Size (Device 0: AGP Mode Only) .................................71

3.4.33.

ATTBASE--Aperture Translation Table Base Register (Device 0: AGP

Mode Only)

........................................................................................................72

3.4.34.

AMTT--AGP Multi-Transaction Timer (Device 0: AGP Mode Only) ..........73

3.4.35.

LPTT--AGP Low Priority Transaction Timer Register (Device 0: AGP Mode

Only) ........................................................................................................74

3.4.36.

MCHCFG--MCH Configuration Register (Device 0: AGP Mode Only) ......75

3.4.37.

ERRCMD--Error Command Register (Device 0: AGP Mode Only) ...........76

3.5.

AGP/PCI Bridge Registers (Device 1: Visible in AGP Mode Only) ...............................78

3.5.1.

VID1--Vendor Identification Register (Device 1).........................................79

3.5.2.

DID1--Device Identification Register (Device 1) .........................................79

3.5.3.

PCICMD1--PCI-PCI Command Register (Device 1) ..................................79

3.5.4.

PCISTS1--PCI-PCI Status Register (Device 1) ..........................................81

3.5.5.

RID1--Revision Identification Register (Device 1) ......................................82

3.5.6.

SUBC1--Sub-Class Code Register (Device 1) ...........................................82

3.5.7.

BCC1--Base Class Code Register (Device 1) ............................................82

3.5.8.

MLT1--Master Latency Timer Register (Device 1) .....................................83

3.5.9.

HDR1--Header Type Register (Device 1)...................................................83

3.5.10.

PBUSN--Primary Bus Number Register (Device 1)....................................83

3.5.11.

SBUSN--Secondary Bus Number Register (Device 1)...............................84

3.5.12.

SUBUSN--Subordinate Bus Number Register (Device 1) ..........................84

3.5.13.

SMLT--Secondary Master Latency Timer Register (Device 1)...................85

3.5.14.

IOBASE--I/O Base Address Register (Device 1)........................................86

3.5.15.

IOLIMIT--I/O Limit Address Register (Device 1).........................................87

3.5.16.

SSTS--Secondary PCI-PCI Status Register (Device 1) .............................88

3.5.17.

MBASE--Memory Base Address Register (Device 1) ................................89

3.5.18.

MLIMIT--Memory Limit Address Register (Device 1) .................................90

3.5.19.

PMBASE--Prefetchable Memory Base Address Register (Device 1).........91

3.5.20.

PMLIMIT--Prefetchable Memory Limit Address Register (Device 1)..........92

3.5.21.

BCTRL--PCI-PCI Bridge Control Register (Device 1) ................................93

3.5.22.

ERRCMD1--Error Command Register (Device 1)......................................95

Functional Description ................................................................................................................97

82815EP and 82815P MCH

Datasheet

4.1.

System Address Map .................................................................................................... 97

4.1.1.

Memory Address Ranges............................................................................ 98

4.1.2.

Compatibility Area ....................................................................................... 99

4.1.3.

Extended Memory Area............................................................................. 102

4.1.3.1.

System Management Mode (SMM) Memory Range .................... 105

4.2.

Memory Shadowing..................................................................................................... 106

4.3.

I/O Address Space ...................................................................................................... 106

4.3.1.

MCH Decode Rules and Cross-Bridge Address Mapping ........................ 106

4.3.2.

Address Decode Rules.............................................................................. 107

4.3.2.1.

AGP Interface Decode Rules ....................................................... 108

4.3.2.2.

Legacy VGA Ranges .................................................................... 109

4.4.

Host Interface .............................................................................................................. 110

4.4.1.

Host Bus Device Support .......................................................................... 110

4.4.2.

Special Cycles ........................................................................................... 112

4.5.

System Memory DRAM Interface................................................................................ 113

4.5.1.

DRAM Organization and Configuration ..................................................... 113

4.5.1.1.

Configuration Mechanism For DIMMs .......................................... 114

4.5.1.2.

DRAM Register Programming...................................................... 115

4.5.2.

DRAM Address Translation and Decoding ............................................... 115

4.5.3.

DRAM Array Connectivity.......................................................................... 116

4.5.4.

SDRAMT Register Programming .............................................................. 117

4.5.5.

SDRAM Paging Policy............................................................................... 117

4.6.

System Reset for the MCH.......................................................................................... 117

4.7.

System Clock Description ........................................................................................... 117

4.8.

Power Management .................................................................................................... 118

4.8.1.

Specifications Supported........................................................................... 118

Pinout and Package Information.............................................................................................. 119

5.1.

82815EP MCH Pinout ................................................................................................. 119

5.2.

Package Information ................................................................................................... 126

Testability ................................................................................................................................. 129

6.1.

XOR Tree Testability Algorithm Example.................................................................... 130

6.1.1.

Test Pattern Consideration for XOR Chains 3 and 4, and 7 and 8 ........... 130

6.2.

XOR Tree Initialization................................................................................................. 131

6.2.1.

Chain [1:6] Initialization ............................................................................. 131

6.2.2.

Chain [7:8] Initialization ............................................................................. 131

6.3.

XOR Chain .................................................................................................................. 132

6.4.

All Z ............................................................................................................................. 137

82815EP and 82815P MCH

Datasheet

Figures

Figure 1. Intel

815EP Chipset Family System Block Diagram................................................13

Figure 2. 82815EP MCH Block Diagram ..................................................................................14

Figure 3. PAM Registers ..........................................................................................................53

Figure 4. System Memory Address Map ..................................................................................98

Figure 5. Detailed Memory System Address Map ....................................................................98

Figure 6. DRAM Array Sockets ..............................................................................................116

Figure 7. MCH Pinout (Top View-Left Side) ...........................................................................120

Figure 8. MCH Pinout (Top View-Right Side) .........................................................................121

Figure 9. MCH BGA Package Dimensions (Top and Side Views) .........................................126

Figure 10. MCH BGA Package Dimensions (Bottom View) ...................................................127

Figure 11. XOR Tree Implementation ....................................................................................129

Tables

Table 1. Supported System Bus and System Memory Bus Frequencies.................................17

Table 2. MCH PCI Configuration Space (Device 0) .................................................................36

Table 3. Supported System Memory DIMM Configurations .....................................................48

Table 4. Attribute Bit Assignments ...........................................................................................52

Table 5. PAM Registers and Associated Memory Segments...................................................53

Table 6. Summary of MCH Error Sources, Enables and Status Flags.....................................77

Table 7. MCH Configuration Space (Device 1) ........................................................................78

Table 8. Memory Segments and Their Attributes .....................................................................99

Table 9. Summay of Transactions Supported By MCH..........................................................110

Table 10. Host Responses Supported by the MCH................................................................111

Table 11. Special Cycles ........................................................................................................112

Table 12. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations ..114

Table 13. Data Bytes on DIMM Used for Programming DRAM Registers .............................115

Table 14. MCH DRAM Address Mux Function .......................................................................116

Table 15. Programmable SDRAM Timing Parameters ..........................................................117

Table 16. Alphabetical Pin Assignment ..................................................................................122

Table 17. Package Dimensions..............................................................................................127

Table 18. XOR Test Pattern Example ....................................................................................130

Table 19

XOR Chain 1 35 Inputs Output: SMAA5 (A12).......................................................132

Table 20

XOR Chain 2 33 Inputs Output: SMAA2 (F12).......................................................132

Table 21

XOR Chain 3 38 Inputs Output: SMAA0 (D13) ......................................................133

Table 22

XOR Chain 4 36 Inputs Output: SMAA9 (D13) ......................................................133

Table 23

XOR Chain 5 56 Inputs Output: SMD31 (K5).........................................................134

Table 24

XOR Chain 6 60 Inputs Output: SMAA11 (A13).....................................................135

Table 25

XOR Chain 7 33 Inputs Output: SMAA8 (D12) ......................................................136

Table 26

XOR Chain 8 31 Inputs Output: SMAA4 (B12).......................................................136

82815EP and 82815P MCH

Datasheet

82815EP MCH Features

Processor/Host Bus Support

Intel

Pentium

III

processor and Intel

CeleronTM

Processor in FC-PGA package

Supports processor 370-Pin Socket

Supports 32-Bit System Bus Addressing

4 deep in-order queue; 4 or 1 deep request queue

Supports Uni-processor systems only

In-order and Dynamic Deferred Transaction Support

66/100/133MHz System Bus Frequency

GTL+ I/O Buffer

Integrated SDRAM Controller

32 MB to 512 MB using 16Mb/64Mb/128Mb/256Mb
technology

Supports up to 3 double sided DIMMs at 100 MHz system
memory bus

Supports up to 2 double sided or 3 single sided DIMMs at
133 MHz system memory bus.

64-bit data interface

100/133 MHz system memory bus frequency

Support for Asymmetrical SDRAM addressing only

Support for x8 and x16 SDRAM device width

Unbuffered, Non-ECC SDRAM only supported

Refresh Mechanism: CBR ONLY supported

Enhanced Open page arbitration SDRAM paging scheme

Suspend to RAM support

Accelerated Graphics Port (AGP) Interface

Supports a single AGP device via a connector

Supports AGP 2.0 including 4x AGP data transfers

AGP Universal Connector support via dual mode buffers
to allow AGP 2.0 3.3V or 1.5V signaling

AGP PIPE# or SBA initiated accesses to SDRAM not
snooped

AGP FRAME# initiated accesses to SDRAM are snooped

High priority access support

Hierarchical PCI configuration mechanism

Delayed transaction support for AGP-to-SDRAM reads
that can not be serviced immediately

Arbitration Scheme and Concurrency

Intelligent Centralized Arbitration Model for Optimum
Concurrency Support

Concurrent operations of processor and System busses
supported via dedicated arbitration and data buffering

Data Buffering

Distributed Data Buffering Model for optimum
concurrency

SDRAM Write Buffer with read-around-write capability

Dedicated processor SDRAM, hub interface-SDRAM
and Graphics-SDRAM Read Buffers

Power Management Functions

SMRAM space remapping to A0000h (128 KB)

Optional Extended SMRAM space above 256 MB,
additional 512 KB / 1MB TSEG from Top of Memory,
cacheable

Stop Clock Grant and Halt special cycle translation from
the host to the hub interface

ACPI Compliant power management

APIC Buffer Management

SMI, SCI, and SERR error indication

Supporting I/O Bridge

82801AA I/O Controller Hub (ICH)

82801BA I/O Controller Hub (ICH2)

Packaging/Power

544 BGA

1.85V core with 3.3V CMOS I/O

82815EP and 82815P MCH

Datasheet

1. Overview

The Intel

815EP chipset family is a high-flexibility chipset designed to extend from the basic

graphics/multimedia PC platform up to the mainstream performance desktop platform. The chipset
consists of a 82815EP Memory Controller Hub (MCH) and an I/O Controller Hub for the I/O subsystem.
The MCH integrates a system memory SDRAM controller that supports a 64-bit 100/133 MHz SDRAM
array.

The 82815EP MCH integrates an AGP controller interface to enable graphics configuration and upgrade
flexibility with the Intel

815EP chipset family.

There are four chipsets in the Intel

815 chipset family:

Intel

82815 chipset: This chipset contains the 82815 and the 82801AA ICH.

Intel

82815E chipset: This chipset contains the 82815E and the 82801BA ICH2.

Intel

82815EP chipset: This chipset contains the 82815EP and the 82801BA ICH2. There is no

internal graphics capability. This MCH uses an AGP port only.

Intel

82815P chipset: This chipset contains the 82815P and the 82801AA (ICH) and Intel®

82801AB (ICH0). There is no internal graphics capability. This MCH uses an AGP port only.

The only component difference between the Intel

82815 GMCH and the Intel

82815E GMCH is the

I/O Controller Hub.

This datasheet provides an overview of the 815EP chipset family (see Section 1.2). The remainder of the
document describes the Intel

82815EP Memory Controller Hub (MCH).

The Intel

815EP chipset family may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

1.1. Related Documents

I/O Specification: Contained in the Intel

Pentium

II Processor Datasheet

PCI Local bus Specification 2.2: Contact

www.pcisig.com

Intel

82801AA (ICH) and Intel

82801AB (ICH0) I/O Controller Hub Datasheet

(Document Number 290655)

Intel

82801BA I/O Controller Hub (ICH2) Datasheet (Document Number 290687)

Intel

82802 Firmware Hub (FWH) Datasheet (Document Number 290658)

Intel

815EP Chipset Design Guide (Document Number 290692)

Intel

815 Chipset Family: 82815EP and 82815P Memory Controller Hub (MCH)

Specification Update (Document Number 290695)

82815EP and 82815P MCH

Datasheet

1.2. The Intel

815EP Chipset Family

Figure 1 shows a typical system block diagram based on the Intel

815EP chipset family. The chipset

uses a hub architecture with the MCH as the host bridge hub and the I/O Controller Hub as the I/O hub.
The MCH supports processor bus frequencies of 66/100/133 MHz. The I/O Controller Hub is highly
integrated providing many of the functions needed in today's PC platforms; it also provides the interface
to the PCI Bus. The MCH and I/O Controller Hub communicate over a dedicated hub interface.

82801BA ICH2 functions include:

PCI Rev 2.2 compliant with support for 33 MHz PCI operations

Supports up to 6 Req/Gnt pairs (PCI Slots)

Power management logic support

Enhanced DMA controller, interrupt controller, and timer functions

Integrated IDE controller

Ultra ATA/100/66/33

USB host interface

2 host controllers and supports 4 USB ports

Integrated LAN controller

System Management Bus (SMBus) compatible with most I

C devices

ICH2 has both bus master and slave capability

AC'97 2.1 compliant link for audio and telephony codecs

Up to 6 channels

Low Pin Count (LPC) interface

Firmware Hub (FWH) interface support

Intel's FWH component is the 82802: It contains a Random Number Generator (RNG), five
General Purpose Inputs (GPIs), register-based block locking, hardware-based locking, and
Flash memory for platform code/data nonvolatile storage

FWH component is also available from other suppliers

Alert on LAN*

AOL

AOL2

82815EP and 82815P MCH

Datasheet

1.4. Host Interface

The host interface of the MCH is optimized to support the Intel

Pentium

III

processor and Intel

Celeron

processor in the FC-PGA package. The MCH implements the host address, control, and data

bus interfaces within a single device. The MCH supports a 4-deep in-order queue (i.e., supports
pipelining of up to 4 outstanding transaction requests on the host bus) . Host bus addresses are decoded
by the MCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI
configuration space and Graphics memory. The MCH takes advantage of the pipelined addressing
capability of the processor to improve the overall system performance.

The 82815EP MCH supports the 370-pin socket processor.

370-pin socket (PGA370). The PGA370 is a zero insertion force (ZIF) socket that a processor in
the FC-PGA package will use to interface with a system board.

1.5. System Memory Interface

The MCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array.
The only DRAM type supported is industry standard Synchronous DRAM (SDRAM). The SDRAM
controller interface is fully configurable through a set of control registers.

The MCH supports industry standard 64-bit wide DIMMs with SDRAM devices. The thirteen
multiplexed address lines (SMAA[12:0]) along with the two bank select lines (SBS[1:0]) allow the MCH
to support 2M, 4M, 8M, 16M, and 32M x64 DIMMs. Only asymmetric addressing is supported. The
MCH has 6 SCS# lines (2 copies of each for electrical loading), enabling the support of up to six 64-bit
rows of SDRAM. The MCH targets SDRAM with CL2 and CL3, and supports both single and double-
sided DIMMs. Additionally, the MCH also provides a 1024 deep refresh queue. The MCH can be
configured to keep up to 4 pages open within the memory array. Pages can be kept open in any one bank
of memory.

The Intel

815EP chipset family supports up to 3 DIMM connectors in a system. A maximum of 2

double-sided or 3 single-sided DIMMs may be populated when the SDRAM interface is operating at
133 MHz. Upon detection that additional rows are populated beyond these configurations, the BIOS
must down-shift the SDRAM clocks to 100 MHz through a two-wire interface of the system clock
generator.

SCKE[5:0] is used in configurations requiring powerdown mode for the SDRAM.

82815EP and 82815P MCH

Datasheet

1.6. AGP Interface

A single AGP connector is supported by the MCH AGP interface. The AGP buffers operate in one of
two selectable modes in order to support the AGP Universal Connector:

3.3V drive, not 5 volt safe: This mode is compliant to the AGP 1.0 and 2.0 specifications.

1.5V drive, not 3.3 volt safe: This mode is compliant with the AGP 2.0 specification.

The following table shows the AGP Data Rate and the Signaling Levels supported by the MCH.

Signaling Level

Data Rate

1.5V 3.3V

1x AGP

Yes

2x AGP

Yes

4x AGP

Yes

The AGP interface supports 4x AGP signaling. The Intel 82815EP only supports AGP4X cards that use
differential clocking mode.

AGP semantic (PIPE# or SBA[7:0]) cycles to SDRAM are not snooped on the host bus. AGP FRAME#
cycles to SDRAM are snooped on the host bus. The MCH supports PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected
during system initialization. High priority accesses are supported. Only memory writes from the hub
interface to AGP are allowed. No transactions from AGP to the hub interface are allowed.

1.7. Hub Interface

The hub interface is a private interconnect between the MCH and the I/O Controller Hub.

82815EP and 82815P MCH

Datasheet

1.8 System

Clocking

The 82815EP MCH has a new type of clocking architecture. It has integrated SDRAM buffers that run at
either 100 or 133 MHz, independent of the system bus frequency. See table below for supported system
bus and system memory bus frequencies. The system bus frequency is selectable between 66 MHz,
100 MHz, or 133 MHz. The MCH uses a copy of the USB clock as the DOT Clock input for the graphics
pixel clock PLL.

Table 1. Supported System Bus and System Memory Bus Frequencies

Front Side Bus

Frequency

System Memory

Bus Frequency

Display Cache Interface

Frequency

66 MHz

100 MHz

133 MHz or DVMT

100 MHz

133 MHz or DVMT

133 MHz

100 MHz

133 MHz or DVMT

133 MHz

3 MHz or DVMT

1.9

MCH Power Delivery

The 82815EP MCH core voltage is 1.85V. System memory operates from a 3.3V supply. AGP 1X/2X
I/O can operate from either a 3.3V or a 1.5V supply. AGP 4X I/O requires a 1.5V supply. The AGP
interface voltage is determined by the VDDQ generation on the motherboard.

82815EP and 82815P MCH

Datasheet

2. Signal

Description

This section provides a detailed description of the MCH signals. The signals are arranged in functional
groups according to their associated interface. The states of all of the signals during reset are provided in
the System Reset section.

The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when
at the high voltage level.

The following notations are used to describe the signal type:

I Input

O Output

I/OD

Input / Open Drain Output pin. This pin requires a pullup

I/O

Bi-directional Input/Output pin

s/t/s

Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.

As/t/s

Active Sustained Tristate. This applies to some of the hub interface signals. This pin
is weakly driven to its last driven value.

The signal description also includes the type of buffer used for the particular signal:

AGTL+

Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details

AGP

AGP interface signals. These signals can be programmed to be compatible with AGP
2.0 3.3V or 1.5V Signaling Environment DC and AC Specifications. In 3.3V mode
the buffers are not 5V tolerant. In 1.5V mode the buffers are not 3.3V tolerant.

CMOS

The CMOS buffers are low voltage TTL compatible signals. These are 3.3V only.

LVTTL

Low Voltage TTL compatible signals. There are 3.3V only.

1.8V

1.8V signals for the digital video interface

Analog

Analog CRT Signals

Note that the processor address and data bus signals (Host Interface) are logically inverted signals
(i.e., the actual values are inverted of what appears on the processor bus). This must be taken into
account and the addresses and data bus signals must be inverted inside the MCH. All processor control
signals follow normal convention. A 0 indicates an active level (low voltage) if the signal is followed by
a # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix.

82815EP and 82815P MCH

Datasheet

2.1. Host Interface Signals

Signal Name

Type

Description

CPURST# O

AGTL+

CPU Reset. The MCH asserts CPURST# while RESET# (PCIRST# from the I/O
Controller Hub) is asserted and for approximately 1 ms after RESET# is deasserted.
The MCH also pulses CPURST# for approximately 1 ms when requested via a hub
interface special cycle. The CPURST# allows the processor to begin execution in a
known state.

HA[31:3]# I/O

AGTL+

Host Address Bus. HA[31:3]# connect to the processor address bus. During
processor cycles, HA[31:3]# are inputs. The MCH drives HA[31:3]# during snoop
cycles on behalf of Primary PCI. Note that the address bus is inverted on the
processor bus.

HD[63:0]# I/O

AGTL+

Host Data. These signals are connected to the processor data bus. Note that the
data signals are inverted on the processor bus.

ADS# I/O

AGTL+

Address Strobe. The processor bus owner asserts ADS# to indicate the first of two
cycles of a request phase.

BNR# I/O

AGTL+

Block Next Request. Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the processor bus pipeline
depth.

BPRI# O

AGTL+

Priority Agent Bus Request. The MCH is the only priority agent on the processor
bus. It asserts this signal to obtain the ownership of the address bus. This signal
has priority over symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the HLOCK# signal was asserted.

DBSY# I/O

AGTL+

Data Bus Busy. Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.

DEFER# O

AGTL+

Defer. The MCH will generate a deferred response as defined by the rules of the
MCH dynamic defer policy. The MCH will also use the DEFER# signal to indicate a
processor retry response.

DRDY# I/O

AGTL+

Data Ready. Asserted for each cycle that data is transferred.

HIT# I/O

AGTL+

Hit. Indicates that a caching agent holds an unmodified version of the requested
line. Also driven in conjunction with HITM# by the target to extend the snoop
window.

HITM# I/O

AGTL+

Hit Modified. Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
HITM# is also driven in conjunction with HIT# to extend the snoop window.

HLOCK# I

AGTL+

Host Lock. All processor bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface or MCH
graphics snoopable access to SDRAM is allowed when HLOCK# is asserted by the
processor).

HREQ[4:0]# I/O

AGTL+

Host Request Command. Asserted during both clocks of request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals carry additional information
to define the complete transaction type.

The transactions supported by the MCH are defined in the Host Interface section of
this document.

HTRDY# I/O

AGTL+

Host Target Ready. Indicates that the target of the processor transaction is able to
enter the data transfer phase.

82815EP and 82815P MCH

Datasheet

Signal Name

Type

Description

RS[2:0]# I/O

AGTL+

Response Signals. Indicates type of response as shown below:

000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by the MCH)
100 = Hard Failure (not driven by the MCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response

GTLREF[1:0] I GTL Reference. Reference voltage input for the Host GTL interface. GTLREF is

2/3 * VTT. VTT is nominally 1.5V.

2.2. System Memory Interface Signals

Signal Name

Type

Description

SMAA[12:0]
SMAB[7:4]#
SMAC[7:4]#

SBS[1:0]

CMOS

Memory Address. SMAA[12:0], SMAB[7:4]#, and SMAC[7:4]# are used to provide
the multiplexed row and column address to SDRAM. SBS[1:0] provide the Bank
Select.

SBS[1:0] O

CMOS

Memory Bank Select. These signals define the banks that are selected within
each DRAM row. The SMAx and SBS signals combine to address every possible
location within a DRAM device.

SBS[1:0] may be heavily loaded and require 2 SDRAM clock cycles for setup time
to the SDRAMs. For this reason, all chip select signals (SCSA[5:0]# and
SCSB[5:0]#) must be deasserted on any SDRAM clock cycle that one of these
signals change.

SMD[63:0] I/O

CMOS

Memory Data. These signals are used to interface to the SDRAM data bus.

SDQM[7:0] O

CMOS

Input/Output Data Mask. These pins act as synchronized output enables during
read cycles and as a byte enables during write cycles.

SCSA[5:0]#
SCSB[5:0]#

CMOS

Chip Select. For the memory row configured with SDRAM, these pins perform the
function of selecting the particular SDRAM components during the active state.

SRAS# O

CMOS

SDRAM Row Address Strobe. These signals drive the SDRAM array directly
without any external buffers.

SCAS# O

CMOS

SDRAM Column Address Strobe. These signals drive the SDRAM array directly
without any external buffers.

SWE# O

CMOS

Write Enable Signal. SWE# is asserted during writes to SDRAM.

SCKE[5:0] O

CMOS

System Memory Clock Enable. SCKE SDRAM Clock Enable is used to signal a
self-refresh or power-down command to an SDRAM array when entering system
suspend.

SRCOMP O

System Memory RCOMP. Used to calibrate the System memory I/O buffers. This
pin should be connected to a 40 ohm resistor tied to 3.3V VCC (VSUS3.3).

82815EP and 82815P MCH

Datasheet

2.3. AGP Interface Signals

For more details on the operation of these signals, refer to the AGP Interface Specification Revision 2.0.
82815EP AGP inteface signals function as documented in this section.

2.3.1.

AGP Addressing Signals

There are two mechanisms that the AGP master can enqueue AGP requests: PIPE# and SBA (side-band
addressing). Upon initialization, one of the methods is chosen. The master may not switch methods
without a full reset of the system. When

PIPE#

is used to enqueue addresses, the master is not allowed to

queue addresses using the SBA bus. For example, during configuration time, if the master indicates that
it can use either mechanism, the configuration software will indicate which mechanism the master will
use. Once this choice has been made, the master will continue to use the mechanism selected until the
system is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic
mechanism but rather a static decision when the device is first being configured after reset.

Signal Name

Type

Description

PIPE# I

AGP

Pipeline.

During PIPE# Operation. This signal is asserted by the AGP master to indicate a
full-width address is to be enqueued on by the target using the AD bus. One
address is placed in the AGP request queue on each rising clock edge while PIPE#
is asserted.

During SBA Operation. This signal is not used if SBA (Side Band Addressing) is
selected.

During FRAME# Operation. This signal is not used during AGP FRAME#
operation.

SBA[7:0] I

AGP

Side-band Addressing.

During PIPE# Operation. These signals are not used during PIPE# operation.

During SBA Operation. These signals (the SBA, or side-band addressing, bus) are
used by the AGP master (graphics component) to place addresses into the AGP
request queue. The SBA bus and AD bus operate independently. That is,
transactions can proceed on the SBA bus and the AD bus simultaneously.

During FRAME# Operation. These signals are not used during AGP FRAME#
operation.

82815EP and 82815P MCH

Datasheet

2.3.2.

AGP Flow Control Signals

Signal Name

Type

Description

RBF# I

AGP

Read Buffer Full.

During PIPE# and SBA Operation. Read buffer full indicates if the master is ready
to accept previously requested low priority read data. When RBF# is asserted the
MCH is not allowed to initiate the return low priority read data. That is, the MCH can
finish returning the data for the request currently being serviced, however it can not
begin returning data for the next request. RBF# is only sampled at the beginning of
a cycle.

If the AGP master is always ready to accept return read data, then it is not required
to implement this signal.

During FRAME# Operation. This signal is not used during AGP FRAME#
operation.

WBF# I

AGP

Write-Buffer Full.

During PIPE# and SBA Operation. Write bufffer full indicates if the master is ready
to accept Fast Write data from the MCH. When WBF# is asserted the MCH is not
allowed to drive Fast Write data to the AGP master. WBF# is only sampled at the
beginning of a cycle.

If the AGP master is always ready to accept fast write data, then it is not required to
implement this signal.

During FRAME# Operation: This signal is not used during AGP FRAME#
operation.

2.3.3.

AGP Status Signals

Signal Name

Type

Description

ST[2:0] O

AGP

Status Bus.

During PIPE# and SBA Operation. Provides information from the arbiter to a AGP
Master on what it may do. ST[2:0] only have meaning to the master when its GNT#
is asserted. When GNT# is deasserted, these signals have no meaning and must
be ignored. Refer to the AGP Interface Specificaiton revision 2.0 for further
explanation of the ST[2:0] values and their meanings.

During FRAME# Operation. These signals are not used during FRAME# based
operation; except that a `111' indicates that the master may begin a FRAME#
transaction.

82815EP and 82815P MCH

Datasheet

2.3.4.

AGP Clocking Signals (Strobes)

Signal Name

Type

Description

AD_STB0 I/O

s/t/s

AGP

AD Bus Strobe-0.

During 2X Operation. During 2X operation, this signal provides timing for the
G_AD[15:0] and G_C/BE[1:0]# signals. The agent that is providing the data will
drive this signal.

During 4X Operation. During 4X operation, this is one-half of a differential strobe
pair that provides timing information for the G_AD[15:0] and G_C/BE[1:0]# signals.

AD_STB0# I/O

s/t/s

AGP

AD Bus Strobe-0 Compliment.

During 2X Operation. During 2X operation, this signal is not used.

During 4X Operation. During 4X operation, this is one-half of a differential strobe
pair that provides timing information for the G_AD[15:0] and G_C/BE[1:0]# signals.
The agent that is providing the data will drive this signal.

AD_STB1 I/O

s/t/s

AGP

AD Bus Strobe-1.

During 2X Operation. During 2X operation, this signal provides timing for the
G_AD[16:31] and G_C/BE[2:3]# signals. The agent that is providing the data drives
this signal.

During 4X Operation. During 4X operation, this is one-half of a differential strobe
pair that provides timing information for the G_AD[16:31] and G_C/BE[2:3]# signals.
The agent that is providing the data drives this signal.

AD_STB1# I/O

s/t/s

AGP

AD Bus Strobe-1 Compliment.

During 2X Operation. During 2X operation, this signal is not used

SB_STB I

AGP

SBA Bus Strobe.

During 2X Operation. During 2X operation, this signal provides timing for the SBA
bus signals. The agent that is driving the SBA bus drives this signal.

During 4X Operation. During 4X operation, this is one-half of a differential strobe
pair that provides timing information for the SBA bus signals. The agent that is
driving the SBA bus drives this signal.

SB_STB# I

AGP

SBA Bus Strobe Compliment.

During 2X Operation. During 2X operation, this signal is not used.

GRCOMP O

AGP RCOMP. Used to calibrate AGP I/O buffers. This pin should be connected to a
40 ohm pull down resistor tied to VSS.

AGPREF I

AGP Reference. Reference voltage input for the AGP interface. AGPREF should
be 0.4*VDD

AGP

when VDD is 3.3V, or 0.5* VDD

AGP

when VDD is 1.5V.

82815EP and 82815P MCH

Datasheet

2.3.5.

AGP FRAME# Signals

Signal Name

Type

Description

G_FRAME# I/O

s/t/s

AGP

FRAME.

During PIPE# and SBA Operation. Not used by AGP SBA and PIPE#, but used
during AGP FRAME# .

During Fast Write Operation. G_FRAME# is used to frame transactions as an
output from the MCH during Fast Writes.

During FRAME# Operation. G_FRAME# is an output when the MCH acts as an
initiator on the AGP Interface. G_FRAME# is asserted by the MCH to indicate the
beginning and duration of an access. G_FRAME# is an input when the MCH acts as
a FRAME# based AGP target. As a FRAME# based AGP target, the MCH latches
the G-C/BE[3:0]# and the G_AD[31:0] signals on the first clock edge on which it
samples G_FRAME# active.

G_IRDY# I/O

s/t/s

AGP

Initiator Ready.

During PIPE# and SBA Operation. Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.

During FRAME# Operation. G_IRDY# is an output when MCH acts as a FRAME#
based AGP initiator and an input when the MCH acts as a FRAME# based AGP
target. The assertion of G_IRDY# indicates the current FRAME# based AGP bus
initiator's ability to complete the current data phase of the transaction.

During Fast Write Operation. G_IRDY# indicates the AGP compliant master is
ready to provide all write data for the current transaction. Once G_IRDY# is
asserted for a write operation, the master is not allowed to insert wait states. The
master is never allowed to insert a wait state during the initial data transfer (32
bytes) of a write transaction. However, it may insert wait states after each 32 byte
block is transferred.

G_TRDY# I/O

s/t/s

AGP

Target Ready.

During PIPE# and SBA Operation. Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.

During FRAME# Operation. G_TRDY# is an input when the MCH acts as an AGP
initiator and an output when the MCH acts as a FRAME# based AGP target. The
assertion of G_TRDY# indicates the target's ability to complete the current data
phase of the transaction.

During Fast Write Operation. G_TRDY# indicates the AGP compliant target is
ready to receive write data for the entire transaction (when the transfer size is less
than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32
bytes) of data when the transfer size is greater than 32 bytes. The target is allowed
to insert wait states after each block (32 bytes) is transferred on write transactions.

G_STOP# I/O

s/t/s

AGP

Stop.

During PIPE# and SBA Operation. This signal is not used during PIPE# or SBA
operation.

During FRAME# Operation. STOP# is an input when the MCH acts as a FRAME#
based AGP initiator and an output when the MCH acts as a FRAME# based AGP
target. STOP# is used for disconnect, retry, and abort sequences on the AGP
interface.

82815EP and 82815P MCH

Datasheet

Signal Name

Type

Description

G_DEVSEL# I/O

s/t/s

AGP

Device Select.

During PIPE# and SBA Operation. This signal is not used during PIPE# or SBA
operation.

During FRAME# Operation. G_DEVSEL#, when asserted, indicates that a
FRAME# based AGP target device has decoded its address as the target of the
current access. The MCH asserts G_DEVSEL# based on the SDRAM address
range being accessed by a PCI initiator. As an input it indicates whether any device
on the bus has been selected.

G_REQ# I

AGP

Request.

During SBA Operation. This signal is not used during SBA operation.

During PIPE# and FRAME# Operation. G_REQ#, when asserted, indicates that a
FRAME# or PIPE# based AGP master is requesting use of the AGP interface. This
signal is an input into the MCH.

G_GNT# O

AGP

Grant.

During SBA, PIPE# and FRAME# Operation. G_GNT# along with the information
on the ST[2:0] signals (status bus) indicates how the AGP interface will be used
next. Refer to the AGP Interface Specificaiton revision 2.0 for further explanation of
the ST[2:0] values and their meanings.

G_AD[31:0] I/O

AGP

Address/Data Bus.

During PIPE# and FRAME# Operation. G_AD[31:0] are used to transfer both
address and data information on the AGP inteface.

During SBA Operation. G_AD[31:0] are used to transfer data on the AGP
interface.

G_C/BE[3:0]# I/O

AGP

Command/Byte Enable.

During FRAME# Operation. During the address phase of a transaction,
G_C/BE[3:0]# define the bus command. During the data phase G_C/BE[3:0]# are
used as byte enables. The byte enables determine which byte lanes carry
meaningful data. The commands issued on the G_C/BE# signals during FRAME#
based AGP are the same G_C/BE# command described in the PCI 2.1 and 2.2
specifications.

During PIPE# Operation. When an address is enqueued using PIPE#, the C/BE#
signals carry command information. Refer to the AGP 2.0 Interface Specification
Revision 2.0 for the definition of these commands. The command encoding used
during PIPE# based AGP is Different than the command encoding used during
FRAME# based AGP cycles (or standard PCI cycles on a PCI bus).

During SBA Operation. These signals are not used during SBA operation.

G_PAR I/O

AGP

Parity.
During FRAME# Operation. G_PAR is driven by the MCH when it acts as a
FRAME# based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. G_PAR is driven by the MCH when it
acts as a FRAME# based AGP target during each data phase of a FRAME# based
AGP memory read cycle. Even parity is generated across G_AD[31:0] and
G_C/BE[3:0]#.

During SBA and PIPE# Operation. This signal is not used during SBA and PIPE#
operation.

NOTES:

1. LOCK#, SERR#, and PERR# signals are not supported on the AGP Interface (even for PCI operations).
2. PCI signals described in this table behave according to PCI 2.1 specifications when used to perform PCI

transactions on the AGP interface.

82815EP and 82815P MCH

Datasheet

2.5 Power

Signals

Signal Name

Type

Description

V1.8

Power

Core Power (1.85V)

VDDQ

Power

AGP I/O Supply Power

VSUS3.3

Power

System Memory Buffer Power (Separate 3.3V power plane for power down modes)

VCCDA

Power

Display Power Signal (Connect to an isolated 1.85V plane with VCCDACA1 and
VCCDACA2.) Note that VCCDA, VCCDACA1, and VCCDACA2 provide display
power. However, in an 815EP platform these circuits are not functional. DAC power
is disabled via BIOS software.

VCCDACA1

Power

Display Power Signal (See description for VCCDA.)

VCCBA

Power

AGP/Hub I/F Power (1.85V)

VCCDACA2

Power

Display Power Signal (See description for VCCDA)

VCCDPLL

Power

System Memory PLL Power (1.85V)

VSS Power

Core

Ground

VSSDPLL

Power

System Memory PLL Ground

VSSBA

Power

AGP/Hub I/F Ground

2.5. Clock Signals

Signal Name

Type

Description

HCLK I

CMOS

Host Clock Input. Clock used on the host interface. Externally generated
66/100/133 MHz clock.

SCLK I

CMOS

System Memory Clock. Clock used on the output buffers of system memory.
Externally generated 100/133 MHz clock.

HLCLK I

CMOS

Hub Interface Clock. 66 MHz hub interface clock generated by an external clock
synthesizer.

RESET# I

Global Reset. Driven by the I/O Controller Hub when PCIRST# is active.

2.6. MCH Power-Up/Reset Strap Options

Pin Name

Strap Description

Configuration

Interface

Type

Buffer Type

SBA[7]

Local Memory Frequency
Select

High = 133 MHz (default)
Low = 100MHz

AGP/LM Input

SCAS#

Host Frequency

High = 133 MHz (default)
Low = 100 or 66 MHz

System

Memory

Bi-directional

SWE#

Host Frequency

High = 100 MHz (default)
Low = 66 MHz

System

Memory

Bi-directional

SMAA[11]

IOQ Depth

High = 4 (default)
Low = 1

System

Memory

Bi-directional

SMAA[10]

ALL Z

High = Normal (default)

Low = All Z

System

Memory

Bi-directional

82815EP and 82815P MCH

Datasheet

3. Configuration

Registers

This chapter describes the following register sets:

PCI Configuration Registers. The MCH contains PCI configuration registers for Device 0 (Host-
hub interface Bridge/DRAM Controller) and Device 1 (AGP Bridge).

3.1. Register Nomenclature and Access Attributes

Mnemonic Description

Read-Only. If a register is read-only, writes to this register have no effect.

R/W

Read/Write. A register with this attribute can be read and written

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

R/WO

Read/Write-Once. A register bit with this attribute can be written to only once after power up.
After the first write, the bit becomes read-only.

Reserved
Bits

Some of the MCH registers described in this section contain reserved bits. These bits are labeled
"Reserved" or "Intel Reserved". Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved
bits being any particular value. On writes, software must ensure that the values of reserved bit
positions

are preserved. That is, the values of reserved bit positions must first be read, merged

with the new values for other bit positions and then written back. Note that software does not
need to perform read, merge, write operation for the configuration address register.

Reserved
Registers

In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-hub interface Bridge/DRAM Controller and the internal graphics
device entities that are marked either "Reserved" or Intel Reserved". When a "Reserved" register
location is read, a random value can be returned. ("Reserved" registers can be 8-, 16-, or 32-bit in
size). Registers that are marked as "Reserved" must not be modified by system software. Writes
to "Reserved" registers may cause system failure.

Default
Value Upon
Reset

Upon a Full Reset, the MCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping options. The
default state represents the minimum functionality feature set required to successfully bring up
the system. Hence, it does not represent the optimal system configuration. It is the responsibility
of the system initialization software (usually BIOS) to properly determine the DRAM
configurations, operating parameters, and optional system features that are applicable, and to
program the MCH registers accordingly.

3.2. PCI Configuration Space Access

The MCH and the I/O Controller Hub are physically connected via the hub interface. From a
configuration standpoint, the hub interface connecting the MCH and the I/O Controller Hub is logically
PCI bus #0. All devices internal to the MCH and I/O Controller Hub appear to be on PCI bus #0. The
system primary PCI expansion bus is physically attached to the I/O Controller Hub and, from a
configuration standpoint, appears as a hierarchical PCI bus behind a PCI-to-PCI bridge. The primary PCI
expansion bus connected to the I/O Controller Hub has a programmable PCI Bus number.

Note: Even though the primary PCI expansion bus is referred to as PCI0 in this document it is not PCI bus #0

from a configuration standpoint.

82815EP and 82815P MCH

Datasheet

The MCH contains two PCI devices within a single physical component. The configuration registers for
Devices 0 and 1 are mapped as devices residing on PCI bus #0.

Device 0: Host-hub interface Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus #0. Physically, Device 0 contains the PCI registers, DRAM registers, and other
MCH specific registers.

Device 1: AGP Bridge supporting 1X/2X/4X transactions. Logically this appears as a PCI device
residing on PCI bus #0.

Note: A physical PCI bus #0 does not exist. The hub interface and the internal devices in the MCH and I/O

Controller Hub logically constitute PCI Bus #0 to configuration software.

3.2.1.

PCI Bus Configuration Mechanism

The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported
by a mapping mechanism implemented within the MCH. The PCI specification defines two mechanisms
to access configuration space, Mechanism #1 and Mechanism #2.

The MCH supports only Mechanism #1

The configuration access mechanism makes use of the CONF_ADDR Register and CONF_DATA
Register. To reference a configuration register a DWord I/O write cycle is used to place a value into
CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device, and a
specific configuration register of the device function being accessed. CONF_ADDR[31] must be 1 to
enable a configuration cycle. CONF_DATA then becomes a window into the four bytes of configuration
space specified by the contents of CONF_ADDR. Any read or write to CONF_DATA results in the
MCH translating the CONF_ADDR into the appropriate configuration cycle.

The MCH is responsible for translating and routing the processor I/O accesses to the CONF_ADDR and
CONF_DATA registers to internal MCH configuration registers, the internal graphic device, or the hub
interface.

3.2.2.

Logical PCI Bus #0 Configuration Mechanism

The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONF_ADDR
register. If the Bus Number field of CONF_ADDR is 0, the configuration cycle is targeting a PCI Bus #0
device.

Device #0: The Host-hub interface Bridge/DRAM Controller entity within the MCH is hardwired as
Device #0 on PCI Bus #0.

Device #1: The AGP interface entity within the MCH is hardwired as Device #1 on PCI Bus #0.

Note: Configuration cycles to one of the MCH internal devices are confined to the MCH and not sent over the

hub interface. Note that accesses to devices #3 to #31 on PCI Bus #0 are forwarded over the hub
interface.

82815EP and 82815P MCH

Datasheet

3.2.3.

Primary PCI (PCI0) and Downstream Configuration Mechanism

If the Bus Number in the CONF_ADDR is non-zero, the MCH generates a configuration cycle over the
hub interface. The I/O Controller Hub compares the non-zero Bus Number with the Secondary Bus
Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle
is meant for Primary PCI expansion bus (PCI0), or a downstream PCI bus.

3.2.4.

MCH Register Introduction

The MCH contains two sets of software accessible registers, accessed via the Host I/O address space:

Control registers I/O mapped into the host I/O space that control access to PCI configuration space
(see section entitled I/O Mapped Registers)

Internal configuration registers residing within the MCH are partitioned into two logical device
register sets ("logical" since they reside within a single physical device). The first register set is
dedicated to Host-hub interface Bridge/DRAM Controller functionality (controls PCI bus 0 such as
DRAM configuration, other chip-set operating parameters, and optional features). The second
register block is dedicated to the AGP interface.

The MCH supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.

The MCH internal registers (both I/O Mapped and Configuration registers) are accessible by the host.
The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of
CONF_ADDR which can only be accessed as a DWord. All multi-byte numeric fields use "little-endian"
ordering (i.e., lower addresses contain the least significant parts of the field).

3.3. I/O Mapped Registers

The MCH contains two registers that reside in the processor I/O address space

the Configuration

Address (CONF_ADDR) Register and the Configuration Data (CONF_DATA) Register. The
Configuration Address Register enables/disables the configuration space and determines what portion of
configuration space is visible through the Configuration Data window.

3.3.1. CONF_ADDR

Configuration Address Register

I/O Address:

0CF8h Accessed as a DWord

Default Value:

00000000h

Access: Read/Write

Size: 32

bits

CONF_ADDR is a 32 bit register accessed only when referenced as a DWord. A Byte or Word reference
will "pass through" the Configuration Address Register onto the PCI0 bus as an I/O cycle. The
CONF_ADDR register contains the Bus Number, Device Number, Function Number, and Register
Number for which a subsequent configuration access is intended.

82815EP and 82815P MCH

Datasheet

CFGE

Reserved (0)

Bus Number

11 10

8 7

2 1

Device Number

Function Number

Reserved

Bit Descriptions

Configuration Enable (CFGE). This bit enables/disables accesses to PCI configuration space.

1 = Enabled.

0 = Disable.

30:24 Reserved. These bits are read-only and have a value of 0.

23:16

Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is one
of the two devices in the MCH or the PCI Bus (the hub interface is logically a PCI bus) that is directly
connected to the MCH, depending on the Device Number field.

A type 0 Configuration Cycle is generated on the hub interface if the Bus Number is programmed to 00h
and the MCH is not the target.

If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number
Register a Type 0 PCI configuration cycle will be generated on the AGP bridge.

If the Bus Number is non-zero, greater than the value in the Secondary Bus Number Register (Device 1)
and less than or equal to the value programmed into the Subordinate Bus Number Register (Device 1) a
Type 1 PCI configuration cycle will be generated on the AGP bridge.

If the Bus Number is non-zero, and is less than the value programmed into the Secondary Bus Number
or is greater than the value programmed into the Subordinate Bus Number Register a Type 1 hub
interface configuration cycle is generated.

15:11

Device Number. This field selects one agent on the PCI bus selected by the Bus Number. During a
Type 1 Configuration cycle, this field is mapped to AD[15:11]. During a Type 0 Configuration Cycle, this
field is decoded and one bit among AD[31:11] is driven to a 1.

The MCH is always Device Number 0 for the Host bridge (MCH) entity and Device Number 1 for the
AGP bridge entity.

If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number
Register, a Type 0 PCI configuration cycle is generated on the AGP bridge. The Device Number field is
decoded and the MCH asserts one and only one GADxx signal as an IDSEL. GAD16 is asserted to
access Device 0, GAD17 for Device 1, GAD18 for Device 2 and so forth up to Device 15 which asserts
AD31. All device numbers higher than 15 cause a type 0 configuration access with no IDSEL asserted,
which results in a Master Abort reported in the MCH's "virtual" PCI-PCI bridge registers.

For Bus Numbers resulting in hub interface configuration cycles the MCH propagates the Device
Number field as A[15:11]. For Bus Numbers resulting in AGP bridge Type 1 Configuration cycles the
Device Number is propagated as GAD[15:11].

10:8

Function Number. This field is mapped to AD[10:8] during PCIx configuration cycles. This allows the
configuration registers of a particular function in a multi-function device to be accessed. The MCH only
responds to configuration cycles with a function number of 000b; all other function number values
attempting access to the MCH (Device Number = 0 or 1, Bus Number = 0) will generate a master abort.

7:2

Register Number. This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2]
during PCI configuration cycles.

1:0 Reserved.

82815EP and 82815P MCH

Datasheet

3.4. Host-Hub Interface Bridge/DRAM Controller Device

Registers (Device 0)

Table 2 shows the MCH configuration space for device #0.

Table 2. MCH PCI Configuration Space (Device 0)

Address

Offset

Mnemonic

Register Name

Default Value

Access

0001h VID

Vendor

Identification

8086h

0203h DID

Device

Identification

1130h

0405h PCICMD

PCI

Command

0006h

R/W

0607h

PCISTS

PCI Status

0090h (AGP)

0080h (GFX)

RO, R/WC

08h

RID

Revision Identification

02h (see note)

09h

Reserved 00h

0Ah SUBC

Sub-Class

Code

00h

0Bh

BCC

Base Class Code

06h

0Ch

Reserved

00h

0Dh MLT

Master

Latency

Timer

00h

0Eh HDR

Header

Type

00h

0Fh

Reserved

1013h

APBASE

Aperture Base Configuration

00000008h (AGP)

00000000h (GFX)

R/W, RO

142Bh

Reserved

2C2Dh

SVID

Subsystem Vendor Identification

0000h

R/WO

2E2Fh SID

Subsystem

Identification

0000h R/WO

3033h

Reserved

34h CAPPTR

Capabilities

Pointer

00h

(GFX)

A0h (AGP)

354Fh

Reserved

50h MCHCFG

MCH

Configuration

40h

R/W

51h APCONT

Aperture

Control

00h R/WO/RO

52h DRP

DRAM

Row

Population

00h R/W

53h

DRAMT

DRAM Timing Register

00h

R/W

54h

DRP2

DRAM Row Population Register 2

00h

R/W

5557h

Reserved

58h

FDHC

Fixed DRAM Hole Control

00h

R/W

595Fh

PAM

Programmable Attributes Map
Registers

00h R/W

82815EP and 82815P MCH

Datasheet

Address

Offset

Mnemonic

Register Name

Default Value

Access

606Fh

Reserved

70h

SMRAM

System Management RAM Control

00h

R/W

71h

Reserved

7273h MISCC

Miscellaneous

Control

0000h R/W,RO

7487h

Reserved

888Bh CAPID

Capability

Identification

F104A009h RO

8C91h

Reserved

9293h

BUFF_SC

Buffer Strength Control

FFFFh

R/W

9495h

BUFF_SC2

Buffer Strength Control 2

FFFFh

R/W

969Fh

Reserved

A0A3h ACAPID

AGP

Capability

Identifier

00200002h

A4A7h AGPSTAT

AGP

Status

1F000207h

A8Abh AGPCMD

AGP

Command

00000000h

R/W

ACAfh

Reserved

B0B3h AGPCTRL

AGP

Control

00000000h

R/W

B4h APSIZE

Aperture

Size

00h

R/W

B5B7h

Reserved

B8BBh

ATTBASE

Aperture Translation Table Base

00000000h

R/W

BCh AMTT

AGP

Multi-Transaction

Timer

00h

R/W

BDh

LPTT

Low Priority Transaction Timer

00h

R/W

BEh

MCHCFG

MCH Configuration

0000 x000b

R/W, RO

BFCAh

Reserced

CBh ERRCMD

Error

Command

00h

R/W

CCFFh

Reserved

Note:

See Specification Update document for latest information.

82815EP and 82815P MCH

Datasheet

3.4.3.

PCICMD--PCI Command Register (Device 0)

Address Offset:

0405h

Default: 0006h

Access: Read/Write
Size: 16

bits

This register provides basic control over the PCI0 interface (hub interface) ability to respond to PCI
cycles. The PCICMD Register enables and disables the SERR# signal, parity checking (PERR# signal),
MCH's response to PCI special cycles, and enables and disables PCI0 bus master accesses to main
memory.

9 8

Reserved (0)

FB2B

(Not Impl)

SERR En

7 6 5 4 3 2 1 0

Addr/Data

Stepping

(Not Impl)

Parity

Error En

(Not Impl)

VGA Pal

(Not Impl)

Mem WR

& Inval En

(Not Impl)

Special

Cycle En

(Not Impl)

Bus

Master En

(Not Impl)

Mem Acc

(Not Impl)

I/O Acc En

(Not Impl)

Bit Descriptions

15:10 Reserved.

Fast Back-to-Back. (Not implemented). Hardwired to 0. Selects whether the MCH can generate fast
back-to-back transactions to different PCI targets.

SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR messaging. The MCH does
not have an SERR# signal. The MCH communicates the SERR# condition by sending an SERR
message to the I/O Controller Hub.

1 = Enable. MCH is enabled to generate SERR messages over the Hub interface for specific Device 0

error conditions

0 = Disable. SERR message is not generated by the MCH for Device 0.

NOTE: This bit only controls SERR messaging for Device 0. Device 1 has its own SERRE bit to

control error reporting for error conditions occurring on Device 1. The two control bits are used
in a logical OR manner to enable the SERR hub interface message mechanism.

Address/Data Stepping. (Not implemented). Hardwired to 0.

Parity Error Enable (PERRE). (Not implemented). Hardwired to 0. PERR# is not implemented by
MCH. Writes to this bit position have no affect.

VGA Palette Snoop. (Not implemented). Hardwired to 0. Writes to this bit position have no affect.

Memory Write and Invalidate Enable. The MCH will never use this command and this bit is hardwired
to 0. Writes to this bit position will have no affects.

Special Cycle Enable. (Not implemented). Hardwired to 0. The MCH ignores all special cycles
generated on the PCI.

Bus Master Enable (BME). (Not implemented). Hardwired to 1. The MCH is always allowed to be a
Bus Master. . Writes to this bit position have no affect.

Memory Access Enable (MAE). (Not implemented). Hardwired to 1. The MCH always allows access
to main memory. Writes to this bit position have no affect.

I/O Access Enable (IOAE). (Not implemented). Hardwired to 0. Writes to this bit position have no
affect.

82815EP and 82815P MCH

Datasheet

3.4.4.

PCISTS--PCI Status Register (Device 0)

Address Offset:

0607h

Default Value:

0090h

Access:

Read-Only, Read/Write Clear

Size: 16

bits

PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort
on the PCI0 bus. PCISTS also indicates the DEVSEL# timing that has been set by the MCH hardware for
target responses on the PCI0 bus. Bits [15:12] and bit 8 are read/write clear and bits [10:9] are read-only.

15 14 13 12 11

Detected
Par Error

(HW=0)

Sig Sys

Error

Recog

Mast Abort

Sta

Rec

Target

Abort Sta

Sig Target

Abort Sta

(HW=0)

DEVSEL# Timing

(HW=00)

Data Par
Detected

(HW=0)

7 6

5 4 3

FB2B

(HW=1)

Reserved Cap

List

(HW=1)

Reserved

Bit Descriptions

Detected Parity Error (DPE). This bit is hardwired to a 0. Writes to this bit position have no affect.

Signaled System Error (SSE).
1 = MCH Device 0 generates an SERR message over the hub interface for any enabled Device 0 error

condition. Device 0 error conditions are enabled in the PCICMD register. Device 0 error flags are
read/reset from the PCISTS register.

0 = Software sets SSE to 0 by writing a 1 to this bit.

Received Master Abort Status (RMAS).
1 = MCH generates a hub interface request that receives a Master Abort completion packet.
0 = Software clears this bit by writing a 1 to it.

Received Target Abort Status (RTAS).
1 = MCH generates a hub interface request that receives a Target Abort completion packet.
0 = Software clears this bit by writing a 1 to it.

Signaled Target Abort Status (STAS). (Not implemented). Hardwired to a 0. Writes to this bit
position have no affect.

10:9

DEVSEL# Timing (DEVT). These bits are hardwired to 00. Writes to these bit positions have no affect.
Device 0 does not physically connect to PCI0. These bits are set to 00 (fast decode) so that optimum
DEVSEL timing for PCI0 is not limited by the MCH.

Data Parity Detected (DPD). This bit is hardwired to a 0. Writes to this bit position have no affect.

Fast Back-to-Back (FB2B). This bit is hardwired to 1. Writes to these bit positions have no affect.
Device 0 does not physically connect to PCI. This bit is set to 1 (indicating fast back-to-back capability)
so that the optimum setting for PCI is not limited by the MCH.

6:5 Reserved.

Capability List (CLIST). This bit is hardwired to 1 to indicate that the MCH always has a capability list.
The list of capabilities is accessed via register CAPPTR at configuration address offset 34h. Register
CAPPTR contains an offset pointing to the address of the first of a linked list of capability registers.
Writes to this bit position have no affect.

3:0 Reserved.

82815EP and 82815P MCH

Datasheet

3.4.5.

RID--Revision Identification Register (Device 0)

Address Offset:

08h

Default Value:

02h (see Spec. Update document for latest information.)

Access: Read-Only
Size: 8

bits

This register contains the revision number of the Device 0. These bits are read-only and writes to this
register have no effect.

Bit Description

7:0

Revision Identification Number. This is an 8-bit value that indicates the revision identification number
for Device 0.

02h = A-2 Stepping

3.4.6.

SUBC--Sub-Class Code Register (Device 0)

Address Offset:

0Ah

Default Value:

00h

Access: Read-Only
Size: 8

bits

This register contains the Sub-Class Code for the MCH Function #0. The register is read-only.

Bit Description

7:0

Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which MCH
falls.

00h = Host Bridge.

3.4.7.

BCC--Base Class Code Register (Device 0)

Address Offset:

0Bh

Default Value:

06h

Access: Read-Only
Size: 8

bits

This register contains the Base Class Code of the MCH Function #0. This register is read-only.

Bit Description

7:0

Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH.

06h = Bridge device.

82815EP and 82815P MCH

Datasheet

3.4.8.

MLT--Master Latency Timer Register (Device 0)

Address Offset:

0Dh

Default Value:

00h

Access: Read-Only
Size: 8

bits

Device 0 is not a PCI master; therefore, this register is not implemented.

Bit Descriptions

7:0

Master Latency Timer Value. This read-only field always returns 0 when read and writes have no
affect.

3.4.9.

HDR--Header Type Register (Device 0)

Address Offset:

0Eh

Default: 00h
Access: Read-Only
Size: 8

bits

This register identifies the header layout of the configuration space. No physical register exists at this
location.

Bit Descriptions

7:0

Header Type. This read-only field always returns 0 when read and writes have no affect.

3.4.10. APBASE--Aperture Base Configuration Register

(Device 0: AGP Mode Only)

Address Offset:

103h

Default Value (AGP Mode):

00000008h

Default Value (GFX Mode):

00000000h

Access: Read/Write,

Read-Only

Size: 32

bits

The APBASE is a standard PCI Base Address register that is used to set the base of the AGP aperture.
The standard PCI Configuration mechanism defines the base address configuration register such that only
a fixed amount of space can be requested (dependent on which bits are hardwired to "0" or behave as
hardwired to "0"). To allow for flexibility (of the aperture) an additional register called APSIZE is used
as a "back-end" register to control which bits of the APBASE will behave as hardwired to "0". This
register is programmed by the MCH specific BIOS code that runs before any of the generic configuration
software is run.

Note: Bit 1 of the APCONT register is used to prevent accesses to the aperture range before this register is

initialized by the configuration software and the appropriate translation table structure has been
established in the main memory.

82815EP and 82815P MCH

Datasheet

26 25 24

Upper Prog. Base Address Bits

Lower

"HW"/Prog

Base

Address

Hardwired to 0s

2 0

Hardwired to 0s

Prefetch

able

Type Mem

Space

Indicator

Bit Description

31:26

Upper Programmable Base Address bits--R/W. These bits are used to locate the range size selected
via lower bits 25:4.

Default = 0000

Lower "Hardwired"/Programmable Base Address bit . This bit behaves as "hardwired" or as
programmable depending on the contents of the APSIZE register as defined below:

Aperture Size = 32 MB

r/w

Aperture Size = 64 MB

0 (default)

Bit 25 is controlled by the bit 3 of the APSIZE register in the following manner:

If bit APSIZE[3]=0 (indicating 64 MB aperture size), then APBASE[25]=0. If APSIZE[3]=1, then

APBASE[25]=r/w (read/write) allowing 32 MB aperture size if desired.

Default for APSIZE[3]=0b forces default APBASE[25] = 0b (bit responds as "hardwired" to 0). This

provides a default to the maximum aperture size of 64 MB. The MCH specific BIOS is responsible for
selecting smaller size (if required) before PCI configuration software runs and establishes the system
address map.

24:4

Hardwired to 0. This forces minimum aperture size selected by this register to be 32 MB.

Prefetchable--RO. This bit is hardwired to 1 to identify the Graphics Aperture range as a prefetchable
(i.e., There are no side effects on reads, the device returns all bytes on reads regardless of the byte
enables, and the MCH may merge processor writes into this range without causing errors).

2:1

Type--RO. These bits determine addressing type and they are hardwired to 00 to indicate that address
range defined by the upper bits of this register can be located anywhere in the 32-bit address space.

Memory Space Indicator--RO. Hardwired to 0 to identify aperture range as a memory range.

82815EP and 82815P MCH

Datasheet

3.4.11. SVID--Subsystem Vendor Identification Register (Device 0)

Address Offset:

2C2Dh

Default: 0000h
Access: Read/Write-Once
Size: 16

bits

Bit Description

15:0

Subsystem Vendor ID--R/WO. This value is used to identify the vendor of the subsystem. The default
value is 0000h. This field should be programmed by BIOS during boot-up. Once written, this register
becomes read-only. This Register can only be cleared by a Reset.

3.4.12. SID--Subsystem Identification Register (Device 0)

Address Offset:

2E2Fh

Default: 0000h
Access: Read/Write-Once
Size: 16

bits

Bit Description

15:0

Subsystem ID--R/WO. This value is used to identify a particular subsystem. The default value is
0000h. This field should be programmed by BIOS during boot-up. Once written, this register becomes
read-only. This Register can only be cleared by a Reset.

3.4.13. CAPPTR--Capabilities Pointer (Device 0)

Address Offset:

34h

Default Value:

88h

Access: Read-Only
Size: 8

bits

The CAPPTR provides the offset that is the pointer to the location where the capability identification
register is located.

Bit Description

7:0

Pointer to Start of CAPPTR Linked List.

88h = Points to the CAPID register that provides capability information regarding the MCH. The

capabilities are determined by which fuses are blown.

82815EP and 82815P MCH

Datasheet

3.4.14. MCHCFG--MCH Configuration Register (Device 0)

Address Offset:

50h

Default: 01ss0s00

Access: Read/Write,

Read-Only

Size: 8

bits

7 6 5 4 3 2

Mem Arb

Gnt Win

Enable

CPU

Latency

Timer

Reserved

Local

Memory

Frequency

Select

DRAM

Page

Closing

Policy

System

Memory

Frequency

Select

Reserved

Bit Description

Memory Arbiter Grant Window Enable (MAGWE). This bit controls the Host vs Low Priority Graphics
timeslice regulation in the arbiter for the System DRAM.

At pre-arbitration (aka, stage 1)

0 = Disabled. Enforce fixed priority.

1 = Limit grant to host-to-graphics stream to 6 consecutive packets.

At main-arbitration (aka, stage 2)

0 = Disabled. Enforce fixed priority.

1 = 24 clocks limiting host, 24 clocks guaranteed to low priority graphics stream.

In fixed mode arbitration (MAGWE=0) the host stream always has higher priority over the low priority
graphics stream for accesses to system memory. In timeslice mode, the host stream and the low
priority graphics stream are both regulated by a time window to provide fairness to the graphics stream.
Fixed priority mode, where the host stream is always favored, is the recommended mode of operation;
this setting gives highest system performance without adversely affecting graphics performance under
real life applications workload.

CLT (CPU Latency Timer).

0 = Deferrable processor cycle will be Deferred immediately after receiving another ADS#

1 = Deferrable processor cycle will only be Deferred after in has been held in a "Snoop Stall" for 31

clocks and another ADS# has arrived (default).

5 Reserved.

Local Memory Frequency Select (LMFS). This bit selects the operating frequency for the Local
Memory Controller. Default is set by sampling the LM_FREQ_SEL strap (AGP SBA[7] pin) at reset. It
has a weak internal pull-up enabled during reset.

This is a reserved bit in the UMA Only and No Internal Graphics SKUs. A 0 is read back in these SKUs.
The output of the register bit in these SKUs is also forced to 0 such that a customer cannot effectively
program the part for 133 MHz local memory. In the Fully-Featured and 100 MHz FSB & SM SKUs,
either 1 or 0 can be programmed by the customer.

1 = 133 MHz, (default). This is a reflection of LM_FREQ_SEL strap being pulled up (default).

0 = 100 MHz. This is a reflection of LM_FREQ_SEL strap being pulled down.

Note. The value of this bit should only be changed when the Internal Graphics device is disabled

(i.e., GMS = 00).

82815EP and 82815P MCH

Datasheet

3.4.15. APCONT--Aperture Control (Device 0)

Address Offset:

51h

Default Value:

00h

Access:

Read/Write, Write-Once, Read-Only

Size: 8

bits

The Aperture Control Register controls selection and access to aperture space.

2 1

Reserved AGP

Select

Lock

Aperture

Access

Global EN

AGP

Select

Bit Description

7:3 Reserved.

GFX AGP Select Lock--WO. This GFX AGP Select (bit 0) can be made read-only by this bit. This is
a write-once bit. After it is written, this bit can not be changed without a system reset.

0 = GFX AGP Select remains writeable.

1 = GFX AGP Select is read-only.

Aperture Access Global EnableR/W. This bit is used to prevent access to the aperture from any
port (processor, PCI0, or AGP/PCI1) before the aperture range is established by the configuration
software and appropriate translation table in the main DRAM has been initialized. It must be set after
system is fully configured for aperture accesses. Default is 0.

GFX AGP Select--R/W. This field selects the graphics device to be either AGP or Internal Graphics
(GFX).

0 = AGP Mode. AGP interface device is enabled. All registers in device 0 and device 1 are visible.

No device 2 registers are visible; reads from those addresses return 1s.

1 = GFX Mode. Internal Graphics device is enabled. All non-AGP related device 0 registers and all

device 2 registers are visible. No device 1 registers are visible; reads from those addresses
return 1s. Reads from AGP related device 0 registers return 0s. The internal graphics device
does not respond to any configuration cycles unless SMRAM[7:6] (@ 70h) are NOT 00 AND
APCONT[0] (@ 51h) is 1.

R/W, RO if GFX AGP Select Lock (bit 2 =1)

GFX AGP Select must be programmed before any other access is made to the configuration space.
The two possible modes are mutually exclusive. This bit determines whether other configuration
registers are enabled or disabled. This bit must be set as part of the initialization sequence. See
Software Start-Up Sequence section.

82815EP and 82815P MCH

Datasheet

3.4.16. DRP--DRAM Row Population Register (Device 0)

Address Offset:

52h

Default Value:

00h

Access:

Read/Write (Read-Only if D_LCK = 1)

Size: 8

bits

The MCH supports 6 physical rows of DRAM in 3 DIMMs. The width of a row is 64 bits. The DRAM
Row Population Register defines the population of each side of each DIMM. Note that this entire register
becomes read-only when the D_LCK bit is set to 1. For D_LCK bit description, see SMRAM register
(Device 0, address offset 70h).

If the system memory interface is configured to run at 133 MHz, the system BIOS must use the DRP
register (offset 52h) along with the DRP2 register (offset 52h) to detect whether the memory
configuration exceeds 2 double-sided DIMMs or 3 single-sided DIMMs. If so, the system BIOS must
down-shift the clock generator to 100 MHz to guarantee electrical integrity and timings.

DIMM 1 Population

DIMM 0 Population

Bit Description

7:4

DIMM 1 Population. This field indicates the population of DIMM 1. (See table below)

3:0

DIMM 0 Population. This field indicates the population of DIMM 0. (See table below)

Table 3. Supported System Memory DIMM Configurations

Register

Code

DIMM

Capacity

# of Devices /

DIMM

# of

Sides

DRAM

Tech.

Front Side

Population

Back Side

Population

Row Bank Column

Count Config Count Config

0 0

N/A Empty Empty

N/A

32 MB

16 Mb

8 -

2 Mb x 8

8 -

2 Mb x 8

32 MB

64 Mb

4 -

4 Mb x 16

48 MB

64/16 Mb

4 -

4 Mb x 16

8 -

2 Mb x 8

2/1

64 MB

64 Mb

4 -

4 Mb x 16

4 -

4 Mb x 16

64 MB

64 Mb

8 -

8 Mb x 8

64 MB

128 Mb

4 -

8 Mb x 16

96 MB

64 Mb

8 -

8 Mb x 8

4 -

4 Mb x 16

9/8

96 MB

128/64 Mb

4 -

8 Mb x 16

4 -

4 Mb x 16

9/8

128 MB

64 Mb

8 -

8 Mb x 8

8 -

8 Mb x 8

128 MB

128 Mb

4 -

8 Mb x 16

4 -

8 Mb x 16

128 MB

128 Mb

8 -

16 Mb x 8

128 MB

256 Mb

4 -

16 Mb x 16

192 MB

128 Mb

8 -

16 Mb x 8

4 -

8 Mb x 16

10/9

192 MB

128/64 Mb

8 -

16 Mb x 8

8 -

8 Mb x 8

10/9

256 MB

128 Mb

8 -

16 Mb x 8

8 -

16 Mb x 8

256 MB

256 Mb

4 -

16 Mb x 16

4 -

16 Mb x 16

256 MB

256 Mb

8 -

32 Mb x 8

512 MB

256 Mb

8 -

32 Mb x 8

8 -

32 Mb x 8

82815EP and 82815P MCH

Datasheet

3.4.17. DRAMT--DRAM Timing Register (Device 0)

Address Offset:

53h

Default Value:

00h

Access: Read/Write
Size: 8

bits

This register controls the operating mode and the timing of the DRAM Controller.

4 3 2 1 0

SDRAM Mode Select

DRAM

Cycle Time

Host

Aperture

Cycle

Queue Slot

CAS#

Latency

SDRAM

RAS# to

CAS# Dly

SDRAM

RAS#

Precharge

Bit Description

7:5

SDRAM Mode Select (SMS). These bits select the operational mode of the MCH DRAM interface. The
special modes are intended for initialization at power up.

000 = DRAM in Self-Refresh Mode, Refresh Disabled (Default)

001 = Normal Operation, 100 MHz System memory Refresh interval 15.6 uSec

133 MHz System memory Refresh interval 11.7 uSec

010 = Normal Operation, 100 MHz System memory Refresh interval 7.8

133 MHz System memory Refresh interval 5.85 uSec

011 = Normal Operation, 100 MHz System memory Refresh interval 1.28 uSec

133 MHz System memory Refresh interval 0.96 uSec

100 = NOP Command Enable. In this mode all processor cycles to SDRAM result in a NOP

Command on the SDRAM interface.

101 = All Banks Precharge Enable. In this mode all processor cycles to SDRAM result in an All

Banks Precharge Command on the SDRAM interface.

110 = Mode Register Set Enable. In this mode all processor cycles to SDRAM result in a mode

register set command on the SDRAM interface. The Command is driven on the MA[12:0] lines.
MA[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be driven to 1 for
interleave wrap type. MA4 needs to be driven to the value programmed in the CAS# Latency bit.
MA[6:5] should always be driven to 01. MA[12:7] must be driven to 00000. BIOS must calculate
and drive the correct host address for each row of memory such that the correct command is
driven on the MA[12:0] lines.

Note that MAB[7:4]# are inverted from MAA[7:4]; BIOS must account for this.

111 = CBR Enable. In this mode all processor cycles to SDRAM result in a CBR cycle on the SDRAM

interface.

DRAM Cycle Time (DCT). This bit controls the number of SCLKs for an access cycle.

0 = Tras = 5 SCLKs and Trc = 7 SCLKs (Default)

1 = Tras = 7 SCLKs and Trc = 9 SCLKs.

Host Aperture Cycle Queue Slot

0 = Default value. No dedicated queue slot is reserved for host to aperture cycles.

1 = A dedicated queue slot is reserved for host to aperture cycles.

The BIOS should set this bit to `1'.

82815EP and 82815P MCH

Datasheet

Bit Description

CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled
by the SDRAMs and when MCH samples read data from the SDRAMs.

0 = CAS# latency is 3 SCLKs.

1 = CAS# latency is 2 SCLKs.

SDRAM RAS# to CAS# Delay (SRCD). This bit controls the number of SCLKs from a Row Activate
command to a read or write command.

0 = 3 clocks are inserted between a row activate command and either a read or write command.

1 = 2 clocks are inserted between a row activate and either a read or write command.

SDRAM RAS# Precharge (SRP). This bit controls the number of SCLKs for RAS# precharge.

0 = 3 clocks of RAS# precharge are provided.

1 = 2 clocks of RAS# precharge are provided

3.4.18. DRP2--DRAM Row Population Register 2 (Device 0)

Address Offset:

54h

Default Value:

00h

Access:

Read/Write (Read-Only if D_LCK = 1)

Size: 8

bits

This register extends support to 6 physical rows of DRAM in 3 DIMMs. The width of a row is 64 bits.
This second DRAM Row Population Register (DRP2) defines the population of each side of DIMM 2.
Note that this entire register becomes read-only when the D_LCK bit is set. For D_LCK bit description,
see SMRAM register (Device 0, address offset 70h).

Reserved DIMM

Population

Bit Description

7:4 Reserved.

3:0

DIMM 2 Population. This field indicates the population of DIMM 2. Refer to the Supported System
Memory DIMM Configurations table located with the DRP register definition. Note that some of the
larger capacity DIMMs may not be supported in DIMM 2 based on the capacities of DIMM 0 and
DIMM 1. The maximum supported main memory capacity is 512 MB.

82815EP and 82815P MCH

Datasheet

3.4.19. FDHC--Fixed DRAM Hole Control Register (Device 0)

Address Offset:

58h

Default Value:

00h

Access: Read/Write
Size: 8

bits

This 8-bit register controls a single fixed DRAM hole: 15 MB16 MB.

7 6

Hole EN

Reserved

Bit Description

Hole Enable (HEN). This field enables a memory hole in DRAM space. Host cycles matching an
enabled hole are passed on to the I/O Controller Hub through the hub interface. Hub interface and PCI
cycles matching an enabled hole are ignored by the MCH. Note that a selected hole is not re-mapped.

0 = No Hole Enabled

1 = 15 MB16 MB (1MB) Hole Enabled

6:0 Reserved.

3.4.20. PAM--Programmable Attributes Map Registers (Device 0)

Address Offset:

595Fh

Default Value:

00h

Attribute: Read/Write
Size: 4

bits/register

The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in
the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to
support these features. Cacheability of these areas is controlled via the MTRR registers in the P6
processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to
both host, AGP/PCI, and hub interface initiator accesses to the PAM areas. These attributes are:

Read Enable (RE). When RE = 1, the processor read accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to the hub interface/PCI0.

Write Enable (WE). When WE = 1, the host write accesses to the corresponding memory segment
are claimed by the MCH and directed to main memory. Conversely, when WE = 0, the host write
accesses are directed to the hub interface/PCI0.

The RE and WE attributes permit a memory segment to be Read-Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read-Only.

Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field.
The four bits that control each region have the same encoding and are defined in the following table.

82815EP and 82815P MCH

Datasheet

Table 4. Attribute Bit Assignments

Bits [7, 3]

Reserved

Bits [6, 2]

Reserved

Bits [5, 1]

Bits [4, 0]

Description

X X 0 0

Disabled. DRAM is disabled and all accesses
are directed to the hub interface. The MCH
does not respond as a AGP/PCI or hub
interface target for any read or write access to
this area.

X X 0 1

Read-Only. Reads are forwarded to DRAM
and writes are forwarded to the hub interface
for termination. This write protects the
corresponding memory segment. The MCH
responds as a AGP/PCI or hub interface
target for read accesses but not for any write
accesses.

X X 1 0

Write Only. Writes are forwarded to DRAM
and reads are forwarded to the hub interface
for termination. The MCH responds as a
AGP/PCI or hub interface target for write
accesses but not for any read accesses.

X X 1 1

Read/Write. This is the normal operating
mode of main memory. Both read and write
cycles from the host are claimed by the MCH
and forwarded to DRAM. The MCH responds
as a AGP/PCI or hub interface target for both
read and write accesses.

As an example, consider a BIOS that is implemented on the expansion bus. During the initialization
process, BIOS can be shadowed in main memory to increase the system performance. When BIOS is
shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the
attributes for that address range should be set to write only. BIOS is shadowed by first doing a read of
that address. This read is forwarded to the expansion bus. The host then does a write of the same address,
which is directed to main memory. After BIOS is shadowed, the attributes for that memory area are set to
read-only so that all writes are forwarded to the expansion bus. The table above and the figure below
show the PAM registers and the associated attribute bits.

82815EP and 82815P MCH

Datasheet

Figure 3. PAM Registers

pam

PAM6
PAM5
PAM4
PAM3
PAM2
PAM1
PAM0

Read Enable (R/W
1=Enable
0=Disable

Write Enable (R/W)
1=Enable
0=Disable

Reserved

Read Enable (R/W)
1=Enable
0=Disable

Write Enable (R/W)
1=Enable
0=Disable

Reserved

5Fh
5Eh
5Dh
5Ch
5Bh
5Ah
59h

Offset

Table 5. PAM Registers and Associated Memory Segments

PAM Reg

Attribute Bits

Memory Segment

Comments

Offset

PAM0[3:0] Reserved

59h

PAM0[7:4] R

0F0000h0FFFFFh BIOS

Area

59h

PAM1[3:0]

0C0000h0C3FFFh

ISA Add-on BIOS

5Ah

PAM1[7:4] R

0C4000h0C7FFFh ISA

Add-on

BIOS

5Ah

PAM2[3:0]

0C8000h0CBFFFh

ISA Add-on BIOS

5Bh

PAM2[7:4]

0CC000h 0CFFFFh

ISA Add-on BIOS

5Bh

PAM3[3:0]

0D0000h 0D3FFFh

ISA Add-on BIOS

5Ch

PAM3[7:4]

0D4000h 0D7FFFh

ISA Add-on BIOS

5Ch

PAM4[3:0]

0D8000h 0DBFFFh

ISA Add-on BIOS

5Dh

PAM4[7:4]

0DC000h 0DFFFFh

ISA Add-on BIOS

5Dh

PAM5[3:0]

0E0000h 0E3FFFh

BIOS Extension

5Eh

PAM5[7:4]

0E4000h 0E7FFFh

BIOS Extension

5Eh

PAM6[3:0]

0E8000h 0EBFFFh

BIOS Extension

5Fh

PAM6[7:4]

0EC000h 0EFFFFh

BIOS Extension

5Fh

82815EP and 82815P MCH

Datasheet

DOS Area (00000h9FFFFh)

The DOS area is 640 KB in size is always mapped to the main memory controlled by the MCH.

Video Buffer Area (A0000hBFFFFh)

The 128 KB graphics adapter memory region is normally mapped to a legacy video device on the hub
interface/PCI (typically VGA controller). This area is not controlled by attribute bits and processor
initiated cycles in this region are forwarded to either the hub interface or the AGP/Internal Graphics
Device for termination. This region is also the default region for SMM space.

Accesses to this range are directed to either the hub interface or the AGP/internal Graphics Device based
on the configuration. The configuration is specified by:

1. AGP on/off configuration bit
2. AGP off: GMS bits of the SMRAM register in the MCH Device 0 configuration space. There is

additional steering information coming from the Device 2* configuration registers and from some
of the VGA registers in the Graphics device.

3. AGP on: MCHCFG (Device 0, bit 5, PCI-PCI Command) and BCTRL (Device 1, bit 3, PCI-PCI

Bridge Control) configuration registers

Control is applied for accesses initiated from any of the system interfaces; that is, processor bus, the hub
interface, or AGP (if enabled). Note that for the hub interface to AGP/PCI accesses, only memory write
operations are supported. Any AGP/PCI initiated VGA accesses targeting the MCH will master abort.
For more details, see the descriptions in the configuration registers specified above.

The SMRAM Control register controls how SMM accesses to this space are treated.

Monochrome Adapter (MDA) Range (B0000hB7FFFh)

Legacy support requires the ability to have a second graphics controller (monochrome) in the system.

In an AGP system, accesses in the standard VGA range are forwarded to the AGP bus (depending on
configuration bits). Since the monochrome adapter may be on the hub interface/PCI (or ISA) bus, the
MCH must decode cycles in the MDA range and forward them to the hub interface. This capability is
controlled by a configuration bit (MDA bit Device 0, BEh). In addition to the memory range B0000h
to B7FFFh, the MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh and forwards
them to the hub interface.

In an internal graphics system, the GMS bits of the SMRAM register in Device 0, bits in the Device 2
PCICMD register, and bits from some of the VGA registers control this functionality.

82815EP and 82815P MCH

Datasheet

Expansion Area (C0000hDFFFFh)

This 128 KB ISA Expansion region is divided into eight 16 KB segments. Each segment can be assigned
one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are
mapped through MCH and are subtractively decoded to ISA space. Memory that is disabled is not
remapped.

Extended System BIOS Area (E0000hEFFFFh)

This 64 KB area is divided into four 16 KB segments. Each segment can be assigned independent read
and write attributes so it can be mapped either to main DRAM or to the hub interface. Typically, this area
is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere.

System BIOS Area (F0000hFFFFFh)

This area is a single 64 KB segment. This segment can be assigned read and write attributes. It is by
default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating
the read/write attributes, the MCH can "shadow" BIOS into the main DRAM. When disabled, this
segment is not remapped.

82815EP and 82815P MCH

Datasheet

3.4.21. SMRAM--System Management RAM Control Register

(Device 0)

Address Offset:

70h

Default Value:

00h

Access: Read/Write,

Read-Only

Size: 8

bits

The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated,
and how much (if any) memory is "Stolen" from the system to support both SMRAM and graphics local
memory needs.

7 6

5 4

3 2

Graphics Mode Select

Upper SMM Select

Lower SMM Select

SMM

Space

Locked

E_SMRA

M_ERR

Bit Description

7:6

Graphics Mode Select (GMS). This field is used to enable/disable the Internal Graphics device and
select the amount of main memory that is "Stolen" to support the internal graphics device in VGA (non-
linear) mode only. These 2 bits only have meaning if we are not in AGP mode.
00 = Internal graphics device Disabled, No memory "Stolen"
01 = Internal graphics device Enabled, No memory "Stolen"
10 = Internal graphics device Enabled, 512 KB of memory "Stolen" for frame buffer.

11 = Internal graphics device Enabled, 1 MB of memory "Stolen" for frame buffer.

Notes:

When the internal graphics device is disabled (00), the graphics device and all of its memory and I/O

functions are disabled and the clocks to this logic are turned off; memory accesses to the VGA range
(A0000BFFFF) are forwarded on to the hub interface and the graphics local memory space is NOT
"stolen" from main memory. Any change to the SMRAM register will not affect AGP mode or cause
the controller to go into AGP mode. When this field is non-zero, the internal graphics device and all of
its memory and I/O functions are enabled; all non-SMM memory accesses to the VGA range will be
handled internally and the selected amount of graphics local memory space (0, 512 KB or 1 MB) is
"stolen" from the main memory. Graphics memory is "stolen" AFTER TSEG memory is "stolen".

Once D_LCK is set, these bits becomes read-only.

MCH does not support VGA on local memory. Software must not use the 01 mode for VGA.

82815EP and 82815P MCH

Datasheet

Bit Description

5:4

Upper SMM Select (USMM). This field is used to enable/disable the various SMM memory ranges
above 1 MB. TSEG is a block of memory ("Stolen" from Main Memory at [TOM-Size] : [TOM]) that is
only accessable by the processor and only while operating in SMM mode. HSEG is a remap of the AB
segment at FEEA0000 : FEEBFFFF. Both of these areas, when enabled, are usable as SMM RAM.

00 = TSEG and HSEG are both disabled
01 = TSEG is disabled, HSEG is conditionally enabled
10 = TSEG is enabled as 512 KB and HSEG is conditionally enabled
11 = TSEG is enabled as 1 MB and HSEG is conditionally enabled

Note:

Non-SMM Operations (SMM processor accesses and all other access) that use these address ranges

are forwarded to the hub interface.

Once D_LCK is set, these bits becomes read-only.

HSEG is ONLY enabled if LSMM = 00.

3:2

Lower SMM Select (LSMM). This field controls the definition of the AB segment SMM space.

00 = AB segment disabled (no one can write to it).

01 = AB segment enabled as general system RAM (anyone can write to it).
10 = AB segment enabled as SMM Code RAM shadow. Only SMM code reads can access DRAM in the

AB segment (processor code reads only). SMM Data operations and all Non-SMM Operations go
to either the internal graphics device or are broadcast on the hub interface.

11 = AB segment enabled as SMM RAM. All SMM operations to the AB segment are serviced by

DRAM, all Non-SMM operations go to either the internal graphics device or are broadcast on the
hub interface (processor SMM R/W can access SMM space).

When D_LCK is set, bit 3 becomes read-only, and bit 2 is writable ONLY if bit 3 is a 1. When bit 3 is set,
only the processor can access it.

SMM Space Locked (D_LCK). When D_LCK is set to 1 then D_LCK, GMS, USMM, and the most
significant bit of LSMM become read-only. D_LCK can be set to 1 via a normal configuration space write
but can only be cleared by a reset. The combination of D_LCK and LSMM provide convenience with
security. The BIOS can use LSMM=01 to initialize SMM space and then use D_LCK to "lock down"
SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM
space, even if the program has knowledge of the LSMM function. This bit also Locks the DRP and
DRP2 registers.

E_SMRAM_ERR (E_SMERR).

1 = This bit is set when processor accesses the defined memory ranges in Extended SMRAM (HSEG or

TSEG) while not in SMM mode. This bit is Not set for the case of an explicit write-back operation.

0 = It is software's responsibility to clear this bit. Software must write a 1 to this bit to clear it.

82815EP and 82815P MCH

Datasheet

3.4.22. MISCC--Miscellaneous Control Register (Device 0)

Address Offset:

7273h

Default Value:

0000h

Access: Read/Write,

Read-Only

Size: 16

bits

This register holds all of the miscellaneous control bits for the MCH .

15 14

12 11 10

SM GFX

133

Enable

Reserved CPC

Mask Reserved

3 2 1 0

Read PWR Throttle Cntl

Write PWR Throttle Cntl

Throttle

Lock

Reserved BNR

Looka

head

GFX LM

Win Size

Sel

Bit Description

System Memory Graphics PC133 Enable--R/W. This bit allows the MCH to operate in Graphics
Mode with Enhanced System Memory (PC133). Normally, SM frequency is locked to 100 MHz in
Internal Graphics mode, and MCHCFG[2] (SMFS) is read-only. Setting this bit allows the SM frequency
to be changed by writing to MCHCFG[2]. This bit has no effect in AGP mode.

0 = Normal Operation. MCHCFG[2] hardwired to 0 when MCH is in Graphics Mode

(i.e., APCONT[0] = 1)

1 = Allow 133 MHz System Memory when the MCH is in Graphics Mode. Note that this just enables

PC133. To actually run graphics with 133 MHz SM, MCHCFG[2] must be set to 1. Also, this bit
should be set by BIOS before MCH is changed from AGP to Graphics mode via APCONT[0].

14 Reserved.

SM Transmit Stage Bypass--R/W.

0 = Normal Operation (Default). Bypass if SM=100 MHz; No bypass if SM=133 MHz.

1 = Always bypass, regardless of SM frequency.

System BIOS should set this bit to 1 to enable the bypass and optimize system memory latency by one
clock for 133 MHz operation (has no affect on 100 MHz operation).

12 Reserved.

CPC Mask Enable--R/W.

0 = Normal Operation (default).

1 = Never perform command per clock accesses to system memory. Mask command per clock.

Note: This bit must be set to 1 if using 133 MHz system memory.

10:8 Reserved.

82815EP and 82815P MCH

Datasheet

Bit Description

7:6

Read Power Throttle Control--R/W. These bits select the Power Throttle Bandwidth Limits for read
operations to system memory.

R/W, RO if Throttle Lock (bit 3 =1). These bits are locked (read-only) when bit 3 (Throttle Lock) is 1.

00 = No Limit

(800 MB/Sec) (Default)

01 = Limit at 87 ½ %

(700 MB/Sec)

10 = Limit at 75 %

(600 MB/Sec)

11 = Limit at 62 ½ %

(500 MB/Sec)

5:4

Write Power Throttle Control--R/W. These bits select the Power Throttle Bandwidth Limits for Write
operations to System Memory.

R/W, RO if Throttle Lock (bit 3 =1). These bits are locked (read-only) when bit 3 (Throttle Lock) is 1.

00 = No Limit

(800 MB/Sec) (Default)

01 = Limit at 62 ½ % ( 500 MB/Sec)

10 = Limit at 50 %

( 400 MB/Sec)

11 = Limit at 37 ½ % ( 300 MB/Sec)

Note: These bits must be set to `01' if using 100 MHz system memory and `10' if using 133 MHz

system memory.

Throttle Lock--R/W.

R/W, RO if Throttle Lock (bit 3 =1). Once set, this bit can only be cleared by a reset.

0 = Bits [7:3] remain writeable

1 = Block writes to bits [7:3]

2 Reserved--RO.

BNR Lookahead--R/W. This enables the HT unit to look further up the data path to optimize the BNR
(Block New Requests) signal to increase our effective IOQ (In Order Queue) depth.

0 = Normal Behavior (default)

1 = BNR Lookahead Enable

Graphics Translation Window Size Select--R/W. In GFX mode this would be the size of the GTT
(Graphics Translation Table). Not a valid bit in AGP mode.

0 = 64 MB (default)

1 = 32 MB.

82815EP and 82815P MCH

Datasheet

3.4.23. CAPID--Capability Identification (Device 0: AGP Mode Only)

Address Offset:

888Bh

Default Value:

F104 A009h

Access: Read-Only
Size: 32

bits

This register

uniquely identifies chipset capabilities as defined in the table below. Writes to this register have no

effect.

31 30 29 28

133 MHz

Capability

Display

Cache

Capability

AGP

Capability

Internal

Graphics

Capability

CAPID Version

CAPID Length

Next Capability Pointer

CAP_ID

Bit Description

133 MHz Capability--RO.

0 = Component is capable of up to 100 MHz front side bus and system memory.

1 = Component is capable of up to 133 MHz front side bus and system memory.

Display Cache Capability--RO.

0 = Only supports UMA mode (no local memory).

1 = Component is local memory (Display Cache) and UMA capable.

AGP Capability--RO.

0 = AGP mode not supported. Note that the AGP interface may still be active through the addition of

an AIMM card if bits 28 and 30 are both 1.

1 = AGP mode supported.

Internal Graphics Capability--RO.

0 = Internal graphic controller not supported.

1 = Internal graphic controller supported.

27:24

CAPID Version--RO. This field has the value 0001b to identify the first revision of the CAPID register
definition.

23:16

CAPID Length--RO. This field has the value 04h to indicate the structure length.

82815EP and 82815P MCH

Datasheet

Bit Description

15:8

Next Capability Pointer--RO. This field has two possible values based on APCONT[0] at offset 51h:

A0h when APCONT[0] = 0 (AGP Mode) meaning the next capability pointer is ACAPID.

00h when APCONT[0] = 1 (GFX Mode) meaning that this was the last capability pointer in the list.

7:0

CAP_ID--RO. This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for
vendor dependent capability pointers.

3.4.24. BUFF_SC--System Memory Buffer Strength Control Register

(Device 0)

Address Offset:

9293h

Default Value:

FFFFh

Access: Read/Write
Size: 16

bits

This register programs the system memory DRAM interface signal buffer strengths, with the exception of
the CKEs. The programming of these bits should be based on DRAM density (x8 or x16), DRAM
technology (16Mb, 64Mb, 128Mb or 256 Mb), rows populated, etc.. Note that x4 & x32 DRAMs are not
supported. Registered DIMMs and DIMMS with ECC are also not supported and BIOS upon detection
of ECC via SPD, should report to the user that ECC DIMM timings are not supported by the MCH.

In the descriptions below, the term "Row" is equivalent to one side of one DIMM. In other words, a
"single-sided" DIMM contains one populated row (always an odd numbered), and one empty row (even
numbered). A "double-sided" DIMM contains two populated rows.

All buffer strengths are based on the number of "loads" connected to each pin of a given signal group. A
"load" represents one pin of one SDRAM Device. The MCH pin is implied and not counted in the load
equations. The number of loads on a given signal for a given configuration can be determined entirely
from the width of the SDRAM devices that populate each row in the configuration. This information is
readily available for each row via the Serial Presence Detect mechanism.

Regardless of system memory interface frequency, the SMAA [11:8, 3:0], SBS [1:0] SWE#, SCAS#, and
SRAS# signal buffer strengths for all rows should be set accordingly to the DIMM loading which is
defined by bits [1:0] in the table below.

15 14 13 12 11 10

SCS[5]#

Buffer

Strength

SCS[4]#

Buffer

Strength

SCS[3]#

Buffer

Strength

SCS[2]#

Buffer

Strength

SCS[1]#

Buffer

Strength

SCS[0]#

Buffer

Strength

SMAC[7:4]# Buffer

Strength

7 6

5 4

3 2

1 0

SMAB[7:4]# Buffer

Strength

SMAA[7:4] Buffer

Strength

MD and DQM Buffer

Strengths

Control Buffer Strengths

82815EP and 82815P MCH

Datasheet

Bit Description

SCS[5]# Buffer Strength (Row 5).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

Each Row is actually selected by a pair of chip select signals (SCSA[n]# and SCSB[n]#). The number of
SCS# loads for a given row can be determined from SPD data using the following equation:

Loads = 32 / (width of SDRAM devices in row)

SCS[4]# Buffer Strength (Row 4).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

SCS[3]# Buffer Strength (Row 3).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

SCS[2]# Buffer Strength (Row 2).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

SCS[1]# Buffer Strength (Row 1).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

SCS[0]# Buffer Strength (Row 0).

0 = Reserved
1 = 1.0x 0 or 2 load or 4 loads

9:8

SMAC[7:4]# Buffer Strength (Rows 4/5).

00 = 2.7x > 8 loads
01 = 1.7x 8 loads
10 = 1.0x 0 or 4 loads
11 = 1.0x 0 or 4 loads

Separate copies of these SMA*[7:4] "Command-Per-Clock" signals are provided for each DIMM. So the
loads for each copy are determined by the number of SDRAM devices on the corresponding DIMM (4, 8,
12, or 16 loads). The number of loads for each SMA*[7:4] signal group can be determined from SPD
data using the following equation:

Loads = (64 / (SDRAM Device Width for 1

row)) + (64 / (SDRAM Device Width for 2

row))

7:6

SMAB[7:4]# Buffer Strength (Rows 2/3).

00 = 2.7x > 8 loads
01 = 1.7x 8 loads
10 = 1.0x 0 or 4 loads
11 = 1.0x 0 or 4 loads

82815EP and 82815P MCH

Datasheet

3.4.25. BUFF_SC2--System Memory Buffer Strength Control Register

2 (Device 0)

Address Offset:

9495h

Default Value:

FFFFh

Access: Read/Write
Size: 16

bits

This register programs the system memory DRAM interface CKE signal buffer strengths. See BUFF_SC
register for the remainder of the buffer strength controls.

Reserved (R/W)

5 4 3 2 1 0

Reserved (R/W)

CKE5
Buffer

Strength

CKE4
Buffer

Strength

CKE3
Buffer

Strength

CKE2
Buffer

Strength

CKE1
Buffer

Strength

CKE0
Buffer

Strength

Bit Description

15:6 Reserved.

SCKE[5] Buffer Strength (Row 5).