2
Intel
82845G/82845GL/82845GV GMCH
Datasheet
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2
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2
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Copyright 2002, Intel Corporation
Intel
82845G/82845GL/82845GV GMCH
Datasheet
3
Contents
1
Introduction
...........................................................................................................13
1.1
Terminology ...................................................................................................13
1.2
Related Documents .......................................................................................14
1.3
Intel
845G Chipset System Overview ..........................................................15
1.4
Intel 82845G GMCH Overview....................................................................17
1.4.1
Host Interface....................................................................................17
1.4.2
System Memory Interface .................................................................17
1.4.3
Hub Interface ....................................................................................17
1.4.4
Multiplexed AGP and Intel
DVO Port Interface ...............................18
1.4.5
Graphics Overview............................................................................18
1.4.6
Display Interfaces .............................................................................19
2
Signal Description
..............................................................................................21
2.1
Host Interface Signals....................................................................................23
2.2
Memory Interface ...........................................................................................25
2.2.1
DDR SDRAM Interface .....................................................................25
2.2.2
SDR SDRAM Interface .....................................................................26
2.3
Hub Interface .................................................................................................28
2.4
AGP Interface Signals....................................................................................29
2.4.1
AGP Addressing Signals...................................................................29
2.4.2
AGP Flow Control Signals ................................................................29
2.4.3
AGP Status Signals ..........................................................................30
2.4.4
AGP Strobes .....................................................................................30
2.4.5
PCI SignalsAGP Semantics............................................................31
2.4.6
PCI Pins during PCI Transactions on AGP Interface........................32
2.5
Multiplexed Intel
DVO Device Signal Interfaces ..........................................32
2.5.1
Intel
DVO Signal Name to AGP Signal Name Pin Mapping............34
2.6
Analog Display ...............................................................................................35
2.7
Clocks, Reset, and Miscellaneous Signals ....................................................36
2.8
RCOMP, VREF, VSWING Signals.................................................................36
2.9
Power and Ground Signals ............................................................................37
2.10
Functional Straps ...........................................................................................38
2.11
GMCH Sequencing Requirements.................................................................38
2.12
Reset States ..................................................................................................39
2.12.1 Full and Warm Reset States .............................................................39
3
Register Description
..........................................................................................41
3.1
Register Terminology.....................................................................................41
3.2
Platform Configuration ...................................................................................42
3.3
Routing Configuration Accesses....................................................................43
3.3.1
Standard PCI Bus Configuration Mechanism ...................................44
3.3.2
PCI Bus #0 Configuration Mechanism ..............................................44
3.3.3
Primary PCI and Downstream Configuration Mechanism.................44
3.3.4
AGP/PCI_B Bus Configuration Mechanism ......................................44
3.4
I/O Mapped Registers ....................................................................................46
3.4.1
CONFIG_ADDRESS--Configuration Address Register ...................46
3.4.2
CONFIG_DATA--Configuration Data Register ................................47
3.5
Intel
GMCH Internal Device Registers.........................................................48
4
Intel
82845G/82845GL/82845GV GMCH
Datasheet
3.5.1
DRAM Controller/Host-Hub Interface Device Registers (Device 0) .. 48
3.5.1.1
VID--Vendor Identification Register (Device 0) ................ 50
3.5.1.2
DID--Device Identification Register (Device 0)................. 50
3.5.1.3
PCICMD--PCI Command Register (Device 0) ................. 51
3.5.1.4
PCISTS--PCI Status Register (Device 0)......................... 52
3.5.1.5
RID--Revision Identification Register (Device 0).............. 53
3.5.1.6
SUBC--Sub-Class Code Register (Device 0)................... 53
3.5.1.7
BCC--Base Class Code Register (Device 0).................... 53
3.5.1.8
MLT--Master Latency Timer Register (Device 0) ............. 54
3.5.1.9
HDR--Header Type Register (Device 0) .......................... 54
3.5.1.10 APBASE--Aperture Base Configuration Register
(Device 0)............................................................................. 55
3.5.1.11 SVID--Subsystem Vendor Identification Register
(Device 0)............................................................................. 56
3.5.1.12 SID--Subsystem Identification Register (Device 0) .......... 56
3.5.1.13 CAPPTR--Capabilities Pointer Register (Device 0) ......... 56
3.5.1.14 AGPM--AGP Miscellaneous Configuration Register
(Device 0)............................................................................. 57
3.5.1.15 GC--Graphics Control Register (Device 0)....................... 58
3.5.1.16 DRB[0:3]--DRAM Row Boundary Register (Device 0) ..... 60
3.5.1.17 DRA--DRAM Row Attribute Register (Device 0) .............. 61
3.5.1.18 DRT--DRAM Timing Register (Device 0) ......................... 62
3.5.1.19 DRC--DRAM Controller Mode Register (Device 0) .......... 63
3.5.1.20 PAM[0:6]--Programmable Attribute Map Registers
(Device 0)............................................................................. 64
3.5.1.21 FDHC--Fixed SDRAM Hole Control Register (Device 0) . 67
3.5.1.22 SMRAM--System Management RAM Control Register
(Device 0)............................................................................. 67
3.5.1.23 ESMRAMC--Extended System Management RAM Control
Register (Device 0) .............................................................. 68
3.5.1.24 ACAPID--AGP Capability Identifier Register (Device 0) .. 69
3.5.1.25 AGPSTAT--AGP Status Register (Device 0) ................... 69
3.5.1.26 AGPCMD--AGP Command Register (Device 0) .............. 70
3.5.1.27 AGPCTRL--AGP Control Register (Device 0).................. 70
3.5.1.28 APSIZE--Aperture Size Register (Device 0) .................... 71
3.5.1.29 ATTBASE--Aperture Translation Table Register
Device 0).............................................................................. 71
3.5.1.30 AMTT--AGP MTT Control Register (Device 0)................. 72
3.5.1.31 LPTT--AGP Low Priority Transaction Timer Register
(Device 0)............................................................................. 72
3.5.1.32 GMCHCFG--GMCH Configuration Register (Device 0) ... 73
3.5.1.33 ERRSTS--Error Status Register (Device 0) ..................... 74
3.5.1.34 ERRCMD--Error Command Register (Device 0).............. 75
3.5.1.35 SMICMD--SMI Command Register (Device 0) ................ 76
3.5.1.36 SCICMD--SCI Command Register (Device 0) ................. 76
3.5.1.37 SKPD--Scratchpad Data Register (Device 0) .................. 76
3.5.1.38 CAPREG--Capability Identification Register (Device 0)... 77
3.5.2
Host-to-AGP Bridge Registers (Device 1)......................................... 78
3.5.2.1
VID1--Vendor Identification Register (Device 1) .............. 79
3.5.2.2
DID1--Device Identification Register (Device 1)............... 79
3.5.2.3
PCICMD1--PCI Command Register (Device 1) ............... 80
3.5.2.4
PCISTS1--PCI Status Register (Device 1)....................... 81
3.5.2.5
RID1--Revision Identification Register (Device 1)............ 82
3.5.2.6
SUBC1--Sub-Class Code Register (Device 1)................. 82
3.5.2.7
BCC1--Base Class Code Register (Device 1).................. 82
3.5.2.8
MLT1--Master Latency Timer Register (Device 1) ........... 83
Intel
82845G/82845GL/82845GV GMCH
Datasheet
5
3.5.2.9
HDR1--Header Type Register (Device 1).........................83
3.5.2.10 PBUSN1--Primary Bus Number Register (Device 1) .......83
3.5.2.11 SBUSN1--Secondary Bus Number Register (Device 1)...84
3.5.2.12 SUBUSN1--Subordinate Bus Number Register (Device 1)..
84
3.5.2.13 SMLT1--Secondary Bus Master Latency Timer Register
(Device 1).............................................................................84
3.5.2.14 IOBASE1--I/O Base Address Register (Device 1)............85
3.5.2.15 IOLIMIT1--I/O Limit Address Register (Device 1).............85
3.5.2.16 SSTS1--Secondary Status Register (Device 1) ...............86
3.5.2.17 MBASE1--Memory Base Address Register (Device 1) ....87
3.5.2.18 MLIMIT1--Memory Limit Address Register (Device 1) .....88
3.5.2.19 PMBASE1--Prefetchable Memory Base Address Register
(Device 1).............................................................................89
3.5.2.20 PMLIMIT1--Prefetchable Memory Limit Address Register
(Device 1).............................................................................89
3.5.2.21 BCTRL1--Bridge Control Register (Device 1) ..................90
3.5.2.22 ERRCMD1--Error Command Register (Device 1)............91
3.5.3
Integrated Graphics Device Registers (Device 2).............................92
3.5.3.1
VID2--Vendor Identification Register (Device 2) ..............93
3.5.3.2
DID2--Device Identification Register (Device 2)...............93
3.5.3.3
PCICMD2--PCI Command Register (Device 2) ...............94
3.5.3.4
PCISTS2--PCI Status Register (Device 2) .......................95
3.5.3.5
RID2--Revision Identification Register (Device 2) ............95
3.5.3.6
CC--Class Code Register (Device 2) ...............................96
3.5.3.7
CLS--Cache Line Size Register (Device 2) ......................96
3.5.3.8
MLT2--Master Latency Timer Register (Device 2) ...........96
3.5.3.9
HDR2--Header Type Register (Device 2).........................97
3.5.3.10 GMADR --Graphics Memory Range Address Register
(Device 2).............................................................................97
3.5.3.11 MMADR--Memory Mapped Range Address Register
(Device 2).............................................................................98
3.5.3.12 SVID2--Subsystem Vendor Identification Register
(Device 2).............................................................................98
3.5.3.13 SID2--Subsystem Identification Register (Device 2) ........98
3.5.3.14 ROMADR--Video BIOS ROM Base Address Registers
(Device 2).............................................................................99
3.5.3.15 CAPPOINT--Capabilities Pointer Register (Device 2)......99
3.5.3.16 INTRLINE--Interrupt Line Register (Device 2)..................99
3.5.3.17 INTRPIN--Interrupt Pin Register (Device 2) ...................100
3.5.3.18 MINGNT--Minimum Grant Register (Device 2) ..............100
3.5.3.19 MAXLAT--Maximum Latency Register (Device 2)..........100
3.5.3.20 PMCAPID--Power Management Capabilities ID Register
(Device 2)...........................................................................100
3.5.3.21 PMCAP--Power Management Capabilities Register
(Device 2)...........................................................................101
3.5.3.22 PMCS--Power Management Control/Status Register
(Device 2)...........................................................................101
3.5.4
Device 6 Registers..........................................................................102
3.5.4.1
DWTC--DRAM Write Throttling Control Register
(Device 6)...........................................................................102
3.5.4.2
DRTC--DRAM Read Throttling Control Register
(Device 6)...........................................................................103
4
Functional Description
...................................................................................105
4.1
Processor System Bus.................................................................................105
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