Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power
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should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 845MP/845 MZ Memory Controller Hub (MCH-M) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel. Implementations

of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

Alert on LAN* is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

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countries.

*Other brands and names may be claimed as the property of others.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

Contents

Overview .................................................................................................................................... 14

1.1.

System Architecture ...................................................................................................... 15

1.2.

Mobile Intel Pentium

4 Processor-M Host Interface .................................................... 15

1.2.1.

System Bus Error Checking ........................................................................ 16

1.3.

System Memory Interface ............................................................................................. 16

1.4.

AGP Interface................................................................................................................ 18

1.5.

Hub Interface................................................................................................................. 18

1.6.

MCH-M Clocking ........................................................................................................... 18

1.7.

System Interrupts .......................................................................................................... 19

Signal Description ...................................................................................................................... 20

2.1.

Host Interface Signals ................................................................................................... 21

2.2.

DDR Interface................................................................................................................ 23

2.3.

Hub Interface Signals .................................................................................................... 24

2.4.

AGP Interface Signals ................................................................................................... 24

2.4.1.

AGP Addressing Signals ............................................................................. 24

2.4.2.

AGP Flow Control Signals........................................................................... 25

2.4.3.

AGP Status Signals..................................................................................... 25

2.4.4.

AGP Strobes ............................................................................................... 26

2.4.5.

AGP/PCI Signals-Semantics ....................................................................... 27

2.5.

Clocks, Reset, and Miscellaneous ................................................................................ 30

2.6.

Voltage References, PLL Power ................................................................................... 31

2.7.

Pin State Table .............................................................................................................. 31

Register Description................................................................................................................... 36

3.1.

Conceptual Overview of the Platform Configuration Structure...................................... 36

3.2.

Standard PCI Bus Configuration Mechanism................................................................ 36

3.3.

Routing Configuration Accesses ................................................................................... 37

3.3.1.

PCI Bus #0 Configuration Mechanism ........................................................ 37

3.3.2.

Primary PCI and Downstream Configuration Mechanism........................... 37

3.3.3.

AGP Configuration Mechanism ................................................................... 38

3.4.

MCH-M Register Introduction........................................................................................ 38

3.5.

I/O Mapped Registers ................................................................................................... 39

3.5.1.

CONFIG_ADDRESS Configuration Address Register............................. 39

3.5.2.

CONFIG_DATA - Configuration Data Register ........................................... 41

3.6.

Memory Mapped Register Space.................................................................................. 42

3.6.1.

DRAMWIDTH--DRAM Width Register....................................................... 43

3.6.2.

DQCMDSTR Strength Control Register for DQ and CMD Signal

Groups

........................................................................................................ 44

3.6.3.

CKESTR Strength Control Register for CKE Signal Group ..................... 45

3.6.4.

CSBSTR Strength Control Register for CS# Signal Group...................... 46

3.6.5.

CKSTR Strength Control Register for CK Signal Group (CK / CK#)........ 47

3.6.6.

RCVENSTR Strength Control Register for RCVENOUT# Signals........... 48

3.7.

Host-Hub Interface Bridge Device Registers Device #0............................................. 48

3.7.1.

VID Vendor Identification Register Device#0 ........................................ 51

3.7.2.

DID Device Identification Register Device#0......................................... 51

3.7.3.

PCICMD PCI Command Register Device #0 ........................................ 52

3.7.4.

PCISTS PCI Status Register Device #0................................................ 53

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.5.

RID Revision Identification Register Device #0..................................... 54

3.7.6.

SUBC Sub-Class Code Register Device #0.......................................... 54

3.7.7.

BCC Base Class Code Register Device #0........................................... 54

3.7.8.

MLT Master Latency Timer Register Device #0.................................... 55

3.7.9.

HDR Header Type Register Device #0 ................................................. 55

3.7.10.

APBASE Aperture Base Configuration Register Device #0 .................. 56

3.7.11.

SVID Subsystem Vendor ID Device #0 ................................................. 57

3.7.12.

SID Subsystem ID Device #0 ................................................................ 57

3.7.13.

CAPPTR Capabilities Pointer Device #0............................................... 57

3.7.14.

AGPM- AGP Miscellaneous Configuration.................................................. 58

3.7.15.

DRB[0:7] DRAM Row Boundary Registers Device #0 .......................... 58

3.7.16.

DRA[0:7] DRAM Row Attribute Registers Device #0 ............................ 59

3.7.17.

DRT DRAM Timing Register Device #0 ................................................ 60

3.7.18.

DRC DRAM Controller Mode Register Device #0 ................................. 61

3.7.19.

DERRSYN DRAM Error Syndrome Register ........................................... 63

3.7.20.

EAP Error Address Pointer Register Device #0 .................................... 63

3.7.21.

PAM[0:6] Programmable Attribute Map Registers Device #0 ............... 64

3.7.22.

FDHC Fixed DRAM Hole Control Register Device #0........................... 68

3.7.23.

SMRAM System Management RAM Control Register Device #0......... 69

3.7.24.

ESMRAMC Extended System Mgmt RAM Control Register

Device #0 ................................................................................................. 70

3.7.25.

ACAPID AGP Capability Identifier Register Device #0.......................... 71

3.7.26.

AGPSTAT AGP Status Register Device #0 .......................................... 72

3.7.27.

AGPCMD AGP Command Register Device #0..................................... 73

3.7.28.

AGPCTRL AGP Control Register............................................................. 74

3.7.29.

APSIZE Aperture Size Device #0.......................................................... 75

3.7.30.

ATTBASE Aperture Translation Table Base Register Device #0.......... 76

3.7.31.

AMTT AGP Interface Multi-Transaction Timer Register Device #0 ...... 77

3.7.32.

LPTT AGP Low Priority Transaction Timer Register Device #0............ 78

3.7.33.

TOM Top of Low Memory Register Device #0 ...................................... 79

3.7.34.

MCH-MCFG MCH-M Configuration Register Device #0 ....................... 80

3.7.35.

ERRSTS Error Status Register Device #0 ............................................ 81

3.7.36.

ERRCMD Error Command Register Device #0 .................................... 82

3.7.37.

SMICMD SMI Command Register Device #0 ....................................... 83

3.7.38.

SCICMD SCI Command Register Device #0 ........................................ 83

3.7.39.

SKPD Scratchpad Data Device #0........................................................ 84

3.7.40.

CAPID Product Specific Capability Identifier............................................ 84

3.8.

AGP Bridge Registers Device #1 ............................................................................... 85

3.8.1.

VID1 Vendor Identification Register Device #1 ..................................... 87

3.8.2.

DID1 Device Identification Register Device #1...................................... 87

3.8.3.

PCICMD1 PCI-PCI Command Register Device #1............................... 88

3.8.4.

PCISTS1 PCI-PCI Status Register Device #1....................................... 89

3.8.5.

RID1 Revision Identification Register Device #1................................... 90

3.8.6.

SUBC1- Sub-Class Code Register Device #1.......................................... 90

3.8.7.

BCC1 Base Class Code Register Device #1......................................... 91

3.8.8.

MLT1 Master Latency Timer Register Device #1.................................. 91

3.8.9.

HDR1 Header Type Register Device #1 ............................................... 91

3.8.10.

PBUSN1 Primary Bus Number Register Device #1 .............................. 92

3.8.11.

SBUSN1 Secondary Bus Number Register Device #1 ......................... 92

3.8.12.

SUBUSN1 Subordinate Bus Number Register Device #1 .................... 92

3.8.13.

SMLT1 Secondary Master Latency Timer Register Device #1 ............. 93

3.8.14.

IOBASE1 I/O Base Address Register Device #1 .................................. 94

3.8.15.

IOLIMIT1 I/O Limit Address Register Device #1 ................................... 94

3.8.16.

SSTS1 Secondary PCI-PCI Status Register Device #1 ........................ 95

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82845MP/82845MZ Chipset-Mobile (MCH-M)

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Datasheet

3.8.17.

MBASE1 Memory Base Address Register Device #1 ........................... 96

3.8.18.

MLIMIT1 Memory Limit Address Register Device #1............................ 97

3.8.19.

PMBASE1 Prefetchable Memory Base Address Register Device #1 ... 98

3.8.20.

PMLIMIT1 Prefetchable Memory Limit Address Register Device #1 .... 99

3.8.21.

BCTRL1 PCI-PCI Bridge Control Register Device #1......................... 100

3.8.22.

ERRCMD1 Error Command Register Device #1 ................................ 101

3.8.23.

DWTMC DRAM Write Thermal Management Control ........................... 102

3.8.24.

DRTMC DRAM Read Thermal Management Control ............................ 104

System Address Map ............................................................................................................... 105

4.1.

Memory Address Ranges............................................................................................ 105

4.1.1.

VGA and MDA Memory Space.................................................................. 106

4.1.2.

PAM Memory Spaces................................................................................ 107

4.1.3.

ISA Hole Memory Space ........................................................................... 108

4.1.4.

TSEG SMM Memory Space ...................................................................... 108

4.1.5.

System Bus Interrupt APIC Memory Space .............................................. 109

4.1.6.

High SMM Memory Space ........................................................................ 109

4.1.7.

AGP Aperture Space (Device #0 BAR) ..................................................... 109

4.1.8.

AGP Memory and Prefetchable Memory................................................... 109

4.1.9.

Hub Interface A Subtractive Decode......................................................... 110

4.2.

AGP Memory Address Ranges ................................................................................... 110

4.2.1.

AGP DRAM Graphics Aperture................................................................. 110

4.3.

System Management Mode (SMM) Memory Range ................................................... 111

4.3.1.

SMM Space Definition............................................................................... 111

4.3.2.

SMM Space Restrictions ........................................................................... 112

4.4.

I/O Address Space ...................................................................................................... 112

4.5.

MCH-M Decode Rules and Cross-Bridge Address Mapping ...................................... 112

4.5.1.

Decode Rules for the Hub Interface A ...................................................... 112

4.5.2.

AGP Interface Decode Rules .................................................................... 113

Functional Description.............................................................................................................. 114

5.1.

Host Interface Overview .............................................................................................. 114

5.1.1.

Dynamic Bus Inversion.............................................................................. 114

5.1.2.

System Bus Interrupt Delivery................................................................... 114

5.1.3.

Upstream Interrupt Messages................................................................... 115

5.2.

System Memory Interface ........................................................................................... 115

5.2.1.

DDR Interface Overview............................................................................ 115

5.2.2.

Memory Organization and Configuration................................................... 116

5.2.2.1.

Configuration Mechanism for SO-DIMMs..................................... 116

5.2.2.1.1.

Memory Detection and Initialization............................ 116

5.2.2.1.2.

SMBus Configuration and Access of the Serial

Presence Detect Ports................................................ 116

5.2.2.1.3.

Memory Register Programming ................................. 116

5.2.3.

DRAM Performance Description ............................................................... 117

5.2.3.1.

Data Integrity (ECC) ..................................................................... 117

5.3.

AGP Interface Overview.............................................................................................. 117

5.3.1.

AGP Target Operations............................................................................. 118

5.3.2.

AGP Transaction Ordering........................................................................ 119

5.3.3.

AGP Signal Levels .................................................................................... 119

5.3.4.

4x AGP Protocol........................................................................................ 119

5.3.5.

Fast Writes ................................................................................................ 119

5.3.6.

AGP FRAME# Transactions on AGP........................................................ 120

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

5.3.6.1.

MCH-M Target and Initiator Operations for AGP FRAME#
Transactions ................................................................................. 120

5.4.

Power and Thermal Management ............................................................................... 122

5.4.1.

Various States ........................................................................................... 123

5.4.2.

General Description of Supported CPU States ......................................... 123

5.4.3.

General Description of ACPI System States ............................................. 124

5.4.4.

Power Transitions...................................................................................... 124

5.4.5.

Intel SpeedStep

Technology.................................................................... 125

5.5.

MCH-M Clocking ......................................................................................................... 125

5.6.

MCH-M System Reset and Power Sequencing........................................................... 125

Electrical Characteristics.......................................................................................................... 126

6.1.

Absolute Maximum Ratings......................................................................................... 126

6.2.

Thermal Characteristics .............................................................................................. 126

6.3.

Power Characteristics ................................................................................................. 127

Signal Groups .......................................................................................................................... 128

DC Characteristics ................................................................................................................... 130

Ballout and Package Information ............................................................................................. 133

9.1.

Ballout Diagram ........................................................................................................... 133

9.2.

Ballout Table................................................................................................................ 135

9.3.

Package Mechanical Information ................................................................................ 139

9.4.

Testability .................................................................................................................... 143

9.4.1.

XOR Test Mode Initialization..................................................................... 143

9.4.2.

XOR Chains .............................................................................................. 144

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

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Datasheet

Figures

Figure 1. Intel

845MP/845MZ Chipset System Block Diagram .............................................. 14

Figure 2. Configuration Address Register................................................................................ 39

Figure 3. Configuration Data Register...................................................................................... 41

Figure 4. PAM Register Attributes............................................................................................ 66

Figure 5. Addressable Memory Space................................................................................... 105

Figure 6. Detailed DOS Compatible Area Address Map........................................................ 106

Figure 7. Detailed Extended Memory Range Address Map................................................... 108

Figure 8. MCH-M BGA Package Dimensions (Top View)...................................................... 139

Figure 9. MCH-M BGA Package Dimensions (Side View)..................................................... 140

Figure 10. MCH-M BGA Package Dimensions (Bottom View) .............................................. 141

Figure 11. XORTree Chain .................................................................................................. 143

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Tables

Table 1. DDR Memory Capacity .............................................................................................. 16

Table 2. DDR Device Configurations ....................................................................................... 17

Table 3. MCH-M Clock Ratio Table ......................................................................................... 19

Table 4. Host Interface Signal Descriptions............................................................................. 21

Table 5. DDR Interface Signal Descriptions ............................................................................ 23

Table 6. Hub Interface Signal Descriptions.............................................................................. 24

Table 7. AGP Addressing Signal Descriptions......................................................................... 24

Table 8. AGP Flow Control Signal Descriptions....................................................................... 25

Table 9. AGP Status Signal Descriptions................................................................................. 25

Table 10. AGP Strobe Descriptions ......................................................................................... 26

Table 11. AGP/PCI Signal Semantics Descriptions................................................................. 27

Table 12. Clocks, Reset, and Miscellaneous Descriptions ...................................................... 30

Table 13. Voltage Reference Descriptions .............................................................................. 31

Table 14. Host Signals ............................................................................................................. 32

Table 15. DDR Signals............................................................................................................. 33

Table 16. AGP Signals............................................................................................................. 34

Table 17. Clock/Miscellaneous Signals ................................................................................... 35

Table 18. Hub Interface Signals............................................................................................... 35

Table 19. Device Number Assignment .................................................................................... 36

Table 20. Nomenclature for Access Attributes ........................................................................ 48

Table 21. MCH-M Configuration Space for Device #0............................................................. 49

Table 22. Control Signals for Various Memory Segments ....................................................... 65

Table 23. PAM Register Details ............................................................................................... 67

Table 24. Nomenclature for Access Attributes ........................................................................ 85

Table 25. MCH-M Configuration Space - Device #1................................................................ 85

Table 26. SMM Space............................................................................................................ 111

Table 27. Relation of DBI Bits to Data Bits ............................................................................ 114

Table 28. Data Bytes on SO-DIMM Used for Programming DRAM Registers ...................... 117

Table 29. AGP Commands Supported by the MCH-M When Acting as an AGP Target....... 118

Table 30. Fast Write Initialization........................................................................................... 120

Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target ... 120

Table 32. Power Management State Combinations .............................................................. 123

Table 33. Intel

845MP/845MZ Power Transitions .................................................................. 124

Table 34. Absolute Maximum Ratings ................................................................................... 126

Table 35. Intel 845MP/845MZ Chipset MCH-M Package Thermal Resistance..................... 126

Table 36. Power Characteristics ............................................................................................ 127

Table 37. Signal Groups ........................................................................................................ 128

Table 38. DC Characteristics ................................................................................................. 130

Table 39. Top View (Left Side)............................................................................................... 133

Table 40. Top View (Right Side) ............................................................................................ 134

Table 41. FCBGA Handling Zone Description ....................................................................... 142

Table 42. XOR Chains ........................................................................................................... 144

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Reference Documents

Document

Number/Location

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide

www.developer.intel.com

Intel

82801CAM I/O Controller Hub 3 (ICH3-M) Datasheet

www.developer.intel.com

Intel

DDR200 JEDEC Specification Addendum, Revision 1.0

www.developer.intel.com

Intel

DDR266 JEDEC Specification Addendum, Revision 0.9

www.developer.intel.com

JEDEC Double Data Rate (DDR) SDRAM Specification, Revision 2.0

www.jedec.org

JEDEC PC2100 DDR SDRAM Un-buffered SO-DIMM Reference Design Specification
(includes PC1600 DDR SDRAM)

www.jedec.org

Accelerated Graphics Port Interface Specification Rev 2.0

http://www.agpforum.org/

PCI Local Bus Specification Rev. 2.1

www.pcisig.com

PCI-PCI Bridge Specification Rev. 1.0

www.pcisig.com

PCI Bus Power Management Interface Specification Rev. 1.0

www.pcisig.com

Advanced Configuration and Power Interface Specification (ACPI) Rev. 1.0b

www.teleport.com/~acpi/

Note: See Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform Design Guide

for an expanded set of related documents.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

Terminology

MCH-M - The Mobile Memory Controller Hub-M component that contains the processor interface,
DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH3-M) and other
IO controller hubs over proprietary interconnect called the hub interface.

ICH3-M - The Mobile I/O Controller Hub 3-M component that contains the primary PCI interface, LPC
interface, USB, ATA-100, AC'97, and other IO functions. It communicates with the Intel

845MP/845MZ Chipset MCH-M over a proprietary interconnect called hub interface.

Host - This term is used synonymously with processor.

Core - The internal base logic in the MCH-M.

System Bus - Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus
plus enhancements, consisting of source synchronous transfers for address and data, and system bus
interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode.

Hub interface - The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document
hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is
generally referred to as hub interface cycles.

Accelerated Graphics Port (AGP) - Refers to the AGP interface that is in the MCH-M. It supports
AGP 2.0 compliant components only with 1.5V signaling level. PIPE# and SBA addressing cycles and
their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP
bus are generally referred to as AGP/PCI transactions.

PCI_A - The physical PCI bus, driven directly by the ICH3-M component. It supports 5-V, 32-bit, 33-
MHz PCI 2.2 compliant components. Communication between PCI_A and MCH-M occurs over hub
interface. Note: Even though it is referred to as PCI_A it is not PCI Bus #0 from a configuration
standpoint.

Full Reset - A Full MCH-M Reset is defined in this document when RSTIN# is asserted.

System Bus - Synonymous with Host or Front Side Bus

GART - Graphics Aperture Re-map Table. This table contains the page re-map information used during
AGP aperture address translations.

GTLB - Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.

UP Uniprocessor

DBI Dynamic Bus inversion

MSI Message Signaled Interrupts. MSI's allow a device to request interrupt service via a standard
Memory Write transaction instead of through a hardware signal.

IPI Inter Processor Interrupt

Word 16 bits = 2 bytes

Dword (DW) Doubleword: 32bits = 4 bytes

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

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Datasheet

Intel

845 Chipset MCH-M Features

Processor/Host Bus Support

Supports the Mobile Intel Pentium 4 Processor-M

CPU

Supports the Intel Pentium

4 processor subset of

the Enhanced Mode Scaleable Bus Protocol

2x Address, 4x Data

Mobile Intel Pentium 4 Processor-M System Bus

interrupt delivery

Supports system bus at 400 MT/s (100 MHz)

Supports host bus Dynamic Bus Inversion (DBI)

Supports 32-bit host bus addressing

12 deep In-Order Queue

AGTL+ bus driver technology with integrated

AGTL termination resistors

Memory System

Directly supports one DDR channel, 64b wide (72b

with ECC).

Supports 200 and 266-MHz DDR compliant

devices (845MZ supports 200 MHz DDR only)

Supports 64-Mb, 128-Mb, 256-Mb and 512-Mb

technologies for x16 devices and x8 devices.

All supported devices have 4 banks

Configurable optional ECC operation (single bit

Error Correction and multiple bit Error Detection)

Supports up to 16 simultaneous open pages

Supports page sizes of 2 KB, 4 KB, 8 KB, and 16

KB. Page size is individually selected for every
row.

Thermal throttling scheme to selectively throttle

reads and/or writes. Throttling can be triggered by
preset read/write bandwidth limits.

Max of 2 double-sided (4 rows populated) with

unbuffered PC2100 DDR (with or without ECC)
SO-DIMMs (845MZ supports only 200-MHz
DDR).

Largest memory supported is 1 GB (845MZ

supports only up to 512 MB).

System Interrupts

Supports only System Bus interrupt delivery

mechanism

Supports interrupts signaled as upstream Memory

Writes from AGP/PCI (PCI semantics only) and
hub interface

MSI direct to the System Bus

Supports peer MSI between hub interface and AGP

Provides redirection for IPI and upstream

interrupts to the System Bus

Accelerated Graphics Port (AGP) Interface

Supports a single AGP device (either a connector

or on the motherboard)

AGP Support

Supports AGP 2.0 including 1x, 2x, and 4x AGP

data transfers and 2x/4x Fast Write protocol

Supports only 1.5-V AGP electricals

32 deep AGP request queue

PCI semantic (FRAME# initiated) accesses to

DRAM are snooped

High priority access support

Hierarchical PCI configuration mechanism

Delayed transaction support for AGP-to-DRAM

FRAME# semantic reads that can not be serviced
immediately

32-bit upstream address support for inbound AGP

and PCI cycles

32-bit downstream address support for outbound

PCI and Fast Write cycles

AGP Busy/Stop Protocol

AGP Clamping and Sense Amp Control

Hub Interface to ICH3-M

266-MB/s, point-to-point hub interface to ICH3-M

66-MHz base clock

Supports the following traffic types to the ICH3-M

Hub interface-to-AGP memory writes

Hub interface-to-DRAM

CPU-to-hub interface

Messaging

MSI Interrupt messages

Power Management state change

SMI, SCI and SERR error indication

Power Management

SMRAM space remapping to A0000h (128 KB)

Supports extended SMRAM space above 256 MB,

additional 128K/256K/512K TSEG from Top of
Memory, cacheable (cacheability controlled by
CPU)

APM Rev 1.2 compliant power management

Suspend to System Memory

ACPI 2.0 Support

Intel SpeedStep technology support

Cache coherency with CPU in sleep mode

Dynamic Memory Power-down

Package

Package options

593-pin FC-BGA (37.5 x 37.5 mm)

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

1. Overview

Figure 1. Intel

845MP/845MZ Chipset System Block Diagram

The Intel

845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) is designed for use with the

Mobile Intel Pentium 4 Processor-M. The Intel

845MP/845MZ Chipset MCH-M manages the flow of

information between its four interfaces: the System Bus, the memory interface, the AGP port, and the hub
interface. The MCH-M arbitrates between the four interfaces when each initiates an operation. While
doing so, the MCH-M must support data coherency via snooping and must perform address translation
for access to AGP Aperture memory.

The Intel

845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) may contain design defects or

errors known as errata, which may cause the product to deviate from published specifications.

Intel

845MP or

845MZ Chipset

(MCH-M)

Mobile Intel

Pentium

4 Processor-M

ICH3-M

PCI Bus

USB

SIO

Device

AGP

FWH

AC'97 Codec

Sys Me

y
s Me

Primary & Secondary

IDE

Intel

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Datasheet

1.1. System

Architecture

The Intel

845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) component provides the

processor interface, DRAM interface, AGP interface, and hub interface. The CPU interface supports the
Mobile Intel Pentium 4 Processor-M subset of the Extended Mode of the Scalable Bus Protocol. The
Intel

845MP/845MZ Chipset is optimized for the Mobile Intel Pentium 4 Processor-M. It supports a

single channel of DDR memory. The MCH-M contains advanced power management logic. The Intel
845MP/845MZ Chipset platform supports the third generation mobile I/O Controller Hub (ICH3-M) to
provide the features required by a mobile platform.

The Intel

845 Chipset-Mobile Family (MCH-M) is in a 593-pin FC-BGA package and contains the

following functionality:

· Supports single Mobile Intel Pentium 4 Processor-M configurations at 400 MT/s
· AGTL+ host bus with integrated termination supporting 32-bit host addressing
· 845MP supports up to 1 GB of PC2100 Memory
· 845MZ supports up to 512 MB of PC1600 Memory
· 1.5-V AGP interface with 4x SBA/PIPE# Data Transfer and Fast Write capability
· 1.8-V, 8-bit, 66-MHz 4x hub interface to ICH3-M
· Deeper Sleep
· Intel SpeedStep

technology

· Distributed arbitration for highly concurrent operation

1.2.

Mobile Intel Pentium

4 Processor-M Host Interface

The Intel

845MP/845MZ Chipset MCH-M is optimized for the Mobile Intel Pentium 4 Processor-M. The

primary enhancements over the Compatible Mode P6 bus protocol are:

· Source synchronous double pumped address
· Source synchronous quad pumped data
· System bus interrupt and side-band signal delivery

In this mode, the MCH-M supports a 64B cache line size. Only one processor is supported at a System
bus frequency of 400 MT/s. The MCH-M integrates AGTL+ termination resistors on all of the AGTL+
signals. The MCH-M supports 32-bit host addresses, allowing the CPU to access the entire 4 GB of the
MCH-M memory address space.

The MCH-M has a 12-deep In-Order Queue to support up to 12 outstanding pipelined address requests
on the host bus. The MCH-M supports two outstanding defer cycles at a time; however, only one to any
particular IO interface. Host initiated I/O cycles are positively decoded to AGP/PCI or MCH-M
configuration space and subtractively decoded to the hub interface. Host initiated memory cycles are
positively decoded to AGP/PCI or DRAM. AGP semantic memory accesses initiated from AGP/PCI to
DRAM are not snooped on the host bus. Memory accesses initiated from AGP/PCI using PCI semantics
and from the hub interface to DRAM will be snooped on the System bus. Memory accesses whose

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addresses lie within the AGP aperture are translated using the AGP address translation table, regardless
of the originating interface.

1.2.1.

System Bus Error Checking

The Intel

845MP/845MZ Chipset MCH-M does not generate nor check parity for Data, Address/Request,

and Response signals on the processor bus.

1.3.

System Memory Interface

The Intel

845MP/845MZ Chipset memory controller directly supports one channel of PC1600 or

PC2100 (845MZ PC1600 only) SO-DIMM DDR memory. The Intel

845MP/845MZ Chipset memory

interface supports DDR devices with densities of 64-Mb, 128-Mb, 256-Mb, and 512-Mb technology.
The maximum memory support is two, double-sided SO-DIMMs (four rows populated). The Intel

845MP/845MZ Chipset memory interface also supports variable page sizes of 2 KB, 4 KB, 8 KB, and 16
KB. Page size is individually selected for every row and a maximum of 16 pages may be opened
simultaneously.

Table 1. DDR Memory Capacity

Technology

845MP/845MZ Maximum

64 Mb

128 MB/128 MB

128 Mb

256 MB/256 MB

256 Mb

512 MB/512 MB

512 Mb

1 GB/ 512 MB

The memory interface provides optional ECC error checking for DRAM data integrity. During DRAM
writes, ECC is generated on a QWORD (64 bit) basis. Because the Intel

845MP/845MZ Chipset MCH-

M stores only entire cache lines in its internal buffers, partial QWORD writes initially cause a read of the
underlying data, and their write-back into memory is no different from that of a complete cache line.
During DRAM reads and the read of the data that underlies partial writes, the MCH-M supports
detection of single-bit and multiple-bit errors, and will correct single bit errors when correction is
enabled.

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Datasheet

Table 2. DDR Device Configurations

SO-

DIMM

Capacity

SO-DIMM

Organization

Density DDR

Organization

# of

Components

Package

Type

# of

Physical

Banks

# of

Banks

in DDR

# Address

Bits

(row/col)

64 MB

8M x 64

64 Mbit

4M x 16

66 lead

TSOP

2 4 12/8

64 MB

8M x 64

128 Mbit

8M x 16

66 lead

TSOP

1 4 12/9

64 MB

8M x 72

128 Mbit

8M x 16

66 lead

TSOP

1 4 12/9

128 MB

16M x 64

128 Mbit

8M x 16

66 lead

TSOP

2 4 12/9

128 MB

16M x 64

256 Mbit

16M x 16

66 lead

TSOP

1 4 13/9

128 MB

16M x 72

256 Mbit

16M x 16

66 lead

TSOP

1 4 13/9

256 MB

32M x 64

256 Mbit

16M x 16

66 lead

TSOP

2 4 13/9

256 MB

32M x 64

512 Mbit

32M x 16

66 lead

TSOP

1 4

13/10

256 MB

32M x 72

512 Mbit

32M x 16

66 lead

TSOP

1 4

13/10

512 MB

64M x 64

512 Mbit

32M x 16

66 lead

TSOP

2 4

13/10

64 MB

8M x 64

64 Mbit

8M x 8

66 lead

TSOP

1 4 12/9

128 MB

16M x 64

128 Mbit

16M x 8

66 lead

TSOP

1 4

12/10

256 MB

32M x 64

256 Mbit

32M x 8

66 lead

TSOP

1 4

13/10

512 MB

64M x 64

512 Mbit

64M x 8

66 lead

TSOP

1 4

13/11

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1.4. AGP

Interface

A single AGP component or connector (not both) is supported by the Intel

845MP/845MZ Chipset

MCH-M AGP interface. The AGP buffers operate only in 1.5-V mode. They are not 3.3-V safe.

The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x Fast Writes. AGP semantic cycles to
DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on the host bus. The
MCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the
PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and
downstream addressing is limited to 32 bits for AGP and AGP/PCI transactions. The MCH-M contains a
32-deep AGP request queue. High priority accesses are supported. All accesses from the AGP/PCI
interface that fall within the Graphics Aperture address range pass through an address translation
mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited
to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked
from a dedicated 66MHz clock (66IN). The AGP-to-host/core interface is asynchronous.

Consult the latest AGP Busy and Stop Protocol Specification for more information.

1.5. Hub

Interface

The 8-bit hub interface connects the MCH-M to the ICH3-M. All communication between the MCH-M
and the ICH3-M occurs over the hub interface. The hub interface runs at 66 MHz/266 MB/s. Aside from
the obvious traffic types, the following communication also occur over hub interface:

· Interrupt related messages
· Power management events as messages
· SMI, SCI, and SERR error indication messages

It is assumed that the hub interface is always connected to an ICH3-M. This is a proprietary interconnect
between the MCH-M and the ICH3-M.

1.6. MCH-M

Clocking

The MCH-M has the following clock input pins:

· Differential BCLK[1:0] for the host interface
· 66-MHz clock input for the AGP and hub interface

Clock Synthesizer chip(s) are responsible for generating the system Host clocks, AGP and hub interface
clocks, PCI clocks, and DRAM clocks. The Host target speed is 400 MT/s. The MCH-M does not
require any relationship between the HCLKIN host clock and the 66-MHz clock generated for AGP and
hub interface; they are totally asynchronous from each other. The AGP and hub interface runs at a
constant 66-MHz base frequency. The hub interface runs at 4x, while AGP transfers may be 1x, 2x, or
4x.

The following tables indicate the frequency ratios between the various interfaces that the MCH-M
supports.

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Table 3. MCH-M Clock Ratio Table

Interface

Speed

CPU System Bus Frequency Ratio

System Memory

DDR 200 MHz

1:1 synchronous

AGP 66

MHz Asynchronous

Hub interface

66 MHz

Asynchronous

1.7. System

Interrupts

The Intel

845MP/845MZ Chipset MCH-M supports both 8259 and Intel Mobile Pentium 4 Processor-M

interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported.

The 8259 support consists of flushing inbound hub interface write buffers when an Interrupt
Acknowledge cycle is forwarded from the system bus to the hub interface.

The Intel

845MP/845MZ Chipset MCH-M supports the Mobile Intel Pentium 4 Processor-M interrupt

delivery mechanism. PCI MSI interrupts are generated as Memory Writes. The MCH-M decodes
upstream Memory Writes to the range 0FEE0_0000h - 0FEEF_FFFFh from AGP and the hub interface
as message based interrupts. The MCH-M forwards the Memory Writes, along with the associated write
data, to the system bus as an Interrupt Message transaction. Note that since this address does not decode
as part of main memory, the write cycle and the write data does not get forwarded to DRAM via the write
buffer. The Intel

845MP/845MZ Chipset MCH-M provides the response and TRDY# for all Interrupt

Message cycles including the ones originating from the MCH-M. The Intel

845MP/845MZ Chipset

MCH-M supports interrupt re-direction for inter-processor interrupts (IPIs) as well as upstream interrupt
memory writes.

For message based interrupts, system write buffer coherency is maintained by relying on strict ordering
of Memory Writes. The Intel

845MP/845MZ Chipset MCH-M ensures that all Memory Writes received

from a given interface prior to an interrupt message Memory Write are delivered to the system bus for
snooping in the same order that they occur on the given interface.

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2. Signal

Description

This section provides a detailed description of Intel

845MP/845MZ Chipset MCH-M signals. The signals

are arranged in functional groups according to their associated interface. The states of all of the signals
during reset are provided in the System Reset section.

The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when
at the high voltage level.

The following notations are used to describe the signal type:

I Input

O Output

I/O

Bi-directional Input/Output pin

s/t/s

Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.

as/t/s

Active Sustained Tristate. This applies to some of the hub interface signals. This pin
is weakly driven to its last driven value.

The signal description also includes the type of buffer used for the particular signal:

AGTL+

Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The Intel

845MP/845MZ Chipset MCH-M integrates AGTL+

termination resistors.

AGP

AGP interface signals. These signals are compatible with AGP 2.0 1.5v Signaling
Environment DC and AC Specifications. The buffers are not 3.3v tolerant.

CMOS

CMOS buffers.

Ref

Voltage reference signal.

Note: System address and data bus signals are logically inverted signals. The actual values are inverted of what

appears on the system bus. This must be taken into account and the addresses and data bus signals must
be inverted inside the Intel

845MP/845MZ Chipset MCH-M. All processor control signals follow normal

convention. A "0" indicates an active level (low voltage) if the signal is followed by "#" symbol, and a
"1" indicates an active level (high voltage) if the signal has no "#" suffix.

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2.1.

Host Interface Signals

Table 4. Host Interface Signal Descriptions

Signal Name

Type

Description

ADS#

I/O

AGTL+

Address Strobe: The system bus owner asserts ADS# to indicate the first of two
cycles of a request phase.

BNR#

I/O

AGTL+

Block Next Request: Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the system bus pipeline
depth.

BPRI#

AGTL+

Bus Priority Request: The MCH-M is the only Priority Agent on the system bus. It
asserts this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was asserted.

BR0#

I/O

AGTL+

Bus Request 0#: The MCH-M pulls the processor bus' BR0# signal low during
CPURST#. The signal is sampled by the processor on the active-to-inactive
transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The
minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. BR0#
should be tristated after the hold time requirement has been satisfied.

CPURST#

AGTL+

CPU Reset: The CPURST# pin is an output from the MCH-M. The MCH-M asserts
CPURST# while RSTIN# (PCIRST# from ICH3-M) is asserted and for
approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the
processor's to begin execution in a known state.

DBSY#

I/O

AGTL+

Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.

DEFER#

AGTL+

Defer Response: Signals that the MCH-M will terminate the transaction currently
being snooped with either a deferred response or with a retry response.

DBI[3:0]#

I/O

AGTL+ 4x

Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the
associated signals are inverted or not. DBI[3:0]# are asserted such that the
number of data bits driven electrically low (low voltage) within the corresponding
16-bit group never exceeds 8.

DBI[x]# Data

Bits

DBI3# HD[63:48]#
DBI2# HD[47:32]#
DBI1# HD[31:16]#
DBI0# HD[15:0]#

DRDY#

I/O

AGTL+

Data Ready: Asserted for each cycle that data is transferred.

HA[31:3]#

I/O

AGTL+ 2x

Host Address Bus: HA[31:3]# connect to the system address bus. During
processor cycles the HA[31:3]# are inputs. The MCH-M drives HA[31:3]# during
snoop cycles on behalf of hub interface and AGP/Secondary PCI initiators.
HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the
system bus.

HADSTB[1:0]#

I/O

AGTL+ 2x

Host Address Strobe: The source synchronous strobes used to transfer
HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.

Strobe Address

Bits

HADSTB0# HA[16:3]#,

HREQ[4:0]#

HADSTB1# HA[31:17]#

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Signal Name

Type

Description

HD[63:0]#

I/O

AGTL+ 4x

Host Data: These signals are connected to the system data bus. HD[63:0]# are
transferred at 4x rate. Note that the data signals are inverted on the system bus.

HDSTBP[3:0]#

HDSTBN[3:0]#

I/O

AGTL+ 4x

Differential Host Data Strobes: The differential source synchronous strobes used
to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer rate.

Strobe Data

Bits

HDSTBP3#, HDSTBN3#

HD[63:48]#, DBI3#

HDSTBP2#, HDSTBN2#

HD[47:32]#, DBI2#

HDSTBP1#, HDSTBN1#

HD[31:16]#, DBI1#

HDSTBP0#, HDSTBN0#

HD[15:0]#, DBI0#

HIT#

I/O

AGTL+

Hit: Indicates that a caching agent holds an unmodified version of the requested
line. Also, driven in conjunction with HITM# by the target to extend the snoop
window.

HITM#

I/O

AGTL+

Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.

HLOCK#

AGTL+

Host Lock: All system bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface or
AGP snoopable access to DRAM are allowed when HLOCK# is asserted by the
processor.

HREQ[4:0]#

I/O

AGTL+ 2x

Host Request Command: Defines the attributes of the request. In Enhanced
Mode HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent
during both halves of Request Phase. In the first half the signals define the
transaction type to a level of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define the complete
transaction type.

The transactions supported by the MCH-M Host Bridge are defined in the Host
Interface section of this document.

HTRDY#

AGTL+

Host Target Ready: Indicates that the target of the processor transaction is able
to enter the data transfer phase.

RS[2:0]#

AGTL+

Response Status: Indicates type of response according to the following the table:

RS[2:0] Response

type

000

Idle

state

001

Retry

response

010

Deferred

response

011

Reserved (not driven by MCH-M)

100

Hard Failure (not driven by MCH-M)

101

No data response

110

Implicit

Write

back

111

Normal data response

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2.2. DDR

Interface

Table 5. DDR Interface Signal Descriptions

Signal Name

Type

Description

SCS#[3:0]

CMOS

Chip Select: These pins select the particular DDR components during the active
state.

Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge.

SMA[12:0]

CMOS

Multiplexed Memory Address: These signals are used to provide the multiplexed
row and column address to DDR.

SBS[1:0]

CMOS

Memory Bank Address: These signals define the banks that are selected within
each DDR row. The SMA and SBS signals combine to address every possible
location within a DDR device.

SRAS#

CMOS

DDR Row Address Strobe: SRAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs: Used with SCAS# and SWE# (along with
SCS#) to define the DRAM commands.

SCAS#

CMOS

DDR Column Address Strobe: SCAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs. Used with SRAS# and SWE# (along with
SCS#) to define the DRAM commands.

SWE#

I/O

CMOS

Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the
DRAM commands. SWE# is asserted during writes to DDR. SWE# may be heavily
loaded and requires 2 DDR clock cycles for setup time to the DDRs.

SDQ[63:0]

I/O

CMOS 2X

Data Lines: These signals are used to interface to the DDR data bus.

SCB[7:0]

I/O

CMOS 2X

Data Lines: These signals are used to interface to the SDRAM ECC signals (to be
used if SO-DIMMs support ECC).

SDQS[8:0]

I/O

CMOS

Data Strobes:

There is an associated data strobe (DQS) for each data strobe (DQ) and check
bit (CB) group.

SDQS8 -> SCB[7:0]
SDQS7 -> SDQ[63:56]
SDQS6 -> SDQ[55:48]
SDQS5 -> SDQ[47:40]
SDQS4 -> SDQ[39:32]
SDQS3 -> SDQ[31:24]
SDQS2 -> SDQ[23:16]
SDQS1 -> SDQ[15:8]
SDQS0 -> SDQ[7:0]

SCKE[3:0]

CMOS

Clock Enable: These pins are used to signal a self-refresh or power down
command to a DDR array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR rows. There is one SCKE per DDR row.
These signals can be toggled on every rising SCLK edge.

RCVENOUT#

CMOS

Clock Output: Used to emulate source-synch clocking for reads. Connects to
RCVENIN#.

RCVENIN#

CMOS

Clock Input: Used to emulate source-synch clocking for reads. Connects to
RCVENOUT#.

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2.3.

Hub Interface Signals

Table 6. Hub Interface Signal Descriptions

Signal Name

Type

Description

HI_[10:0]

I/O

CMOS

Hub Interface Signals: Signals used for the hub interface.

HI_STB

I/O

CMOS

Hub Interface Strobe: One of two differential strobe signals used to transmit or
receive packet data over hub interface.

HI_STB#

I/O

CMOS

Hub Interface Strobe Compliment: One of two differential strobe signals used to
transmit or receive packet data over hub interface.

2.4.

AGP Interface Signals

2.4.1.

AGP Addressing Signals

Table 7. AGP Addressing Signal Descriptions

Signal Name

Type

Description

PIPE#

AGP

Pipelined Read: This signal is asserted by the AGP master to indicate a full width
address is to be enqueued on by the target using the AD bus. One address is placed
in the AGP request queue on each rising clock edge while PIPE# is asserted. When
PIPE# is deasserted no new requests are queued across the AD bus.

During SBA Operation: This signal is not used if SBA (Side Band Addressing) is
selected.

During FRAME# Operation: This signal is not used during AGP FRAME#
operation.

PIPE# is a sustained tri-state signal from the AGP masters (graphics controller) and
is an MCH-M input.

SBA[7:0]

AGP

Side-band Address: These signals are used by the AGP master (graphics
controller) to place addresses into the AGP request queue. The SBA bus and AD
bus operate independently. That is, transaction can proceed on the SBA bus and
the AD bus simultaneously.

During PIPE# Operation: These signals are not used during PIPE# operation.

During FRAME# Operation: These signal are not used during AGP FRAME#
operation.

Note: When sideband addressing is disabled, these signals are isolated (no
external/internal pull-ups are required).

NOTE: The above table contains two mechanisms, SBA and PIPE#, to queue requests by the AGP master. Note

that the master can only use one mechanism. The master may not switch methods without a full reset of
the system. When PIPE# is used to queue addresses, the master is not allowed to queue addresses
using the SBA bus. For example, during configuration time, if the master indicates that it can use either
mechanism, the configuration software will select which mechanism the master will use. Once this choice
has been made, the master must continue to use the mechanism selected until the master is reset (and
reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a
static decision when the device is first being configured after reset.

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2.4.2.

AGP Flow Control Signals

Table 8. AGP Flow Control Signal Descriptions

Signal Name

Type

Description

RBF#

AGP

Read Buffer Full: Indicates if the master is ready to accept previously requested
low priority read data. When RBF# is asserted, the MCH-M is not allowed to initiate
the return of low priority read data. That is, the MCH-M can only finish returning the
data for the request currently being serviced. RBF# is only sampled at the
beginning of a cycle.

If the AGP master is always ready to accept return read data then it is not required
to implement this signal.

During FRAME# Operation: This signal is not used during AGP FRAME#
operation.

WBF#

AGP

Write-Buffer Full: indicates if the master is ready to accept Fast Write data from
the MCH-M. When WBF# is asserted the MCH-M is not allowed to drive Fast Write
data to the AGP master. WBF# is only sampled at the beginning of a cycle.

If the AGP master is always ready to accept fast write data then it is not required to
implement this signal.

During FRAME# Operation: This signal is not used during AGP FRAME#
operation.

2.4.3.

AGP Status Signals

Table 9. AGP Status Signal Descriptions

Signal Name

Type

Description

ST[2:0]

AGP

Status: Provides information from the arbiter to an AGP Master on what it may do.
ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT#
is deasserted these signals have no meaning and must be ignored. Refer to the
AGP Interface Specification revision 2.0 for further explanation of the ST[2:0]
values and their meanings.

During FRAME# Operation: These signals are not used during FRAME# based
operation; except that a `111' indicates that the master may begin a FRAME#
transaction.

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2.4.4. AGP

Strobes

Table 10. AGP Strobe Descriptions

Signal Name

Type

Description

AD_STB0

I/O

(s/t/s)

AGP

Address/Data Bus Strobe-0: provides timing for 2x and 4x data on AD[15:0] and
C/BE[1:0]# signals. The agent that is providing the data will drive this signal.

AD_STB0#

I/O

(s/t/s)

AGP

Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential
strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]#
signals. The agent that is providing the data will drive this signal.

AD_STB1

I/O

(s/t/s)

AGP

Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on AD[31:16]
and C/BE[3:2]# signals. The agent that is providing the data will drive this signal.

AD_STB1#

I/O

(s/t/s)

AGP

Address/Data Bus Strobe-1 Complement: With AD STB1, forms a differential
strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals
in 4X mode. The agent that is providing the data will drive this signal.

SB_STB

AGP

Sideband Strobe: Provides timing for 2x and 4x data on the SBA[7:0] bus. The
AGP master drives it after the system has been configured for 2x or 4x sideband
address mode.

SB_STB#

AGP

Sideband Strobe Complement: The differential complement to the SB_STB
signal. It is used to provide timing 4x mode.

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2.4.5. AGP/PCI

Signals-Semantics

For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similar
to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined
below.

Table 11. AGP/PCI Signal Semantics Descriptions

Signal Name

Type

Description

G_FRAME#

I/O

s/t/s

AGP

G_FRAME: Frame

During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations.

During Fast Write Operation: Used to frame transactions as an output during
Fast Writes.

During FRAME# Operation: G_FRAME# is an output when the MCH-M acts as
an initiator on the AGP Interface. G_FRAME# is asserted by the MCH-M to indicate
the beginning and duration of an access. G_FRAME# is an input when the MCH-M
acts as a FRAME#-based AGP target. As a FRAME#-based AGP target, the MCH-
M latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which
MCH-M samples FRAME# active.

G_IRDY#

I/O

s/t/s

AGP

G_IRDY#: Initiator Ready

During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.

During FRAME# Operation: G_IRDY# is an output when MCH-M acts as a
FRAME#-based AGP initiator and an input when the MCH-M acts as a FRAME#-
based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based
AGP bus initiator's ability to complete the current data phase of the transaction.

During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the
AGP-compliant master is ready to provide all write data for the current transaction.
Once G_IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The master is never allowed to insert a wait state during the initial data
transfer (32 bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.

G_TRDY#

I/O

s/t/s

AGP

G_TRDY#: Target Ready

During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.

During FRAME# Operation: G_TRDY# is an input when the MCH-M acts as an
AGP initiator and is an output when the MCH-M acts as a FRAME#-based AGP
target. The assertion of G_TRDY# indicates the target's ability to complete the
current data phase of the transaction.

During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-
compliant target is ready to receive write data for the entire transaction (when the
transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is transferred
on write transactions.

Intel

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Signal Name

Type

Description

G_STOP#

I/O

s/t/s

AGP

G_STOP#: Stop

During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.

During FRAME# Operation: G_STOP# is an input when the MCH-M acts as a
FRAME#-based AGP initiator and is an output when the MCH-M acts as a
FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort
sequences on the AGP interface

G_DEVSEL#

I/O

s/t/s

AGP

G_ DEVSEL#: Device Select

During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.

During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a
FRAME#-based AGP target device has decoded its address as the target of the
current access. The MCH-M asserts G_DEVSEL# based on the SDRAM address
range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates
whether the AGP master has recognized a PCI cycle to it.

G_REQ#

AGP

G_REQ#: Request

During SBA Operation: This signal is not used during SBA operation.

During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that
the AGP master is requesting use of the AGP interface to run a FRAME#- or
PIPE#-based operation.

G_GNT#

AGP

G_GNT#: Grant

During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the
information on the ST[2:0] signals (status bus), indicates how the AGP interface will
be used next. Refer to the AGP Interface Specification, Revision 2.0 for further
explanation of the ST[2:0] values and their meanings.

G_AD[31:0]

I/O

AGP

G_AD[31:0]: Address/Data Bus

During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to
transfer both address and data information on the AGP interface.

During SBA Operation: The G_AD[31:0] signals are used to transfer data on the
AGP interface.

G_CBE[3:0]#

I/O

AGP

Command/Byte Enable

During FRAME# Operation: During the address phase of a transaction, the
G_CBE[3:0]# signals define the bus command. During the data phase, the
G_CBE[3:0]# signals are used as byte enables. The byte enables determine which
byte lanes carry meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE# command
described in the PCI 2.2 specification.

During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE#
signals carry command information. Refer to the AGP 2.0 Interface Specification,
Revision 2.0 for the definition of these commands. The command encoding used
during PIPE#-based AGP is different than the command encoding used during
FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus).

During SBA Operation: These signals are not used during SBA operation.

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2.5.

Clocks, Reset, and Miscellaneous

Table 12. Clocks, Reset, and Miscellaneous Descriptions

Signal Name

Type

Description

BCLK /
BCLK#

CMOS

Differential Host Clock In: These pins receive a differential host clock from the
external clock synthesizer. This clock is used by all of the MCH-M logic that is in
the Host clock domain.

66IN

CMOS

66-MHz Clock In: This pin receives a 66-MHz clock from the clock synthesizer.
This clock is used by AGP/PCI and hub interface clock domains.

Note: That this clock input is 3.3-V tolerant.

SCK[5:0]

CMOS

SDRAM Differential Clock (DDR): These signals deliver a source synchronous
clock to

the SO-DIMMs. There are three per SO-DIMM.

SCK#[5:0]

CMOS

SDRAM Inverted Differential Clock (DDR): These signals are the complement to
the SCK[5:0] signals. There are three per

SO-DIMM.

RSTIN#

CMOS

Reset In: When asserted this signal will asynchronously reset the MCH-M logic.
This signal is connected to the PCIRST# output of the ICH3-M. All AGP/PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.

Note: That this input needs to be 3.3-V tolerant.

TESTIN#

CMOS

Test Input: This pin is used for manufacturing and board level test purposes.

Note: This signal has an internal pullup resistor.

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2.6.

Voltage References, PLL Power

Table 13. Voltage Reference Descriptions

Signal Name

Type

Description

HVREF

Ref

Host Reference Voltage. Reference voltage input for the Data, Address, and
Common clock signals of the Host AGTL+ interface

SDREF

Ref

DDR Reference Voltage: Reference voltage input for DQ, DQS, & RCVENIN#.

REF

Ref

Hub Interface Reference: Reference voltage input for the hub interface.

AGPREF

Ref

AGP Reference: Reference voltage input for the AGP interface.

HLRCOMP

I/O

CMOS

Compensation for hub interface: This signal is used to calibrate the hub
interface I/O buffers.

GRCOMP

I/O

CMOS

Compensation for AGP: This signal is used to calibrate AGP buffers.

HRCOMP[1:0]

I/O

CMOS

Compensation for Host: This signal is used to calibrate the Host AGTL+ I/O
buffers.

HSWNG[1:0]

CMOS

Host Reference Voltage: Reference voltage input for the compensation logic.

SMRCOMP

I/O

CMOS

System Memory RCOMP

VCC1_5

The 1.5 V Power input pins

VCC1_8

The 1.8 V Power input pins

VCCSM

The SDRAM Power input pins. 2.5 V for DDR.

VCCA[1:0]

PLL power input pins.

VTT

The AGTL+ bus termination voltage inputs

VSS

GROUND

VSSA[1:0]

PLL

Ground

2.7.

Pin State Table

This section describes the expected states of the MCH-M I/O buffers. These tables only refer to the
contributions on the interface from the MCH-M and do NOT reflect any external influence (such as
external pullup/pulldown resistors or external drivers).

Legend :

Term H/L: Normal termination devices are turned on high/low
Pwrdn:

Power

down

H/L:

Strong Drive low

Tri/High-Z: High

Impedance

IN:

Input buffer Enabled

PU, PD/PL:

Weak internal pull-up, Weak internal pull down

(Strap):

Strap input sampled during assertion or on the deassertion edge of RSTIN#

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Table 14. Host Signals

Buffer

Type/I

Signal

Type

State

During

RSTIN#

Assertion

State After

RSTIN#

Deassertion

C3 S1M S3

S4-S5 G3

HA[31:3]#

GTL+

I/O

Term H

Pwrdn

HD[63:0]#

GTL+

I/O

Term H

Pwrdn

ADS#

GTL+

I/O

Term H

Pwrdn

BNR#

GTL+

I/O

Term H

Pwrdn

BPRI#

GTL+

Term H

Pwrdn

DBSY#

GTL+

I/O

Term H

Pwrdn

DEFER#

GTL+

Term H

Pwrdn

DRDY#

GTL+

I/O

Term H

Pwrdn

HIT#

GTL+

I/O

Term H

Pwrdn

HITM#

GTL+

I/O

Term H

Pwrdn

HLOCK# GTL+

Term

H Term

N/a N/a N/a N/a N/a

HREQ[4:0]#

GTL+

I/O

Term H

Pwrdn

HTRDY#

GTL+

I/O

Term H

Pwrdn

RS[2:0]#

GTL+

Term H

Pwrdn

CPURST#

GTL+

Drive L

Term H after 1
ms

Term

H Term

H Pwrdn Pwrdn Pwrdn

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Table 15. DDR Signals

Buffer

Type/IO

Signal

Type

State

During

RSTIN#

Assertion

State After

RSTIN#

Deassertion

C3 S1M

S4-S5

SCK#[5:0]

SM common

O TRI

DRIVE

Don't
care

Don't care

Pwrdn

SCK[4:0]

SM common

O TRI

DRIVE

Don't
care

Don't care

Pwrdn

SCK[5]

SM common

O TRI

DRIVE

L L L

Pwrdn Pwrdn

SCKE[3:0]

SM common

DRIVE L

Pwrdn Pwrdn

SDQ[63:59]

SM common

I/O PU

Hi-Z

PU or PD *

Pwrdn

SDQ[58]

SM common

I/O PU

L L L

Pwrdn Pwrdn

SDQ[57:56]

SM common

I/O PU

Hi-Z

PU or PD *

Pwrdn

SDQ[55]

SM common

I/O PU

L L L

Pwrdn Pwrdn

SDQ[54:0]

SM common

I/O PU

Hi-Z

PU or PD *

Pwrdn

SCB[7:0]

SM common

I/O PU

Hi-Z

PU or PD *

Pwrdn

SDQS[8:0]

SM common

I/O TRI

TRI

Hi-Z

PU or PD *

Pwrdn

RCVENIN#

SM common

I IN

Don't care

Pwrdn

RCVENOUT# SM

common

O TRI

Drive

H Hi

PU or PD *

Pwrdn

SBS[1:0]

SM common

O TRI

DRIVE

Hi-Z

PU or PD *

Pwrdn

SRAS#

SM common

O TRI

DRIVE

Hi-Z

PU or PD *

Pwrdn

SWE#

SM common

O TRI

DRIVE

Pwrdn Pwrdn

SCAS#

SM common

O TRI

DRIVE

Hi-Z

PU or PD *

Pwrdn

SMA[12:0]

SM common

O TRI

DRIVE

Hi-Z

PU or PD *

Pwrdn

SCS#[3:0]

SM common

O TRI

Drive

H Hi-Z

Hi-Z

PU or PD *

Pwrdn

* There is an indeterminate number of non-CKE DDR pins that will be pull-down in S3.

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Table 16. AGP Signals

Buffer

Type

Signal

Type

State

During

RSTIN#

Assertion

State After

RSTIN#

Deassertion

Pull

Up/Pull

Down

C3 S1M S3 S4-S5

PIPE# CMOS

Input

8.2K

Int

Pullup

H H Pwrdn

Pwrdn

SBA[7:0] CMOS Input PU

(Strap) PU

8.2K

Int

Pullup

H H Pwrdn

Pwrdn

RBF# CMOS

Input

(Strap)

8.2K

Int

Pullup

H H Pwrdn

Pwrdn

WBF# CMOS

Input

(Strap)

8.2K

Int

Pullup

H H Pwrdn

Pwrdn

ST[2:0]

CMOS

Output

PU (Strap)

DRIVE L

Hi-Z

Pwrdn

AD_STB0 CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

AD_STB0
#

CMOS I/O

8.2K

Int

Pulldwn

PL PL Pwrdn

Pwrdn

AD_STB1 CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

AD_STB1
#

CMOS I/O

8.2K

Int

Pulldwn

PD PD Pwrdn

Pwrdn

SB_STB CMOS I

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

SB_STB# CMOS I

8.2K

Int

Pulldwn

PD PD Pwrdn

Pwrdn

G_FRAM
E#

CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_IRDY# CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_TRDY
#

CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_STOP
#

CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_DEVS
EL#

CMOS I/O

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_REQ# CMOS Input PU

8.2K

Int

Pullup

PU PU Pwrdn

Pwrdn

G_GNT#

CMOS

Output

PU (Strap)

DRIVE H

8.2K Int
Pullup

PU PU Pwrdn

Pwrdn

G_AD[31:
0]

CMOS I/O

TRI

Hi-Z Hi-Z Pwrdn

Pwrdn Pwrdn

G_C/BE[3
:0]#

CMOS I/O

TRI

Hi-Z Hi-Z Pwrdn

Pwrdn Pwrdn

G_PAR CMOS I/O TRI

TRI

Hi-Z Hi-Z Pwrdn

Pwrdn Pwrdn

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3. Register

Description

3.1.

Conceptual Overview of the Platform Configuration

Structure

The Intel

845MP/845MZ Chipset MCH-M and ICH3-M are physically connected by hub interface A.

From a configuration standpoint, the hub interface A is PCI bus #0. As a result, all devices internal to the
MCH-M and ICH3-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically
attached to the ICH3-M and from a configuration perspective, appears to be a hierarchical PCI bus
behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the primary
PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration
standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges
resident as devices on PCI bus #0.

The MCH-M contains two PCI devices within a single physical component. The configuration registers
for the four devices are mapped as devices residing on PCI bus #0.

· Device 0: Host-hub interface Bridge/DRAM Controller. Logically this appears as a PCI device

residing on PCI bus #0. Physically Device 0 contains the standard PCI registers, DRAM registers,
the Graphics Aperture controller, and other MCH-M specific registers.

· Device 1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing on

PCI bus #0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard
AGP/PCI configuration registers (including the AGP I/O and memory address mapping).

The following table shows the Device # assignment for the various internal MCH-M devices.

Table 19. Device Number Assignment

MCH-M Function

Bus #0, Device#

DRAM Controller/8 bit HI_A Controller

Device #0

Host-to-AGP Bridge (virtual P2P)

Device #1

NOTE: A physical PCI bus #0 does not exist. The hub interface and the internal devices in the Intel

845MP/845MZ

Chipset MCH-M and ICH3-M logically constitute PCI Bus #0 to configuration software.

3.2.

Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by a
mapping mechanism implemented within the MCH-M. The PCI specification defines two mechanisms to
access configuration space, Mechanism #1 and Mechanism #2. The MCH-M supports only Mechanism
#1.

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The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register a Dword I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device,
and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31]
must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes
of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to
CONFIG_DATA will result in the MCH-M translating the CONFIG_ADDRESS into the appropriate
configuration cycle.

The MCH-M is responsible for translating and routing the CPU's I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH-M configuration registers, hub
interface, or AGP.

3.3.

Routing Configuration Accesses

The MCH-M supports two bus interfaces: the hub interface and AGP. PCI configuration cycles are
selectively routed to one of these interfaces. The MCH-M is responsible for routing PCI configuration
cycles to the proper interface. PCI configuration cycles to the ICH3-M internal devices, and Primary PCI
(including downstream devices) are routed to the ICH3-M via the hub interface. AGP configuration
cycles are routed to AGP. The AGP interface is treated as a separate PCI bus from the configuration
point of view. Routing of configuration AGP is controlled via the standard PCI-PCI bridge mechanism
using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER,
and the SUBORDINATE BUS NUMBER registers of the corresponding PCI-PCI bridge device.

A detailed description of the mechanism for translating CPU I/O bus cycles to configuration cycles on
one of the buses is described below.

3.3.1.

PCI Bus #0 Configuration Mechanism

The MCH-M decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration
cycle is targeting a PCI Bus #0 device.

· The Host-HI Bridge entity within the MCH-M is hardwired as Device #0 on PCI Bus #0.
· The Host-AGP Bridge entity within the MCH-M is hardwired as Device #1 on PCI Bus #0.

Configuration cycles to any of the MCH-M's internal devices are confined to the MCH-M and not sent
over hub interface. Accesses to disabled MCH-M internal devices will be forwarded over the hub
interface as Type0 Configuration Cycles.

3.3.2.

Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-AGP
device's SECONDARY BUS NUMBER register, or greater than the value in the Host-AGP device's
SUBORDINATE BUS NUMBER register, the MCH-M will generate a Type 1 hub interface
Configuration Cycle. The ICH3-M compares the non-zero Bus Number with the SECONDARY BUS
NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the
configuration cycle is meant for Primary PCI or a downstream PCI bus.

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3.3.3.

AGP Configuration Mechanism

From the chipset configuration perspective, AGP is seen as a PCI bus interface residing on a Secondary
Bus side of the "virtual" PCI-PCI bridges referred to as the MCH-M Host-AGP bridge. On the Primary
Bus side, the "virtual" PCI-PCI bridge is attached to PCI Bus #0. Therefore, the PRIMARY BUS
NUMBER register is hardwired to "0". The "virtual" PCI-PCI bridge entity converts Type #1 PCI Bus
Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP interface.
Type 1 configuration cycles on PCI Bus #0 that have a BUS NUMBER that matches the SECONDARY
BUS NUMBER of the MCH-M's "virtual" Host-to-PCI_B/AGP bridge will be translated into Type 0
configuration cycles on the AGP interface.

If the Bus Number is non-zero, greater than the value programmed into the SECONDARY BUS
NUMBER register, and less than or equal to the value programmed into the SUBORDINATE BUS
NUMBER register, the MCH-M will generate a Type 1 PCI configuration cycle on AGP.

3.4.

MCH-M Register Introduction

The MCH-M contains two sets of software accessible registers, accessed via the Host CPU I/O address
space:

1. Control registers I/O mapped into the CPU I/O space, which control access to PCI and AGP

configuration space (see section entitled I/O Mapped Registers).

2. Internal configuration registers residing within the MCH-M are partitioned into four logical device

register sets ("logical" since they reside within a single physical device). The first register set is
dedicated to Host-HI Bridge functionality (i.e. DRAM configuration, other chip-set operating
parameters and optional features). The second register block is dedicated to Host-AGP Bridge
functions (controls AGP interface configurations and operating parameters).

The MCH-M supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.

The MCH-M internal registers (I/O Mapped and Configuration registers) are accessible by the Host
CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the
exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric
fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).

Reserved Bits:

Some of the MCH-M registers described in this section contain reserved bits. These bits are labeled
"Reserved". Software must deal correctly with fields that are reserved. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of
reserved bit positions must first be read, merged with the new values for other bit positions and then
written back. Note the software does not need to perform read, merge, and write operation for the
configuration address register.

Reserved Registers:

In addition to reserved bits within a register, the MCH-M contains address locations in the configuration
space of the Host-HI Bridge entity that are marked either "Reserved" or "Intel Reserved". When a

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"Reserved" register location is read, a random value is returned. ("Reserved" registers can be 8-bit, 16-
bit, or 32-bit in size.) Writes to "Intel Reserved" registers may cause system failure. Reads to "Intel
Reserved" registers may return a non-zero value.

Default Value Upon Reset:

Upon a full Reset, the MCH-M sets all of its internal configuration registers to predetermined default
states. Some register values at reset are determined by external strapping options. The default state
represents the minimum functionality feature set required to successfully bring up the system. Hence, it
does not represent the optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating parameters and
optional system features that are applicable, and to program the MCH-M registers accordingly.

3.5.

I/O Mapped Registers

The MCH-M contains two registers that reside in the CPU I/O address space: the Configuration Address
(CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The
Configuration Address Register enables/disables the configuration space and determines what portion of
configuration space is visible through the Configuration Data window.

3.5.1.

CONFIG_ADDRESS Configuration Address Register

I/O Address:

0CF8h Accessed as a Dword

Default Value:

00000000h

Access: Read/Write
Size: 32

bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word
reference will "pass through" the Configuration Address Register and the hub interface, onto the PCI bus
as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function
Number, and Register Number for which a subsequent configuration access is intended.

Figure 2. Configuration Address Register

1 0

Reserved
Register Number
Function Number
Device Number
Bus Number
Reserved
Enable

Bit
Default

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Bit Descriptions

Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI configuration space are
enabled. If this bit is reset to 0, accesses to PCI configuration space are disabled.

30:24

Reserved (These bits are read only and have a value of 0).

23:16

Bus Number: When the Bus Number is programmed to 00h the target of the Configuration Cycle is a
hub interface agent (MCH-M, ICH3-M, etc.).

The Configuration Cycle is forwarded to hub interface if the Bus Number is programmed to 00h and the
MCH-M is not the target (the device number is >= 2).

If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS
NUMBER Register of device #1, a Type 0 PCI configuration cycle will be generated on AGP.

If the Bus Number is non-zero, greater than the value in the SECONDARY BUS NUMBER register of
device #1 and less than or equal to the value programmed into the SUBORDINATE BUS NUMBER
Register of device #1 a Type 1 PCI configuration cycle will be generated on AGP.

If the Bus Number is non-zero, and does not fall within the ranges enumerated by device #1's
SECONDARY BUS NUMBER or SUBORDINATE BUS NUMBER Register, then a hub interface Type 1
Configuration Cycle is generated.

15:11

Device Number: This field selects one agent on the PCI bus selected by the Bus Number. When the
Bus Number field is "00" the MCH-M decodes the Device Number field. The MCH-M is always Device
Number 0 for the Host-hub interface bridge entity and Device Number 1 for the Host-AGP entity.
Therefore, when the Bus Number =0 and the Device Number=0-1 the internal MCH-M devices are
selected.

If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS
NUMBER Register, a Type 0 PCI configuration cycle will be generated on AGP. The MCH-M will decode
the Device Number field[15:11] and assert the appropriate GAD signal as an IDSEL. For PCI-to-PCI
Bridge translation, one of the 16 IDSELs is generated. When bit [15] = 0 bits [14:11] are decoded to
assert a signal AD[31:16] IDSEL. GAD16 is asserted to access Device #0, GAD17 for Device #1 and so
forth up to Device #15 for which will assert AD31. All device numbers higher than 15 cause a type 0
configuration access with no IDSEL asserted, which will result in a Master Abort reported in the MCH-M's
"virtual" PCI-PCI bridge registers.

For Bus Numbers resulting in hub interface configuration cycles, the MCH-M propagates the device
number field as A[15:11]. For bus numbers resulting in AGP type 1 configuration cycles, the device
number is propagated as GAD[15:11].

10:8

Function Number: This field is mapped to GAD[10:8] during AGP Configuration cycles and A[10:8]
during hub interface configuration cycles. This allows the configuration registers of a particular function in
a multi-function device to be accessed. The MCH-M ignores configuration cycles to its internal Devices if
the function number is not equal to 0.

7:2

Register Number: This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to GAD[7:2]
during AGP Configuration cycles and A[7:2] during hub interface Configuration cycles.

1:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.6.1.

DRAMWIDTH--DRAM Width Register

Address Offset:

2Ch

Default Value:

00h

Access: R/W
Size: 8

bits

This register determines the width of SDRAM devices populated in each row of memory.

Bit Descriptions

7:4 Reserved.

Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices

Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices

Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices

Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices

Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify exactly

which row width field affects which clock signal.

Row Parameters

DDR Clocks Affected

0 SCK[2:0]/SCK[2:0]#

1 SCK[2:0]/SCK[2:0]#

2 SCK[5:3]/SCK[5:3]#

3 SCK[5:3]/SCK[5:3]#

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.6.3.

CKESTR Strength Control Register for CKE Signal Group

Address

Offset:

31h

Default Value:

00h

Access:

Read Only, Read/Write

Size: 8

bits

This register controls the drive strength of the I/O buffers for the CKE signal group. This group has two
possible loadings depending on the width of SDRAM devices used in each Row of memory (x8 or x16).
The proper strength can be independently programmed for each configuration. The actual strength used
for each signal is determined by the DRAM Width Register (offset 2Ch).

Bit Descriptions

Reserved

6:4

CKE x16 Strength Control: Sets drive strength as shown below
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Reserved.

2:0

CKE x8 Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.6.4.

CSBSTR Strength Control Register for CS# Signal Group

Address

Offset:

32h

Default Value:

00h

Access:

Read Only, Read/Write

Size: 8

bits

This register controls the drive strength of the I/O buffers for the CS# signal group. This group has two
possible loadings depending on the width of SDRAM devices used in each Row of memory (x8 or x16).
The proper strength can be independently programmed for each configuration. The actual strength used
for each signal is determined by the DRAM Width register (offset 2Ch).

Bit Descriptions

Reserved

6:4

CS# x16 Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Reserved

2:0

CS# x8 Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.6.5.

CKSTR Strength Control Register for CK Signal Group (CK /

CK#)

Address

Offset:

33h

Default Value:

00h

Access:

Read Only, Read/Write

Size: 8

bits

This register controls the drive strength of the I/O buffers for the CK signal group, which includes both
the CK and CK# signals. This group has two possible loadings depending on the width of SDRAM
devices used in each Row of memory (x8 or x16). The proper strength can be independently programmed
for each configuration. The actual strength used for each signal is determined by the DRAM Width
register (offset 2Ch).

Bit Descriptions

Reserved

6:4

CK x16 Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Reserved

2:0

CK x8 Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.6.6.

RCVENSTR Strength Control Register for RCVENOUT#

Signals

Address

Offset:

34h

Default Value:

00h

Access:

Read Only, Read/Write

Size: 8

bits

This register controls the drive strength of the I/O buffers for the Receive Enable Out (RCVENOUT#)
signal.

Bit Descriptions

7:3

Reserved

2:0

RCVEnOut# Strength Control: Sets drive strength as shown below:
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X

3.7.

Host-Hub Interface Bridge Device Registers Device

Table 20 shows the access attributes for the configuration space. An "s" in the Default Value field means
that a strap determines the power-up default value for that bit. Table 21 below summarizes the MCH-M
configuration space for Device #0.

Table 20. Nomenclature for Access Attributes

RO Read

Only. If a register is read only, writes to this register have no effect.

R/W Read/Write. A register with this attribute can be read and written.

R/W/L Read/Write/Lock

A register with this attribute can be read, written, and Lock.

R/WC Read/Write

Clear. A register bit with this attribute can be read and written. However, a write of a 1

clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

R/WO Read/Write

Once. A register bit with this attribute can be written to only once after power up. After the

first write, the bit becomes read only.

L Lock. A register bit with this attribute becomes Read Only after a lock bit is set.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

Table 21. MCH-M Configuration Space for Device #0

Address

Offset

Register

Symbol

Register Name

Default

Value

Access

00-01h VID

Vendor

Identification

8086h RO

02-03h DID

Device

Identification

1A30h RO

04-05h

PCICMD

PCI Command Register

0006h

RO, R/W

06-07h

PCISTS

PCI Status Register

0090h

RO, R/WC

08h RID

Revision

Identification

Dependent

silicon

revision

09h

Reserved.

0Ah SUBC

Sub-Class

Code

00h RO

0Bh

BCC

Base Class Code

06h

0Dh MLT

Master

Latency

Timer

00h RO

0Eh HDR

Header

Type

00h RO

0Fh

Reserved.

10-13h

APBASE

Aperture Base Configuration

00000008h

RO, R/W

14-2Bh

Reserved.

2C-2Dh SVID

Subsystem

Vendor

Identification

0000h R/WO

2E-2Fh SID

Subsystem

Identification

0000h R/WO

30-33h

Reserved.

34h CAPPTR

Capabilities

Pointer

A0h

35-50h

Reserved.

51h

AGPM

AGP Miscellaneous Config

00h

52-5Fh Reserved.

60-67h

DRB[0:7]

DRAM Row Boundary Registers

00h

R/W

68-6Fh

Reserved.

70-73h

DRA[0:7]

DRAM Row Attribute Registers

00h

R/W

73-77h

Reserved.

78-7Bh

DRT

DRAM Timing Register

00000010h

R/W

7C-7Fh

DRC

DRAM Controller Mode Register

0000h

R/W, RO

80-85h

Reserved.

86h

DERRSYN

DRAM Error Syndrome Register

00h

87-8Bh

Reserved.

8C-8Fh

EAP

Error Address Pointer Register

00000000h

90-96h

PAM[0:6]

Programmable Attribute Map Registers

00000000000

000h

RO, R/W

97h

FDHC

Fixed DRAM Hole Control Register

00h

RO, R/W

98-9Ch

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Address

Offset

Register

Symbol

Register Name

Default

Value

Access

9Dh

SMRAM

System Management RAM Control Register

02h

RO, R/W

9Eh

ESMRAMC

Extended System Mgmt RAM Control Register

38h

RO, R/W,

RWC

9Fh

Reserved

A0-A3h ACAPID

AGP

Capability

Identifier

00200002h RO

A4-A7h AGPSTAT

AGP

Status

1F000217h RO

A8-Abh

AGPCMD

AGP Command Register

00000000h

RO, R/W

AC-Afh

Reserved

B0-B3h

AGPCTRL

AGP Control Register

00000000h

RO, R/W

B4h

APSIZE

Aperture Size

00h

RO, R/W

B5-B7h

Reserved

B8-BBh

ATTBASE

Aperture Translation Table Base Register

00000000h

RO, R/W

BCh

AMTT

AGP MTT Control Register

00h

RO, R/W

BDh

LPTT

AGP Low Priority Transaction Timer Register

00h

RO, R/W

BE-C3h

Reserved

C4-C5h

TOM

Top of Low Memory Register

0000h

R/W

C6-C7h

MCHCFG

MCH-M Configuration Register

0000h

RO, R/W

C8-C9h

ERRSTS

Error Status Register

0000h

RO, R/W

CA-CBh

ERRCMD

Error Command Register

0000h

RO, R/W

CC-CDh

SMICMD

SMI Command Register

0000h

RO, R/W

CE-CFh

SCICMD

SCI Command Register

0000h

RO, R/W

D0-DDh

Reserved

DE-DFh

SKPD

Scratchpad Data Register

0000h

RO, R/W

E0-E3h

Reserved

E4-E7h

CAPID

Product Specific Capability ID

F104A009h

E8-FFh

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.3.

PCICMD PCI Command Register Device #0

Address Offset:

04-05h

Default: 0006h
Access:

Read/Write, Read Only

Size 16

bits

Since MCH-M Device #0 does not physically reside on PCI0 many of the bits are not implemented

Bit Descriptions

15:10

Reserved

Fast Back-to-Back Enable (RO). This bit controls whether or not the master can do fast back-to-
back writes to different targets. Since device #0 is strictly a target this bit is not implemented and is
hardwired to 0. Writes to this bit position have no effect.

SERR Enable (SERRE) (R/W). This bit is a global enable bit for Device #0 SERR messaging. The
MCH-M does not have an SERR# signal. The MCH-M communicates the SERR# condition by
sending an SERR message to the ICH3-M. If this bit is set to a 1, the MCH-M is enabled to generate
SERR messages over hub interface for specific Device #0 error conditions that are individually
enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers.
If SERRE is reset to 0, then the SERR message is not generated by the MCH-M for Device #0.

NOTE: This bit only controls SERR message for the Device #0. Device 1 has its own SERRE bits to
control error reporting for error conditions occurring on their respective devices.

Address/Data Stepping (RO). Address/data stepping is not implemented in the MCH-M, and this bit
is hardwired to 0. Writes to this bit position have no effect.

Parity Error Enable (PERRE) (R/W). PERR# is not implemented by the MCH-M, and this bit is
hardwired to 0. Writes to this bit position have no effect.

VGA Palette Snoop (RO). The MCH-M does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.

Memory Write and Invalidate Enable(MWIE) (RO). The MCH-M does not implement this bit and it
is hardwired to a 0. Writes to this bit position have no effect.

Special Cycle Enable(SCE) (RO). The MCH-M does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.

Bus Master Enable (BME) (RO). The MCH-M is always enabled as a master on hub interface A.
This bit is hardwired to a "1". Writes to this bit position have no effect.

Memory Access Enable (MAE) (RO). The MCH-M always allows access to main memory. This bit
is not implemented and is hardwired to 1. Writes to this bit position have no effect.

I/O Access Enable (IOAE) (RO). This bit is not implemented in the MCH-M and is hardwired to a 0.
Writes to this bit position have no effect.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.4.

PCISTS PCI Status Register Device #0

Address Offset:

06-07h

Default Value:

0090h

Access:

Read Only, Read/Write Clear

Size: 16

bits

PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's on the hub
interface. Since MCH-M Device #0 is the host-to-hub interface A bridge, many of the bits are not
implemented.

Bit

Description

Reserved

Signaled System Error (SSE) (R/WC). This bit is set to 1 when MCH-M Device #0 generates an
SERR message over hub interface for any enabled Device #0 error condition. Device #0 error
conditions are enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset
from the PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit.

Received Master Abort Status (RMAS) (R/WC). This bit is set when the MCH-M generates a hub
interface request that receives a Master Abort completion packet or Master Abort Special Cycle.
Software clears this bit by writing a 1 to it.

Received Target Abort Status (RTAS) (R/WC). This bit is set when the MCH-M generates a hub
interface request that receives a Target Abort completion packet or Target Abort Special Cycle.
Software clears this bit by writing a 1 to it.

Signaled Target Abort Status (STAS) (RO). The MCH-M will not generate a Target Abort hub
interface completion packet or Special Cycle. This bit is not implemented in the MCH-M and is
hardwired to a 0. Writes to this bit position have no effect.

10:9

DEVSEL Timing (DEVT). Hub interface does not comprehend DEVSEL# protocol. These bits are
hardwired to "00". Writes to these bit positions have no effect.

Master Data Parity Error Detected (DPD) (RO). PERR signaling and messaging are not
implemented by the MCH-M therefore this bit is hardwired to 0. Writes to this bit position have no
effect.

Fast Back-to-Back Capable (FB2B). This bit is hardwired to 1. Writes to this bit position have no
effect.

6:5

Reserved

Capability List (CLIST) (RO). This bit is set to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the
start address within configuration space of this device where the AGP Capability standard register
resides.

3:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.5.

RID Revision Identification Register Device #0

Address Offset:

08h

Default Value:

00h

Access: Read

Only

Size: 8

bits

This register contains the revision number of the MCH-M Device #0. These bits are read only and writes
to this register have no effect.

Bit Description

7:0

Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for the MCH-M Device #0.

For the B-1 Stepping, this value is 05h.

3.7.6.

SUBC Sub-Class Code Register Device #0

Address Offset:

0Ah

Default Value:

00h

Access: Read

Only

Size: 8

bits

This register contains the Sub-Class Code for the MCH-M Device #0. This code is 00h indicating a Host
Bridge device. The register is read only.

Bit Description

7:0

Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the
MCH-M falls. The code is 00h indicating a Host Bridge.

3.7.7.

BCC Base Class Code Register Device #0

Address Offset:

0Bh

Default Value:

06h

Access: Read

Only

Size: 8

bits

This register contains the Base Class Code of the MCH-M Device #0. This code is 06h indicating a
Bridge device. This register is read only.

Bit Description

7:0

Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH-
M. This code has the value 06h, indicating a Bridge device.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.10.

APBASE Aperture Base Configuration Register Device #0

Offset: 10-13h
Default: 0000_0008h
Access:

Read/Write, Read Only

Size: 32

bits

The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration register
such that only a fixed amount of space can be requested (dependent on which bits are hardwired to "0" or
behave as hardwired to "0"). To allow for flexibility (of the aperture), an additional register called
APSIZE is used as a "back-end" register to control which bits of the APBASE will behave as hardwired
to "0". This register will be programmed by the MCH-M specific BIOS code that will run before any of
the generic configuration software is run.

Note: Bit 9 of the MCH-MCFG register is used to prevent accesses to the aperture range before this register is

initialized by the configuration software and the appropriate translation table structure has been
established in the main memory.

Bit Description

31:28

Upper Programmable Base Address (R/W). These bits are part of the aperture base set by
configuration software to locate the base address of the graphics aperture. They correspond to bits
[31:28] of the base address in the CPU's address space that will cause a graphics aperture
translation to be inserted into the path of any memory read or write.

Default = 0000

27:22

Middle "Hardwired"/Programmable Base Address: These bits are part of the aperture base set
by configuration software to locate the base address of the graphics aperture. They correspond to
bits [27:4] of the base address in the CPU's address space that will cause a graphics aperture
translation to be inserted into the path of any memory read or write. These bits can behave as
though they were hardwired to "0" if programmed to do so by the APSIZE bits of the APSIZE register.
This will cause configuration software to understand that the granularity of the graphics aperture base
address is either finer or coarser, depending upon the bits set by MCH-M-specific configuration
software in APSIZE.

21:4

Lower "Hardwired": This forces minimum aperture size selected by this register to be 4MB.

Prefetchable (RO). This bit is hardwired to "1" to identify the Graphics Aperture range as
prefetchable as per the PCI Specification for the base address registers.

There are no side effects on reads, the device returns all bytes on reads regardless of the byte
enables, and the MCH-M may merge processor writes into this range without causing errors.

2:1

Type (RO). These bits determine addressing type and they are hardwired to "00" to indicate that
address range defined by the upper bits of this register can be located anywhere in the 32-bit address
space.

Memory Space Indicator (RO). Hardwired to "0" to identify aperture range as a memory range.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.11.

SVID Subsystem Vendor ID Device #0

Offset: 2C-2Dh
Default: 0000h
Access: Read/Write

Once

Size: 16

bits

This value is used to identify the vendor of the subsystem.

Bit Description

15:0

Subsystem Vendor ID (R/WO). The default value is 00h. This field should be programmed during
boot-up. After this field is written once, it becomes read only.

3.7.12.

SID Subsystem ID Device #0

Offset: 2E-2Fh
Default: 0000h
Access: Read/Write

Once

Size: 16

bits

This value is used to identify a particular subsystem.

Bit Description

15:0

Subsystem ID (R/WO). The default value is 00h. This field should be programmed during boot-up.
After this field is written once, it becomes read only.

3.7.13.

CAPPTR Capabilities Pointer Device #0

Offset: 34h
Default: E4h

Access: Read

Only

Size: 8

bits

The CAPPTR provides the offset that is the pointer to the location where the AGP standard registers are
located.

Bit Description

7:0

Pointer to the start of AGP standard register block. This pointer tells software where it can find
the beginning of the AGP register block. The value in this field is E4h.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.14.

AGPM- AGP Miscellaneous Configuration

Offset: 51h
Default: 00h

Access: Read/Write
Size: 8

bits

Bit Description

7:2

Reserved

Aperture Access Global Enable (APEN): This bit is used to prevent access to the graphics aperture
from any port (CPU, HI_A, or AGP/PCI_B) before the aperture range is established by the
configuration software and the appropriate translation table in the main DRAM has been initialized.
The default value is "0", so this field must be set after system is fully configured in order to enable
aperture accesses.

Reserved

3.7.15.

DRB[0:7] DRAM Row Boundary Registers Device #0

Offset: 60-6

Default: 00h

Access: Read/Write
Size: 8

bits

The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM rows
with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1
in DRB0 indicates that 32 MB of DRAM has been populated in the first row.
Row0: 60h
Row1: 61h
Row2: 62h

Row3: 63h
Row4: 64h

Row5: 65h

Row6: 66h

Row7: 67h

DRB0 = Total memory in row0 (in 32MB increments)
DRB1 = Total memory in row0 + row1 (in 32MB increments)
----
DRB3 = Total memory in row0 + row1 + row2 + row3 (in 32MB increments)

** When in DDR mode DRB[4:7] must be programmed with value contained in DRB3.

Each Row is represented by a byte. Each byte has the following format.

Bit Description

7:0

DRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
DRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.16.

DRA[0:7] DRAM Row Attribute Registers Device #0

Offset: 70-73h
Default: 00h

Access: Read/Write
Size: 8

bits

The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of
rows. Each nibble of information in the DRA registers describes the page size of a pair of rows:

Row0, 1: 70h
Row2, 3: 71h
Row4, 5: 72h (Not Used; see note)
Row6, 7: 73h (Not Used; see note)

Note: Must contain default value of 00h

7 6

2 0

Row attribute for Row1

Row Attribute for Row0

7 6

2 0

Row attribute for Row3

Row Attribute for Row2

7 6

2 0

Row attribute for Row5

Row Attribute for Row4

2 0

Rsv Row attribute for Row7

Rsv Row Attribute for Row6

Bit Description

Reserved

6:4

Row Attribute for odd-numbered row: This 3-bit field defines the page size of the corresponding
row.

001: 2 KB
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved

Reserved

2:0

Row Attribute for even-numbered row: This 3-bit field defines the page size of the corresponding
row.

001: 2 KB
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.17.

DRT DRAM Timing Register Device #0

Offset: 78-7Bh
Default: 00000010h

Access: Read/Write
Size: 32

bits

Bit Description

31:19

Reserved

18:16

DRAM Idle Timer: This field determines the number of clocks the DRAM controller will remain in the
idle state before it begins precharging all pages.

000 Infinite
001 0
010 8 DRAM clocks
011 16 DRAM clocks
100 64 DRAM clocks
Others: reserved

15:11

Reserved

10:9

Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS.
00 7 Clocks
01 6 Clocks
10 5 Clocks
11 Reserved

8:6

Reserved

5:4

CAS# Latency (tCL). This bit controls the number of DRAM Clocks between when a read command
is sampled by the SDRAMs and when the MCH-M samples read data from the SDRAMs.

00: 2.5
01: 2 Clocks
10: Reserved
11: Reserved

Reserved

DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
Encoding tRCD
0: 3 DRAM Clocks (Default)
1: 2 DRAM Clocks

Reserved

DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
Encoding tRP
0: 3 DRAM Clocks(Default)
1: 2 DRAM Clocks

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.18.

DRC DRAM Controller Mode Register Device #0

Offset: 7C-7Fh
Default: 00000000h

Access: Read/Write
Size: 32

bits

Bit Description

31:30

Revision Number (REV): Reflects the revision number of the format used for DDR register
definition. Currently, this field must be "00", since this (rev "00") is the only existing version of the
specification.

Initialization Complete (IC): This bit is used for communication of software state between the
memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory
array is complete.

Dynamic Power-down mode Enable: When set, the DRAM controller will put pair of rows into
power down mode when all banks are pre-charged (closed). Once a bank is accessed, the relevant
pair of rows is taken out of Power Down mode.

The entry into power down mode is performed by de-activation of CKE. The exit is performed by
activation of CKE.

0: DRAM Power-down disabled
1: DRAM Power-down enabled

27:24

Active DDR Rows: Implementations may use this field to limit the maximum number of DDR rows
that may be active at once.

0000 All rows allowed to be in the active state
Others: Reserved.

23:22

Reserved

21:20

DRAM Data Integrity Mode (DDIM): These bits select one of 4 DRAM data integrity modes.
DDIM Operation
00 Non-ECC mode
10 Error checking with correction.
Other Reserved

19:11

Reserved

10:8

Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what
rate refreshes will be executed.

000: Refresh disabled
001: Refresh enabled. Refresh interval 15.6 µSec
010: Refresh enabled. Refresh interval 7.8 µsec
011: Refresh enabled. Refresh interval 64 µsec
111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other: Reserved

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Bit Description

6:4

Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The
special modes are intended for initialization at power up.

000: Post Reset state When the MCH-M exits reset (power-up or otherwise), the mode select field
is cleared to "000".

During any reset sequence, while power is applied and reset is active, the MCH-M asserts all CKE
signals. After internal reset is de-asserted, CKE signals remain de-asserted until this field is written to
a value different than "000". On this event, all CKE signals are asserted.

During suspend, MCH-M internal signal triggers DRAM controller to flush pending commands and
enter all rows into Self-Refresh mode. As part of resume sequence, MCH-M will be reset which will
clear this bit field to "000" and maintain CKE signals de-asserted. After internal reset is de-asserted,
CKE signals remain de-asserted until this field is written to a value different than "000". On this event,
all CKE signals are asserted.

During entry to other low power states (C3, S1M), MCH-M internal signal triggers DRAM controller to
flush pending commands and enter all rows into Self-Refresh mode. During exit to normal mode,
MCH-M signal triggers DRAM controller to exit Self-Refresh and resume normal operation without
S/W involvement.

001: NOP Command Enable All CPU cycles to DRAM result in a NOP command on the DRAM
interface.

010: All Banks Pre-charge Enable All CPU cycles to DRAM result in an "all banks precharge"
command on the DRAM interface.

011: Mode Register Set Enable All CPU cycles to DRAM result in a "mode register" set command
on the DRAM interface. Host address lines are mapped to memory address lines in order to specify
the command sent. Host address lines [15:3] are mapped to MA[12:0].

100: Extended Mode Register Set Enable All processor cycles to SDRAM result in an "extended
mode register set" command on the DRAM interface (DDR only). Host address lines are mapped to
DDR address lines in order to specify the command sent. Host address lines [15:3] are mapped to
MA[12:0].

101: Reserved

110: CBR Refresh Enable In this mode all CPU cycles to DRAM result in a CBR cycle on the DDR
interface

111: Normal operation

3:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.19.

DERRSYN DRAM Error Syndrome Register

Address Offset:

86h

Default Value:

00hb

Access: Read

Only

Size: 8

bits

This register is used to report the ECC syndromes for each quadword of a 32-Byte aligned data quantity
read from the DRAM array.

Bit Description

7:0

DRAM ECC Syndrome (DECCSYN) (RO): After a DRAM ECC error, hardware loads this field with
a syndrome that describes the set of bits found to be in error.

Note: that this field is locked from the time that it is loaded up to the time when the error flag is
cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple
bit error will overwrite this field. In all other cases, an error that occurs after the first error and
before the error flag has been cleared by software will escape recording.

3.7.20.

EAP Error Address Pointer Register Device #0

Address Offset:

8C-8Fh

Default Value:

0000_0000h

Access: Read

Only

Size: 32

bits

This register stores the DRAM address when an ECC error occurs.

Bit Description

31:30

Reserved

29:1

Error Address Pointer (EAP): This field is used to store the 4-KB block of main memory of which
an error (single bit or multi-bit error) has occurred.

Note: that the value of this bit field represents the address of the first single or the first multiple bit
error occurrence after the error flag bits in the ERRSTS register have been cleared by software. A
multiple bit error will overwrite a single bit error. Once the error flag bits are set as a result of an error,
this bit field is locked and doesn't change as a result of a new error.

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.21.

PAM[0:6] Programmable Attribute Map Registers Device #0

Address Offset:

90-96h

Default Value:

00h

Attribute:

Read/Write, Read Only

Size: 8

bits

The MCH-M allows programmable memory attributes on 13 Legacy memory segments of various sizes
in the 640 Kbytes to 1 Mbytes address range. Seven Programmable Attribute Map (PAM) Registers are
used to support these features. Cacheability of these areas is controlled via the MTRR registers in the
processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to
host initiator only access to the PAM areas. MCH-M will forward to main memory for any A.G.P., PCI,
or hub interface A initiated accesses to the PAM areas. These attributes are:

RE -

Read Enable. When RE = 1, the host read accesses to the corresponding memory segment

are claimed by the MCH-M and directed to main memory. Conversely, when RE = 0, the host read
accesses are directed to PCI0.

WE -

Write Enable. When WE = 1, the host write accesses to the corresponding memory segment

are claimed by the MCH-M and directed to main memory. Conversely, when WE = 0, the host write
accesses are directed to PCI0.

The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.

Each PAM Register controls two regions, typically 16 Kbytes in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and are defined in the following
table.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

Table 22. Control Signals for Various Memory Segments

Bits [7, 3]

Reserved

Bits [6, 2]

Reserved

Bits [5, 1]

Bits [4, 0]

Description

X x 0 0

Disabled. DRAM is disabled and all accesses are
directed to the hub interface A. The MCH-M does not
respond as a PCI target for any read or write access to
this area.

X x 0 1

Read Only. Reads are forwarded to DRAM and writes
are forwarded to the hub interface A for termination.
This write protects the corresponding memory
segment. The MCH-M will respond as an AGP or the
hub interface A target for read accesses but not for
any write accesses.

X x 1 0

Write Only. Writes are forwarded to DRAM and reads
are forwarded to the hub interface for termination. The
MCH-M will respond as an AGP or hub interface A
target for write accesses but not for any read
accesses.

X x 1 1

Read/Write. This is the normal operating mode of
main memory. Both read and write cycles from the
host are claimed by the MCH-M and forwarded to
DRAM. The MCH-M will respond as an AGP or the
hub interface A target for both read and write
accesses.

At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable.

As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is
shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the
attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read
of that address. This read is forwarded to the expansion bus. The host then does a write of the same
address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory
area are set to read only so that all writes are forwarded to the expansion bus. Figure 4 and Table 23
show the PAM registers and the associated attribute bits:

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

Table 23. PAM Register Details

PAM Reg

Attribute Bits

Offset

PAM0[3:0]

Reserved

Memory Segment

Comments

90h

PAM0[7:4]

R WE 90h 0F0000h

0FFFFFh BIOS

Area

90h

PAM1[3:0]

91h

0C0000h - 0C3FFFh

ISA Add-on BIOS

91h

PAM1[7:4]

91h

0C4000h - 0C7FFFh

ISA Add-on BIOS

91h

PAM2[3:0]

92h

0C8000h - 0CBFFFh

ISA Add-on BIOS

92h

PAM2[7:4]

92h

0CC000h- 0CFFFFh

ISA Add-on BIOS

92h

PAM3[3:0]

93h

0D0000h- 0D3FFFh

ISA Add-on BIOS

93h

PAM3[7:4]

93h

0D4000h- 0D7FFFh

ISA Add-on BIOS

93h

PAM4[3:0]

94h

0D8000h- 0DBFFFh

ISA Add-on BIOS

94h

PAM4[7:4]

94h

0DC000h- 0DFFFFh

ISA Add-on BIOS

94h

PAM5[3:0]

95h

0E0000h- 0E3FFFh

BIOS Extension

95h

PAM5[7:4]

95h

0E4000h- 0E7FFFh

BIOS Extension

95h

PAM6[3:0]

96h

0E8000h- 0EBFFFh

BIOS Extension

96h

PAM6[7:4]

R WE 96h 0EC000h-

0EFFFFh BIOS

Extension

96h

For details on overall system address mapping scheme see the Address Decoding Section of this
document.

DOS Application Area (00000h-9FFFh)

The DOS area is 640 KB in size and it is further divided into two parts. The 512-KB area at 0 to 7FFFFh
is always mapped to the main memory controlled by the MCH-M, while the 128-KB address range from
080000 to 09FFFFh can be mapped to PCI0 or to main DRAM. By default this range is mapped to main
memory and can be declared as a main memory hole (accesses forwarded to PCI0) via MCH-M FDHC
configuration register.

Video Buffer Area (A0000h-BFFFFh)

Attribute bits do not control this 128-KB area. The host -initiated cycles in this region are always
forwarded to either PCI0 or AGP unless this range is accessed in SMM mode. Routing of accesses is
controlled by the Legacy VGA control mechanism of the "virtual" PCI-PCI bridge device
embedded within the MCH-M.

This area can be programmed as SMM area via a special configuration register. When used as SMM
space this range cannot be accessed from the hub interface or AGP.

Expansion Area (C0000h-DFFFFh)

This 128-KB area is divided into eight 16-KB segments, which can be assigned with different attributes
via PAM control register as defined by above.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

Extended System BIOS Area (E0000h-EFFFFh)

This 64-Kbytes area is divided into four 16-Kbytes segments which can be assigned with different
attributes via PAM control register as defined by the table above.

System BIOS Area (F0000h-FFFFFh)

This area is a single 64-Kbytes segment, which can be assigned with different attributes via PAM control
register as defined by the table above.

3.7.22.

FDHC Fixed DRAM Hole Control Register Device #0

Address Offset:

97h

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

This 8-bit register controls a fixed DRAM hole: 15 MB-16 MB.

Bit Description

Hole Enable (HEN). This field enables a memory hole in DRAM space. Host cycles matching an
enabled hole are passed on to ICH3-M through the hub interface. The hub interface cycles matching
an enabled hole will be ignored by the MCH-M. Note that a selected hole is not re-mapped.

Disabled. No hole

15 M-16 M (1 MB Hole)

6:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.23.

SMRAM System Management RAM Control Register Device

Address Offset:

9Dh

Default Value:

02h

Access:

Read/Write, Read Only, Lock

Size: 8

bits

The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated.
The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit
must be reset before the LOCK bit is set.

Bit Description

Reserved

SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made
visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK
is set to a 1, D_OPEN is reset to 0 and becomes read only.

SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space DRAM. This
will allow SMM software to reference "through" SMM space to update the display even when SMM is
mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at
the same time.

Note that the D_CLS bit only applies to Compatible SMM space.

SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,
D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become "Read Only". D_LCK
can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The
combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the
future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if
the program has knowledge of the D_OPEN function.

Global SMRAM Enable (G_SMRAME). If set to a 1, then Compatible SMRAM functions is enabled,
providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit has to be set to 1.

Once D_LCK is set, this bit becomes read only.

2:0

Compatible SMM Space Base Segment (C_BASE_SEG) (RO). This field indicates the location of
SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to
access SMM space, otherwise the access is forwarded to the hub interface. C_BASE_SEG is
hardwired to 010 to indicate that the MCH-M supports the SMM space at A0000h-BFFFFh.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.24.

ESMRAMC Extended System Mgmt RAM Control Register 

Device #0

Address Offset:

9Eh

Default Value:

38h

Access:

Read Only, Read/Write, Read/Write Clear, Lock

Size: 8

bits

The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1
MByte.

Bit Description

H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e. above 1 MByte or
below 1 MByte) When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses from FEDA_0000h to FEDB_FFFFh are remapped to
DRAM address 000A0000h to 000BFFFFh.

Once D_LCK is set, this bit becomes read only.

E_SMRAM_ERR (E_SMERR): This bit is set when host accesses the defined memory ranges in
Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit =
0. It is software's responsibility to clear this bit. The software must write a 1 to this bit to clear it

SMRAM_Cache (SM_CACHE): This bit is hardwired to `1'.

SMRAM_L1_EN (SM_L1): This bit is hardwired to `1'.

SMRAM_L2_EN (SM_L2): This bit is hardwired to `1'.

2:1

TSEG_SZ[1-0] (T_SZ): Selects the size of the TSEG memory block if enabled. This memory is
taken from the top of DRAM space (i.e. TOM - TSEG_SZ), which is no longer claimed by the memory
controller (all accesses to this space are sent to the hub interface if TSEG_EN is set). This field
decodes as follows:

TSEG_SZ[1,0] Description

(TOM-128K) to TOM

(TOM-256K)

TOM

(TOM-512K)

TOM

(TOM-1M) to TOM (845MP Only)

Once D_LCK is set, this bit becomes read only.

TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 128 Kbytes, 256 Kbytes, 512 Kbytes or 1
Mbytes of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and
TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space.

Once D_LCK is set, this bit becomes read only.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.25.

ACAPID AGP Capability Identifier Register Device #0

Address Offset:

A0-A3h

Default Value:

0020_0002h

Access: Read

Only

Size: 32

bits

This register provides standard identifier for AGP capability.

Bit Description

31:24

Reserved.

23:20

Major AGP Revision Number (MAJREV): These bits provide a major revision number of AGP
specification to which this version of MCH-M conforms. This field is hardwired to value of "0010b" (i.e.
implying Rev 2.x).

19:16

Minor AGP Revision Number (MINREV): These bits provide a minor revision number of AGP
specification to which this version of MCH-M conforms. This number is hardwired to value of "0000"
(i.e. implying Rev x.0)

Together with major revision number, this field identifies MCH-M as an AGP REV 2.0 compliant
device.

15:8

Next Capability Pointer (NCAPTR): AGP capability is the first and the last capability described via
the capability pointer mechanism and therefore these bits are hardwired to "0" to indicate the end of
the capability linked list.

7:0

AGP Capability ID (CAPID): This field identifies the linked list item as containing AGP registers. This
field has a value of 0000_0010b assigned by the PCI SIG.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.26.

AGPSTAT AGP Status Register Device #0

Address Offset:

A4-A7h

Default Value:

1F00_0217h

Access: Read

Only

Size: 32

bits

This register reports AGP device capability/status.

Bit Description

31:24

Request Queue (RQ): This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP
command requests can be handled by the MCH-M. This field contains the maximum number of AGP
command requests the MCH-M is configured to manage.

Default =1Fh to allow a maximum of 32 outstanding AGP command requests.

23:10

Reserved

Side Band Addressing Support (SBA): This bit indicates that the MCH-M supports side band
addressing. It is hardwired to 1.

8:6

Reserved

Greater that 4 GB Support (4GB): This bit indicates that the MCH-M does not support addresses
greater than 4 gigabytes. It is hardwired to 0.

Fast Write Support (FW): This bit indicates that the MCH-M supports Fast Writes from the host to
the AGP master. It is hardwired to a 1.

Reserved

2:0

Data Rate Support (RATE): After reset the MCH-M reports its data transfer rate capability. Bit 0
identifies if MCH-M supports 1x data transfer mode, bit 1 identifies if MCH-M supports 2x data
transfer mode, and bit 2 identifies if MCH-M supports 4x data transfer mode. 1x, 2x, and 4x data
transfer modes are supported by the MCH-M and therefore this bit field has a Default Value = 111.

Note that the selected data transfer mode applies to both AD bus and SBA bus. It also applies to Fast
Writes if they are enabled.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.27.

AGPCMD AGP Command Register Device #0

Address Offset:

A8-ABh

Default Value:

0000_0000h

Access:

Read/Write, Read Only

Size: 32

bits

This register provides control of the AGP operational parameters.

Bit Description

31:10

Reserved

SBA Enable (SBAEN): When this bit is set to 1, the side band addressing mechanism is enabled.

AGP Enable (AGPEN): When this bit is reset to 0, the MCH-M will ignore all AGP operations,
including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even if
this bit is subsequently reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of
an SBA command being delivered in 1X mode the command will be issued.

0 = MCH-M will ignore all AGP operations, including the sideband strobe sync cycle.

1 = MCH-M will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if
the AGP Side Band Enable bit is also set to 1.

7:5

Reserved

FW Enable (FWEN): When this bit is set, the MCH-M will use the Fast Write protocol for Memory
Write transactions from the MCH-M to the AGP master. Fast Writes will occur at the data transfer
rate selected by the data rate bits (2:0) in this register. When this bit is cleared, or when the data rate
bits are set to 1x mode, the Memory Write transactions from the MCH-M to the AGP master use
standard PCI protocol.

Reserved

2:0

Data Rate (DRATE): The settings of these bits determine the AGP data transfer rate. One (and only
one) bit in this field must be set to indicate the desired data transfer rate.

Encoding Description

0 0 1

1x transfer mode

0 1 0

2x transfer mode

1 0 0

4x transfer mode

Configuration software will update this field by setting only one bit that corresponds to the capability of
AGP master (after that capability has been verified by accessing the same functional register within
the AGP masters' configuration space.)

NOTE: This field applies to G_AD and SBA buses. It also applies to Fast Writes if they are enabled.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.29.

APSIZE Aperture Size Device #0

Address Offset:

B4h

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

This register determines the effective size of the Graphics Aperture used for a particular MCH-M
configuration. This register can be updated by the MCH-M specific BIOS configuration sequence before
the PCI standard bus enumeration sequence takes place. If the register is not updated then a default value
will select an aperture of maximum size (i.e. 256 MB). The size of the table that will correspond to a
256-MB aperture is not practical for most applications and therefore, these bits must be programmed to a
smaller practical value that will force adequate address range to be requested via APBASE register from
the PCI configuration software.

Bit Description

7:6

Reserved

5:0

Graphics Aperture Size (APSIZE) (R/W): Each bit in APSIZE[5:0] operates on similarly ordered bits
in APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is "0"
it forces the similarly ordered bit in APBASE[27:22] to behave as "hardwired" to 0. When a particular
bit of this field is set to "1" it allows the corresponding bit of the APBASE[27:22] field to be read/write
accessible. Only the following combinations are allowed:

5 4 3 2 1 0

Aperture Size

1 1 1 1 1 1

4 MB

1 1 1 1 1 0

8 MB

1 1 1 1 0 0

16 MB

1 1 1 0 0 0

32 MB

1 1 0 0 0 0

64 MB

1 0 0 0 0 0

128 MB

0 0 0 0 0 0

256 MB

Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e. all bits respond as
"hardwired" to 0). This provides maximum aperture size of 256 MB. As another example,
programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling
APBASE[27:25] as read/write.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.30.

ATTBASE Aperture Translation Table Base Register Device

Address Offset:

B8-BBh

Default Value:

0000_0000h

Access:

Read/Write, Read Only

Size: 32

bits

This register provides the starting address of the Graphics Aperture Translation Table Base located in the
main DRAM. This value is used by the MCH-M Graphics Aperture address translation logic (including
the GTLB logic) to obtain the appropriate address translation entry required during the translation of the
aperture address into a corresponding physical DRAM address. The ATTBASE register may be
dynamically changed.

Note: The address provided via ATTBASE is 4-KB aligned

Bit Description

31:12

Aperture Translation Table Base (TTABLE): This field contains a pointer to the base of the
translation table used to map memory space addresses in the aperture range to addresses in main
memory.

NOTE: It should be modified only when the GTLB has been disabled.

11:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.31.

AMTT AGP Interface Multi-Transaction Timer Register 

Device #0

Address Offset:

BCh

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

AMTT is an 8-bit register that controls the amount of time that the MCH-M arbiter allows an AGP
master to perform multiple back-to-back transactions. The MCH-M AMTT mechanism is used to
optimize the performance of an AGP master (using PCI protocol operations) that performs multiple
back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst
transfers). The AMTT mechanism applies to the host-AGP transactions as well and it guarantees to the
processor a fair share of the AGP interface bandwidth.

The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66-
MHz clocks) allotted to the current agent (either AGP master or Host bridge) after which the AGP arbiter
may grant the bus to another agent. The default value of AMTT is 00h and disables this function. The
AMTT value can be programmed with 8-clock granularity. For example, if the AMTT is programmed to
18h, then the selected value corresponds to the time period of 24 AGP (66 MHz) clocks.

Bit Description

7:3

Multi-Transaction Timer Count Value (MTTC): The number programmed in these bits represents
the guaranteed time slice (measured in eight 66-MHz clock granularity) allotted to the current agent
(either AGP master or MCH-M) after which the AGP arbiter may grant the bus to another agent.

2:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.32.

LPTT AGP Low Priority Transaction Timer Register Device

Address Offset:

BDh

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SBA
mechanisms.

The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66
MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not
necessarily apply to a single transaction, but can span multiple low-priority transactions of the same type.
After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request.
The LPTT does not apply in the case of high-priority request where ownership is transferred directly to
high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT
value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h,
then the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.

Bit Description

7:3

Low Priority Transaction Timer Count Value (LPTTC): The number of clocks programmed in these
bits represents the guaranteed time slice (measured in eight 66-MHz clock granularity) allotted to the
current low priority AGP transaction data transfer state.

2:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.33.

TOM Top of Low Memory Register Device #0

Address Offset:

C4-C5h

Default Value:

0100h

Access: Read/Write
Size: 16

bits

This register contains the maximum address below 4 GB that should be treated as a memory access. Note
that this register must be set to a value of 0100h (16 MB) or greater. Usually it will sit below the areas
configured for the hub interface, PCI memory, and the graphics aperture.

Bit Description

15:4

Top of Low Memory (TOM): This register contains the address that corresponds to bits 31 to 20 of
the maximum DRAM memory address that lies below 4 GB. Configuration software should set this
value to either the maximum amount of memory in the system or to the minimum address allocated
for PCI memory or the graphics aperture, whichever is smaller.

Programming example: 400h = 1 GB. An access to 4000_0000h or above will be considered above
the TOM and therefore not routed to DRAM. It may go to AGP, aperture, or subtractively decode to
Hub Interface.

3:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.34.

MCH-MCFG MCH-M Configuration Register Device #0

Offset: C6-C7h
Default: 0000h
Access:

Read/Write Once, Read/Write, Read Only

Size: 16

bits

Bit Description

15:12

Reserved

System Memory Frequency Select: This bit must be programmed prior to memory initialization.

This bit must be programmed/set to "0" prior to memory initialization in order to guarantee proper
operation of the Intel®845MZ.

0: System Memory frequency is set to 100 MHz

1: System Memory frequency is set to 133 MHz (845MP only)

10:6

Reserved

Monochrome Display adapter Present (MDAP): This bit works with the VGA Enable bit in the
BCTRL register of device 1 to control the routing of host initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is
not set in device 1 BCTRL1 register. When the MDAP bit is set, accesses to MDA resources are
forwarded to hub interface A. MDA resources are defined as the following:

Memory addresses: 0B0000h - 0B7FFFh

I/O addresses: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh,

including ISA address aliases, (A[15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the
hub interface A even if the reference also includes I/O locations not listed above.

Please refer to the System Address Map section of this document for further information.

4:3

Reserved

In-Order Queue Depth (IOQD): This bit reflects the value sampled on HA[7]# on the deassertion of
the CPURST#. It indicates the depth of the host bus in-order queue (i.e. level of host bus pipelining).
If IOQD is set to 1 (HA[7]# sampled "1" i.e. undriven on the host bus), then the depth of the host bus
in-order queue is configured to the maximum allowed by the host bus protocol (i.e. 12). Note that the
MCH-M has an 12 deep IOQ and will assert BNR# on the bus to limit the number of queued bus
transactions to 12. If the IOQD bit is set to 0 (HA[7]# is sampled asserted , i.e., "0"), then depth of
the host bus in-order queue is set to 1 (i.e. no pipelining support on the host bus).

Note that HA[7]# is not driven by the MCH-M during CPURST#. If an IOQ size of 1 is desired, HA[7]#
must be driven low during CPURST# by an external source.

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.35.

ERRSTS Error Status Register Device #0

Address Offset:

C8-C9h

Default Value:

0000h

Access:

Read Only, Read/Write Clear

Size: 16

bits

This register is used to report various error conditions via the hub interface messages to ICH3-M. An
SERR, SMI, or SCI error message may be generated via the hub interface A on a zero to one transition of
any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers
respectively. These bits are set regardless of whether or not the SERR is enabled and generated.

Bit Description

15:10

Reserved

LOCK to non-DRAM Memory Flag (LCKF): When this bit is set it indicates that a host initiated
LOCK cycle targeting non-DRAM memory space occurred. Software must write a "1" to clear this
status bit.

8:7

Reserved

SERR on hub interface A Target Abort (TAHLA): When this bit is set, the MCH-M has detected that
an MCH-M originated hub interface A cycle was terminated with a Target Abort completion packet or
special cycle. Software must write a "1" to clear this bit.

MCH-M Detects Unimplemented hub interface Special Cycle (HIAUSC): When this bit is set the
MCH-M detected an Unimplemented Special Cycle on the hub interface. Software must write a "1" to
clear this bit.

AGP Access Outside of Graphics Aperture Flag (OOGF): When this bit is set it indicates that an
AGP access occurred to an address that is outside of the graphics aperture range. Software must
write a 1 to clear this status bit.

Invalid AGP Access Flag (IAAF): When this bit is set to 1 it indicates that an AGP access was
attempted outside of the graphics aperture and either to the 640k-1M range or above top of the
memory or illegal aperture access. Software must write a 1 to clear this status bit.

Invalid Graphics Aperture Translation Table Entry (ITTEF): When this bit is set to 1 it indicates
that an invalid translation table entry was returned in response to an AGP access to the graphics
aperture. Software must write a 1 to clear this bit.

Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had
an uncorrectable multiple-bit error. When this bit is set the address and device number that caused
the error are logged in the EAP register. Software uses bits [1:0] to detect whether the logged error
address is for Single or Multiple-bit error. Once software completes the error processing, a value of `1'
is written to this bit field to clear the value (back to 0) and unlock the error logging mechanism.

Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory read data transfer had a
single-bit correctable error and the corrected data was sent for the access. When this bit is set the
address, channel number, and device number that caused the error are logged in the EAP register.
Once this bit is set the EAP, CN, DN, and ES fields are locked to further single bit error updates until
the processor clears this bit by writing a 1. Software must write a "1" to clear this bit and unlock the
error logging mechanism.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.36.

ERRCMD Error Command Register Device #0

Address Offset:

CA-CBh

Default Value:

0000h

Access:

Read Only, Read/Write

Size: 16

bits

This register enables various errors to generate an SERR message via the hub interface A. Since the
MCH-M does not have an SERR# signal, SERR messages are passed from the MCH-M to the ICH3-M
over the hub interface. When a bit in this register is set, an SERR message will be generated on hub
interface whenever the corresponding flag is set in the ERRSTS register. The actual generation of the
SERR message is globally enabled for Device #0 via the PCI Command register.

Note: An error can generate one and only one error message via the hub interface A. It is software's

responsibility to make sure that when an SERR error message is enabled for an error condition; SMI and
SCI error messages are disabled for that same error condition.

Bit Description

15:10

Reserved

SERR on Non-DRAM Lock (LCKERR): When this bit is asserted, the MCH-M will generate a hub
interface A SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM

8:7

Reserved

SERR on Target Abort on hub interface A Exception (TAHLA_SERR): When this bit is set, the
generation of the hub interface A SERR message is enabled when an MCH-M originated hub
interface A cycle is completed with "Target Abort" completion packet or special cycle status.

SERR on Detecting Hub Interface A Unimplemented Special Cycle (HIAUSCERR): When this bit
is set to 1 the MCH-M generates an SERR message over hub interface A when an Unimplemented
Special Cycle is received on the hub interface. When this bit is set to 0 the MCH-M does not generate
an SERR message for this event. SERR messaging for Device 0 is globally enabled in the PCICMD
register.

SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR): When this bit is set, the
generation of the hub interface A SERR message is enabled when an AGP access occurs to an
address outside of the graphics aperture.

SERR on Invalid AGP Access (IAAF_SERR): When this bit is set, the generation of the hub
interface A SERR message is enabled when an AGP access occurs to an address outside of the
graphics aperture and either to the 640K - 1M range or above the top of memory.

SERR on Invalid Translation Table Entry (ITTEF_SERR): When this bit is set, the generation of the
hub interface A SERR message is enabled when an invalid translation table entry was returned in
response to an AGP access to the graphics aperture.

SERR Multiple-Bit DRAM ECC Error (DMERR_SERR): When this bit is set, the generation of the
hub interface A SERR message is enabled when the MCH-M DRAM controller detects a multiple-bit
error. For systems not supporting ECC this bit must be disabled.

SERR on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SERR message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.37.

SMICMD SMI Command Register Device #0

Address Offset:

CC-CDh

Default Value:

0000h

Access:

Read/Write, Read Only

Size: 16

bits

This register enables various errors to generate an SMI message via the hub interface A.

Note: An error can generate one and only one error message via the hub interface A. It is software's

responsibility to make sure that when an SMI error message is enabled for an error condition; SERR and
SCI error messages are disabled for that same error condition.

Bit Description

15:2

Reserved

SMI on Multiple-bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub
interface A SMI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.

SMI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SMI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.

3.7.38.

SCICMD SCI Command Register Device #0

Address Offset:

CE-CDh

Default Value:

0000h

Access:

Read/Write, Read Only

Size: 16

bits

This register enables various errors to generate a SCI message via the hub interface A.

Note: An error can generate one and only one error message via the hub interface A. It is software's

responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and
SMI error messages are disabled for that same error condition.

Bit Description

15:2

Reserved

SCI on Multiple-Bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub
interface A SCI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.

SCI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.7.39.

SKPD Scratchpad Data Device #0

Address Offset:

DE-DFh

Default Value:

0000h

Access: Read/Write
Size: 16

bits

Bit Description

15:0

Scratchpad [15:0]. These bits are simply R/W storage bits that have no affect on the MCH-M
functionality.

3.7.40.

CAPID Product Specific Capability Identifier

Address Offset:

E4h

Default Value:

B104A009h

Access: Read

Only

Size: 32

bits

Bit Description

Dual Data Rate System Memory Capability

1 = Component supports Dual Data Rate (DDR) SDRAM memory.

Mobile Power Management Capability:

1 = Component is capable of all Mobile Power Management features.

0 = Component is NOT capable of all Mobile Power Management features

Reserved

System Memory Capability

1 = Component supports up to a 266-MHz DDR memory system, and more than 512 MB of maximum
physical memory.

0 = Component supports 200-MHz DDR memory system, will support up to 512 MB of physical
memory.

27:24

CAPID Version: This field has the value 0001b to identify the first revision f the CAPID register
definition.

23:16

CAPID Length: This field has the value 04h to indicate the structure length (4 bytes).

15:8

Next Capability Pointer: This field has the value A0h to point to the next Capability ID in this device
(ACAPID AGP Capability ID Register).

7:0

CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor
dependent capability pointers.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.

AGP Bridge Registers Device #1

Table 24 shows the access attributes for configuration space.

Table 24. Nomenclature for Access Attributes

Read Only. If a register is read only, writes to this register have no effect.

R/W

Read/Write. A register with this attribute can be read and written.

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

Table 25 summarizes the MCH-M configuration space for Device #1.

Table 25. MCH-M Configuration Space - Device #1

Address Offset

Register Symbol

Register Name

Default Value

Access

00-01h VID1

Vendor Identification

8086h RO

02-03h DID1

Device Identification

1A31hh RO

04-05h PCICMD1 PCI Command Register

0000h RO,

R/W

06-07h PCISTS1 PCI Status Register

00A0h RO,

R/WC

08 RID1 Revision Identification

Silicon Revision

Reserved

0Ah SUBC1

Sub-Class Code

04h RO

0Bh BCC1 Base Class Code

06h RO

0Ch

Reserved

0Dh MLT1 Master Latency Timer

00h RO,

R/W

0Eh HDR1 Header Type

01h RO

0F-17h

Reserved

18h PBUSN1

Primary Bus Number

00h RO

19h SBUSN1

Secondary Bus Number

00h R/W

1Ah SUBUSN1

Subordinate Bus Number

00h R/W

1Bh SMLT1

Secondary Bus Master Latency
Timer

00h RO,

R/W

1Ch IOBASE1

I/O Base Address Register

F0h RO,

R/W

1Dh IOLIMIT1

I/O Limit Address Register

00h RO,

R/W

1E-1Fh SSTS1 Secondary Status Register

02A0h RO,

R/WC

20-21h MBASE1 Memory Base Address Register

FFF0h RO,

R/W

22-23h MLIMIT1 Memory Limit Address Register

0000h RO,

R/W

24-25h PMBASE1

Prefetchable Memory Base
Address Reg.

FFF0h RO,

R/W

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.1.

VID1 Vendor Identification Register Device #1

Address Offset:

00 - 01h

Default Value:

8086h

Attribute: Read

Only

Size: 16

bits

The VID Register contains the vendor identification number. This 16-bit register combined with the
Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.

Bit Description

15:0

Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h.

3.8.2.

DID1 Device Identification Register Device #1

Address Offset:

02 - 03h

Default Value:

1A31h

Attribute: Read

Only

Size: 16

bits

This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Writes to this register have no effect.

Bit Description

15:0

Device Identification Number. This is a 16-bit value assigned to the MCH-M device #1.
MCH-M1 device #1 DID =1A31h.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.8.3.

PCICMD1 PCI-PCI Command Register Device #1

Address Offset:

04-05h

Default: 0000h
Access:

Read Only, Read/Write

Size 16

bits

Bit Descriptions

15:10

Reserved

Fast Back-to-Back Enable (FB2BEn): Not Applicable. Hardwired to "0."

SERR Message Enable (SERRE1): This bit is a global enable bit for Device #1 SERR messaging.
The MCH-M does not have an SERR# signal. The MCH-M communicates the SERR# condition by
sending an SERR message to the ICH3-M. If this bit is set to a 1, the MCH-M is enabled to generate
SERR messages over the hub interface for specific Device #1 error conditions that are individually
enabled in the BCTRL register. The error status is reported in the PCISTS1 register. If SERRE1 is
reset to 0, then the SERR message is not generated by the MCH-M for Device #1.

NOTE: This bit only controls SERR messaging for the Device #1. Device #0 has its own SERRE bit to
control error reporting for error conditions occurring on Device #0.

Address/Data Stepping (ADSTEP): Not applicable. Hardwired to "0."

Parity Error Enable (PERRE1): Parity checking is not supported on the primary side of this device.
Hardwired to `0'

Reserved

Memory Write and Invalidate Enable (MWIE): This bit is implemented as Read Only and returns a
value of 0 when read.

Special Cycle Enable (SCE): This bit is implemented as Read Only and returns a value of 0 when
read.

Bus Master Enable (BME1): This bit is not functional. It is a RW bit for compatibility with compliance
testing software.

Memory Access Enable (MAE1): This bit must be set to 1 to enable the Memory and Prefetchable
memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
When set to 0 all of device #1's memory space is disabled.

I/O Access Enable (IOAE1): This bit must be set to1 to enable the I/O address range defined in the
IOBASE1, and IOLIMIT1 registers. When set to 0 all of device #1's I/O space is disabled.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.4.

PCISTS1 PCI-PCI Status Register Device #1

Address Offset:

06-07h

Default Value:

00A0h

Access:

Read Only, Read/Write Clear

Size: 16

bits

PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary
side of the "virtual" PCI-PCI bridge embedded within the MCH-M. Since this device does not
physically reside on PCI_A it reports the optimum operating conditions so that it does not restrict the
capability of PCI_A.

Bit Descriptions

Detected Parity Error (DPE1): Not Applicable - hardwired to "0."

Signaled System Error (SSE1): This bit is set to 1 when MCH-M Device #1 generates an SERR
message over the hub interface A for any enabled Device #1 error condition. Device #1 error
conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers. Device #1 error flags are
read/reset from the ERRSTS and SSTS1 register. Software clears this bit by writing a 1 to it.

Received Master Abort Status (RMAS1): Not Applicable - hardwired to "0."

Received Target Abort Status (RTAS1): Not Applicable - hardwired to "0."

Signaled Target Abort Status (STAS1): Not Applicable - hardwired to "0."

10:9

DEVSEL# Timing (DEVT1): This bit field is hardwired to "00b" to indicate that the device #1 uses the
fastest possible decode.

Data Parity Detected (DPD1): Not Applicable - hardwired to "0".

Fast Back-to-Back Capable (FB2B1): This bit is hardwired to "1" to indicate that the AGP port
supports fast back to back transactions when the transactions are to different targets.

Reserved

66-MHz Capability (CAP66): This bit is hardwired to "1" to indicate that the AGP port is 66-MHz
capable.

4:0

Reserved

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.8.5.

RID1 Revision Identification Register Device #1

Address Offset:

08h

Default Value:

Dependent on Silicon Revision

Access: Read

Only

Size: 8

bits

This register contains the revision number of the MCH-M device #1. These bits are read only and writes
to this register have no effect. For the A-0 stepping, this value is 00h.

Bit Description

7:0

Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the MCH-M device #1.

3.8.6.

SUBC1- Sub-Class Code Register Device #1

Address Offset:

0Ah

Default Value:

04h

Access: Read

Only

Size: 8

bits

This register contains the Sub-Class Code for the MCH-M device #1. This code is 04h indicating a PCI-
PCI Bridge device. The register is read only.

Bit Description

7:0

Sub-Class Code (SUBC1): This is an 8-bit value that indicates the category of Bridge into which the
MCH-M falls. The code is 04h indicating a Host Bridge.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.7.

BCC1 Base Class Code Register Device #1

Address Offset:

0Bh

Default Value:

06h

Access: Read

Only

Size: 8

bits

This register contains the Base Class Code of the MCH-M device #1. This code is 06h indicating a
Bridge device. This register is read only.

Bit Description

7:0

Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the MCH-M
device #1. This code has the value 06h, indicating a Bridge device.

3.8.8.

MLT1 Master Latency Timer Register Device #1

Address Offset:

0Dh

Default Value:

00h

Access: Read/Write
Size: 8

bits

This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-PCI bridge configuration software from getting "confused."

Bit Description

7:3

Not applicable but supports read/write operations. (Reads return previously written data.)

2:0

Reserved

3.8.9.

HDR1 Header Type Register Device #1

Offset: 0Eh
Default: 01h
Access: Read

Only

Size: 8

bits

This register identifies the header layout of the configuration space.

Bit Descriptions

7:0

This read only field always returns 01h when read. Writes have no effect.

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.8.10.

PBUSN1 Primary Bus Number Register Device #1

Offset: 18h
Default: 00h
Access: Read

Only

Size: 8

bits

This register identifies that "virtual" PCI-PCI Bridge is connected to bus #0.

Bit Descriptions

7:0

Bus Number. Hardwired to "0."

3.8.11.

SBUSN1 Secondary Bus Number Register Device #1

Offset: 19h
Default: 00h
Access: Read

/Write

Size: 8

bits

This register identifies the bus number assigned to the second bus side of the "virtual" PCI-PCI bridge
i.e. to AGP. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to AGP.

Bit Descriptions

7:0

Bus Number. Programmable. Default = "00h".

3.8.12.

SUBUSN1 Subordinate Bus Number Register Device #1

Offset: 1Ah
Default: 00h
Access: Read

/Write

Size: 8

bits

This register identifies the subordinate bus (if any) that resides at the level below AGP. This number is
programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.

Bit Descriptions

7:0

Bus Number. Programmable. Default = "00h".

Intel

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250687-002

Datasheet

3.8.13.

SMLT1 Secondary Master Latency Timer Register Device

Address Offset:

1Bh

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

This register controls the bus tenure of the MCH-M on AGP. SMLT1 is an 8-bit register that controls the
amount of time the MCH-M as an AGP/PCI bus master, can burst data on the AGP Bus. The Count
Value is an 8-bit quantity, however SMLT1[2:0] are reserved and assumed to be 0 when determining the
Count Value. The MCH-M's SMLT1 is used to guarantee the AGP master a minimum amount of system
resources. When the MCH-M begins the first AGP FRAME# cycle after being granted the bus, the
counter is loaded and enabled to count from the assertion of FRAME#. If the count expires while the
MCH-M's grant is removed (due to an AGP master request), then the MCH-M will lose the use of the
bus, and the AGP master may be granted the bus. If MCH-M's bus grant is not removed, the MCH-M
will continue to own the AGP bus regardless of the SMLT1 expiration or idle condition.

The number of clocks programmed in the SMLT1 represents the guaranteed time slice (measured in 66-
MHz AGP clocks) allotted to the MCH-M, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT1 is
programmed to 18h, then the value is 24 AGP clocks. The default value of SMLT1 is 00h and disables
this function. When the SMLT1 is disabled, the burst time for the MCH-M is unlimited (i.e. the MCH-M
can burst forever).

Bit Description

7:3

Secondary MLT counter value. Default=0, i.e. SMLT1 disabled

2:0

Reserved

Intel

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Datasheet

250687-002

3.8.14.

IOBASE1 I/O Base Address Register Device #1

Address Offset:

1Ch

Default Value:

F0h

Access:

Read/Write, Read Only

Size: 8

bits

This register controls the hosts to AGP I/O access routing based on the following formula:

IO_BASE=< address =<IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.

Bit Description

7:4

I/O Address Base. Corresponds to A[15:12] of the I/O address. Default=Fh

3:0

Reserved

3.8.15.

IOLIMIT1 I/O Limit Address Register Device #1

Address Offset:

1Dh

Default Value:

00h

Access:

Read/Write, Read Only

Size: 8

bits

This register controls the hosts to AGP I/O access routing based on the following formula:

IO_BASE=< address =<IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.

Bit Description

7:4

I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default=0h

3:0

Reserved (Only 16-bit addressing supported)

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.16.

SSTS1 Secondary PCI-PCI Status Register Device #1

Address Offset:

1E-1Fh

Default Value:

02A0h

Access:

Read Only, Read/Write Clear

Size: 16

bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary
side (i.e. AGP side) of the "virtual" PCI-PCI bridge embedded within MCH-M.

Bit Descriptions

Detected Parity Error (DPE1): This bit is set to a 1 to indicate MCH-M's detection of a parity error in
the address or data phase of AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to this bit.

Reserved

Received Master Abort Status (RMAS1): When the MCH-M terminates a Host-to-AGP with an
unexpected master abort, this bit is set to 1. Software resets this bit to 0 by writing a 1 to it.

Received Target Abort Status (RTAS1): When an MCH-M-initiated transaction on AGP is
terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1 to 0 by writing a 1 to it.

Signaled Target Abort Status (STAS1): STAS1 is hardwired to a 0, since the MCH-M does not
generate target abort on AGP.

10:9

DEVSEL# Timing (DEVT1): This 2-bit field indicates the timing of the DEVSEL# signal when the
MCH-M responds as a target on AGP, and is hardwired to the value 01b (medium) to indicate the
time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.

Master Data Parity Error Detected (DPD1): Hardwired to 0. MCH-M does not implement G_PERR#
signal.

Fast Back-to-Back Capable (FB2B1): This bit is hardwired to 1, since MCH-M as a target supports
fast back-to-back transactions to different targets on the AGP interface.

Reserved

66 MHz Capable (CAP66): This bit is hardwired to 1 to indicate that AGP bus is capable of 66-MHz
operation.

4:0

Reserved

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82845MP/82845MZ Chipset-Mobile (MCH-M)

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Datasheet

3.8.18.

MLIMIT1 Memory Limit Address Register Device #1

Address Offset:

22-23h

Default Value:

0000h

Access:

Read/Write, Read Only

Size: 16

bits

This register controls the host to AGP non-prefetchable memory accesses routing based on the following
formula:

MEMORY_BASE1=< address =<MEMORY_LIMIT1

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeros when read. The
configuration software must initialize this register. For the purpose of address decode address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1-MB aligned memory block.

Bit Description

15:4

Memory Address Limit 1(MEM_LIMIT1). Corresponds to A[31:20] of the memory address.

Default=000h

3:0

Reserved

Note: The memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable AGP

address ranges (typically where control/status memory-mapped I/O data structures of the graphics
controller will reside), and PMBASE 1and PMLIMIT1 are used to map prefetchable address ranges
(typically graphics local memory). This segregation allows application of USWC space attribute to be
performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP
memory access performance.

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Datasheet

3.8.20.

PMLIMIT1 Prefetchable Memory Limit Address Register 

Device #1

Address Offset:

26-27h

Default Value:

0000h

Access:

Read/Write, Read Only

Size: 16

bits

This register controls the host to AGP prefetchable memory accesses routing based on the following
formula:

PREFETCHABLE_MEMORY_BASE1=< address =<PREFETCHABLE_MEMORY_LIMIT1

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The
configuration software must initialize this register. For the purpose of address decode address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1-MB aligned memory block.

Bit Description

15:4

Prefetchable Memory Address Limit 1(PMEM_LIMIT1). Corresponds to A[31:20] of the memory
address.

Default=000h

3:0

Reserved

Note: Prefetchable memory range is supported to allow segregation by the configuration software between the

memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e.
prefetchable) from the processor perspective.

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3.8.21.

BCTRL1 PCI-PCI Bridge Control Register Device #1

Address Offset:

3Eh

Default: 00h
Access:

Read Only, Read/Write

Size 8

bits

This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary interface (i.e. AGP) as well as some bits that affect
the overall behavior of the "virtual" PCI-PCI bridge embedded within MCH-M, e.g. VGA compatible
address ranges mapping.

Bit Descriptions

Fast Back to Back Enable (FB2BEN): Normally this bit controls whether the bridge will generate
Fast Back to Back cycles to different targets. However, since there is only one target allowed on the
AGP interface, this bit is meaningless. This bit is hardwired to "0".

Secondary Bus Reset (SRESET): MCH-M does not support generation of reset via this bit on the
AGP and therefore this bit is hardwired to "0". Note that the only way to perform a hard reset of the
AGP bus is via the system reset either initiated by software or hardware via ICH3-M.

Master Abort Mode (MAMODE): This bit is hardwired to "0". This means when acting as a master
on AGP the MCH-M will discard data on writes and return all 1s during reads when a Master Abort
occurs.

Reserved

VGA Enable (VGAEN1): Controls the routing of host initiated transactions targeting VGA compatible
I/O and memory address ranges. When this bit is set , the MCH-M will forward the following host-
initiated accesses to the AGP bus:

1) memory accesses in the range 0A0000h to 0BFFFFh

2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh or 3C0h to 3DFh

(inclusive of ISA address aliases - A[15:10] are not decoded)

When this bit is set, forwarding of these accesses issued by the host is independent of the I/O
address and memory address ranges that are defined by the previously defined base and limit
registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of
this register if this bit is "1".

If this bit is "0" (default) , then VGA compatible memory and I/O range accesses are not forwarded to
AGP. Instead they are mapped to the hub interface unless they are mapped to AGP via I/O and
memory range registers defined above (IOBASE1, IOLIMIT1, MBASE1, MLIMIT1, PMBASE1,
PMLIMIT1). Please refer to the System Address Map section of this document for further information.

ISA Enable (ISAEN): Modifies the response by the MCH-M to an I/O access issued by the host that
targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and
IOLIMIT registers. When this bit is set to 1 MCH-M will not forward to AGP any I/O transactions
addressing the last 768 bytes in each 1-KB block even if the addresses are within the range defined
by the IOBASE and IOLIMIT registers. Instead of going to AGP these cycles will be forwarded to the
hub interface. If this bit is "0" (default) then all addresses defined by the IOBASE and IOLIMIT for
host I/O transactions will be mapped to AGP.

Reserved

Parity Error Response Enable (PEREN): Controls MCH-M's response to data phase parity errors on
AGP. G_PERR# is not implemented by the MCH-M. However, when this bit is set to 1, address and
data parity errors detected on AGP are reported via hub interface SERR# messaging mechanism, if
further enabled by SERRE1. If this bit is reset to 0, then address and data parity errors on AGP are
not reported via the MCH-M hub interface SERR# messaging mechanism. Other types of error
conditions can still be signaled via SERR# messaging independent of this bit's state.

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3.8.23.

DWTMC DRAM Write Thermal Management Control

Offset: 50h-57h
Default: 0000_0000_0000_0000h

Access: Read/Write/Lock
Size: 64

bits

Bit Description

63:52

Reserved

51:50

TM Lock: These bits secure the DRAM Thermal Management control registers. The bits default to
`0'. Once a `1' is written to either bit, the configuration register bits specified in DWTMC and DRTMC
registers become read-only:

Not locked: All bits in DWTMC or DRTMC are writeable.

Start Mode bits are not locked: All bits in DWTMC and DRTMC except for SWMT and
SRMT are locked and become Read Only.

All bits locked: All of the bits in the DWTMC or DRTMC are locked and become Read
Only.

Reserved

48:41

Global DRAM Write Sampling Window (GDWSW): This eight bit value is multiplied by 4*10

define the length of time in host clocks over which the number of hexwords(32-Byte chunk) written is
counted. If the number of hexwords written during this window exceeds the Global Write Hexword
Threshold (GWHT) defined below, then the thermal management mechanism will be invoked.

40:28

Global Write Hexword Threshold (GWHT): The thirteen-bit value held in this field is multiplied by
2

to arrive at the number of hexwords that must be written within the Global DRAM Write Sampling

Window(GDWSW) in order to cause the thermal management mechanism to be invoked.

27:22

Write Thermal Management Time (WTMT): This value provides a multiplier between 0 and 63,
which specifies how long thermal management remains in effect as a number of Global DRAM Write
Sampling Windows*. For example, if GDWSW is programmed to

1000_0000b and WTT is set to 01_0000b, then thermal management will be performed for 8192*10

host clocks (at 100 MHz) seconds once invoked (128 * 4*10

host clocks * 16).

21:15

Write Thermal Management Monitoring Window (WTMMW): The value in this register is padded
with 4 0's to specify a window of 0-2047 host clocks with 16 clock granularity. While the thermal
management mechanism is invoked, DRAM writes are monitored during this window. If the number of
hexwords written during the window reaches the Write Thermal Management Hexword Maximum,
then write requests are blocked for the remainder of the window.

14:3

Write Thermal Management Hexword Maximum (WTMHM): The Write Thermal Management
Hexword Maximum defines the maximum number of hexwords between 0-4095, which are permitted
to be written to DRAM within one Write Thermal Management Monitoring Window.

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2:1

Write Thermal Management Mode (WTMMode):

Thermal management via Counters and Hardware Thermal Management_on signal
mechanisms disabled.

Hardware Thermal Management_on signal mechanism is enabled. In this mode, as
long as the Thermal Management_on signal is asserted, write thermal management is in
effect based on the settings in WTMW and WTHM. When the Thermal Management_on
signal is de-asserted, write thermal management stops and the counters associated with
the WTMW and WTHM are reset. When the hardware Thermal Management_on signal
mechanism is not enabled, the Thermal Management_on signal has no effects.

Counter mechanism controlled through GDWSW and GWHT is enabled. When the
threshold set in GDWSW and GWHT is reached, thermal management start/stop cycles
occur based on the settings in WTMT, WTMMW and WTMHM.

Reserved

START Write Thermal Management (SWTM): When this bit is set to `1' write thermal management
begins based on the settings in WTMW and WTHM, and remains to be in effect until this bit is reset
to `0'. When this bit is reset to `0', write thermal management stops and the counters associated with
WTMW and WTHM are reset. Software writes to this bit to start and stop write thermal management.

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3.8.24.

DRTMC DRAM Read Thermal Management Control

Offset: 58h-5Fh
Default: 0000_0000_0000_0000h

Access: Read/Write/Lock
Size: 64

bits

Bit Description

63:49

Reserved

48:41

Global DRAM Read Sampling Window (GDRSW): This eight bit value is multiplied by 4*10

define the length of time in host clocks over which the number of hexwords read from the DRAM is
counted. If the number of hexwords read during this window exceeds the Global Read Hexword
Threshold (GRHT) defined below, then the thermal management mechanism will be invoked.

40:28

Global Read Hexword Threshold (GRHT): The thirteen-bit value held in this field is multiplied by 2

to arrive at the number of hexwords that must be written within the Global DRAM Read Sampling
Window(GDRSW) in order to cause the thermal management mechanism to be invoked.

27:22

Read Thermal Management Time (RTMT): This value provides a multiplier between 0 and 63 which
specifies how long thermal management remains in effect as a number of Global DRAM Read
Sampling Windows. For example, if GDRSW is programmed to 1000_0000b and WTT is set to
01_0000b, then thermal management will be performed for 8192*10

host clocks (at 100 MHz)

seconds once invoked (128 * 4*10

host clocks * 16).

21:15

Read Thermal Management Monitoring Window (RTMMW): The value in this register is padded
with 4 0's to specify a window of 0-2047 host clocks with 16 clock granularity. While the thermal
management mechanism is invoked, DRAM reads are monitored during this window. If the number of
hexwords read during the window reaches the Write Thermal Management Hexword Maximum, then
read requests are blocked for the remainder of the window.

14:3

Read Thermal Management Hexword Maximum (RTMHM): The Read Thermal Management
Hexword Maximum defines the maximum number of hexwords between 0-4095, which are permitted
to be read to DRAM within one Write Thermal Management Monitoring Window.

2:1

Read Thermal Management Mode (RTMMode):

Thermal management via Counters and Hardware Thermal Management_on signal
mechanisms disabled.

Hardware Thermal Management_on signal mechanism is enabled. In this mode, as
long as the Thermal Management_on signal is asserted, write thermal management is in
effect based on the settings in RTMW and RTHM. When the Thermal Management_on
signal is de-asserted, read thermal management stops and the counters associated with
the RTMW and RTHM are reset. When the hardware Thermal Management_on signal
mechanism is not enabled, the Thermal Management_on signal has no effects.

Counter mechanism controlled through GDRSW and GRHT is enabled. When the
threshold set in GDRSW and GRHT is reached, thermal management start/stop cycles
occur based on the settings in RTMT, RTMMW and RTMHM.

Reserved

START Read Thermal Management (SRTM): When this bit is set to `1' read thermal management
begins based on the settings in RTMW and RTHM, and remains to be in effect until this bit is reset to
`0'. When this bit is reset to `0', read thermal management stops and the counters associated with
RTMW and RTHM are reset. Software writes to this bit to start and stop read thermal management.

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System Address Map

A system based on the Intel

845MP/845MZ Chipset supports 4 GB of addressable memory space and 64

KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration
software into regions. The memory ranges are useful either as system memory or as specialized memory,
while the I/O regions are used solely to control the operation of devices in the system.

4.1. Memory

Address

Ranges

The system memory map is broken into two categories:

Extended Memory Range (1MB to 4GB) - Extended memory, existing between 1 MB and 4 GB. It
contains a 32-bit memory space, which is used for mapping PCI, AGP, APIC, SMRAM, and BIOS
memory spaces.

DOS Compatible Area (below 1 MB) - A DOS legacy space, which is used for BIOS and legacy
devices on the LPC interface.

Figure 5. Addressable Memory Space

DOS legacy Address

Range

PCI Memory Address

Range

4 GB

Independently
Programmable
Non-overlapping
Windows

Main Memory Address

Range

Hublink_A

AGP

Graphics

Aperture

1 MB

Top of Low Memory

Aperture

APICs

These address ranges are always mapped to system memory, regardless of the system configuration.
Memory may be carved out of the MAINMEM segment for use by System Management Mode (SMM)
hardware and software. The Top of Low Memory (TOM) register defines the top of Main Memory.

Note: The address of the highest 16-MB quantity of valid memory in the system is placed into the GBA15

For memory populations less than 3 GB, this value will be the same as the one programmed into the
TOM register. For other memory configurations, the two are unlikely to be the same, since the PCI
configuration portion of the BIOS software will program the TOM register to the maximum value that is
less than the amount of memory in the system and that allows enough room for all populated PCI
devices.

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Figure 6. Detailed DOS Compatible Area Address Map

Upper, Lower,

Expansion Card BIOS

and Buffer Area

1MB

640 KB

768 KB

0C0000h

0A0000h

C o n t r o l l e d b y
PAM[6:0].

Monchrome Display

Adapter Space

Standard PCI/ISA

Video Memory

(SMM Memory)

0B8000h

0B0000h

736 KB

704 KB

C o n t r o l l e d b y
VGA Enable and
MDA enable.

= DRAM

Key

= Optionally DRAM

= Optionally AGP

4.1.1.

VGA and MDA Memory Space

VGAA From

0_000A_0000

0_000A_FFFF

MDA

0_000B_0000

0_000B_7FFF

VGAB

0_000B_8000

0_000B_FFFF

Video cards use the VGAA, MDA, and VGAB legacy address ranges defined above to map a frame
buffer or a character-based video buffer. By default, accesses to these ranges are forwarded to hub
interface. However, if the VGAEN bit is set in the BCTRL1 configuration register, then transactions
within these VGA and MDA memory spaces are sent to AGP instead of the hub interface.

Note: The VGA_EN bit may be set in the BCTRL registers. Software must not set more than one of the

VGA_EN bits.

If the configuration bit MCH-MCFG.MDAP is set, then accesses that fall within the MDA range
(0B0000h 0B7FFFh) will be sent to hub interface without regard for the state of the VGAEN bit (but
accesses to the VGAA and VGAB ranges will still be sent to AGP). Legacy support requires the ability
to have a second graphics controller (monochrome) in the system. In an Intel

845MP/845MZ Chipset

system, accesses in the standard VGA range are forwarded to AGP when VGAEN is set. Since the
monochrome adapter may be on the hub interface bus (or other expansion bus), the MCH-M must be able
to decode cycles in the MDA range and forward them to the hub interface. This capability is controlled
by the MDAP configuration bit. In addition to the memory range B0000h to B7FFFh, the MCH-M can
decode I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and forwards them to hub interface.

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4.1.2.

PAM Memory Spaces

PAMC0 From

0_000C_0000

0_000C_3FFF

PAMC4

0_000C_4000 0_000C_7FFF

PAMC8

0_000C_8000 0_000C_BFFF

PAMCC

0_000C_C000 0_000C_FFFF

PAMD0

0_000D_0000 0_000D_3FFF

PAMD4

0_000D_4000 0_000D_7FFF

PAMD8

0_000D_8000 0_000D_BFFF

PAMDC

0_000D_C000 0_000D_FFFF

PAME0

0_000E_0000 0_000E_3FFF

PAME4

0_000E_4000 0_000E_7FFF

PAME8

0_000E_8000 0_000E_BFFF

PAMEC

0_000E_C000 0_000E_FFFF

PAMF0

0_000F_0000 0_000F_FFFF

The 256-KB PAM region is divided into three parts:

· ISA expansion region, a 128-KB area between 0_000C_0000h 0_000D_FFFFh
· Extended BIOS region, a 64-KB area between 0_000E_0000h 0_000E_FFFFh
· System BIOS region, a 64-KB area between 0_000F_0000h 0_000F_FFFFh.

The ISA expansion region is divided into eight 16 KB segments. Each segment can be assigned one of
four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are
mapped through MCH-M and are subtractively decoded to ISA space.

The extended System BIOS region is divided into four 16 Kbytes segments. Each segment can be
assigned independent read and write attributes so it can be mapped either to main DRAM or to hub
interface. Typically, this area is used for RAM or ROM.

The system BIOS region is a single 64-Kbytes segment. This segment can be assigned read and write
attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to hub interface.
By manipulating the read/write attributes, the MCH-M can "shadow" BIOS into main DRAM.

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4.1.3.

ISA Hole Memory Space

BIOS software may optionally open a "window" between 15 MB and 16 MB (0_00F0_0000h to
0_00FF_FFFF) that relays transactions to hub interface instead of completing them with a system
memory access. This window is opened with the FDHC.HEN configuration field.

Figure 7. Detailed Extended Memory Range Address Map

Key

1_0000_0000 (4GB)

Local Apic Space

FEF0_0000

FEE0_0000

Hub interface_D-E I/O

Apic Space

FED0_0000

Top of Low Memory (TOM)

FEC0_0000

Hub interface_A I/O

Apic Space

FEC8_0000

High BIOS, optional

extended SMRAM

FF00_0000

Region allowed for AGP/PCI

DRAM Region

100A_0000

Extended SMRAM

(translated to < 1MB)

100C_0000

00F0_0000 (15 MB)

ISA Hole

0100_0000 (16 MB)

0010_0000 (1MB)

Optional DRAM Region

Hub interface_A (always)

Extended SMRAM

Space

TEM - TSEG

4.1.4.

TSEG SMM Memory Space

TSEGSMM From

TOM

TSEG

TOM

The TSEG SMM space allows system management software to partition a region of main memory just
below the top of low memory (TOM) that is accessible only by system management software. This
region may be 128 kB, 256 kB, 512 kB, or 1 MB in size, depending upon the ESMRAMC.TSEG_SZ
field. SMM memory is globally enabled by SMRAM.G_SMRARE. Requests may access SMM system
memory when either SMM space is open (SMRAM.D_OPEN) or the MCH-M receives an SMM code
request on its system bus. In order to access the TSEG SMM space, the TSEG must be enabled by
ESMRAMC.T_EN. When all of these conditions are met, then a system bus access to the TSEG space
(between TOM-TSEG and TOM) is sent to system memory. If the high SMRAM is not enabled or if the
TSEG is not enabled, then all memory requests from all interfaces are forwarded to system memory. If
the TSEG SMM space is enabled, and an agent attempts a non-SMM access to TSEG space, then the
transaction is specially terminated.

Hub interface and AGP originated accesses are not allowed to SMM space.

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4.1.5.

System Bus Interrupt APIC Memory Space

SBINTR From

0_FEE0_0000

0_FEEF_FFFF

The System Bus interrupt space is the address used to deliver interrupts to the system bus. Any device on
AGP or hub interface, D, E may issue a Memory Write to 0FEEx_xxxxh. The MCH-M will forward this
Memory Write along with the data to the system bus as an Interrupt Message Transaction. The MCH-M
terminates the system bus transaction by providing the response and asserting TRDY#. This Memory
Write cycle does not go to DRAM.

4.1.6.

High SMM Memory Space

HIGHSMM From

0_FEDA_0000

0_FEDB_FFFF

The HIGHSMM space allows cacheable access to the compatible SMM space by re-mapping valid SMM
accesses between 0_FEDA_0000 and 0_FEDB_FFFF to accesses between 0_000A_0000 and
0_000B_FFFF. The accesses are remapped when SMRAM space is enabled, an appropriate access is
detected on the system bus, and when ESMRAMC.H_SMRAME allows access to high SMRAM space.
SMM memory accesses from any hub interface or AGP are specially terminated: reads are provided with
the value from address 0 while writes are ignored entirely.

4.1.7.

AGP Aperture Space (Device #0 BAR)

AGPAPP

From

APBASE

APBASE + APSIZE

Processors and AGP devices communicate through a special buffer called the "graphics aperture". This
aperture acts as a window into the main DRAM memory and is defined by the APBASE and APSIZE
configuration registers of the Intel

845MP/845MZ Chipset MCH-M. Note that the AGP aperture must be

above the top of memory and must not intersect with any other address space.

4.1.8.

AGP Memory and Prefetchable Memory

M1 From

MBASE1

MLIMIT1

PM1

PMBASE1

PMLIMIT1

Plug-and-play software configures the AGP memory window in order to provide enough memory space
for the devices behind this PCI-to-PCI bridge. Accesses whose addresses fall within this window are
decoded and forwarded to AGP for completion. Note that these registers must be programmed with
values that place the AGP memory space window between the value in the TOM register and 4 GB. In
addition, neither region should overlap with any other fixed or relocatable area of memory.

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4.1.9.

Hub Interface A Subtractive Decode

HLA_SUB From

TOM

4GB

All accesses that fall between the value programmed into the TOM register and 4GB are subtractively
decoded and forwarded to hub interface if they do not decode to a space that corresponds to another
device.

4.2.

AGP Memory Address Ranges

The MCH-M can be programmed to direct memory accesses to the AGP bus interface when addresses
are within either of two ranges specified via registers in MCH-M Device #1 configuration space. The
first range is controlled via the Memory Base Register (MBASE1) and Memory Limit Register
(MLIMIT1) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE1)
and Prefetchable Memory Limit (PMLIMIT1) registers.

The MCH-M positively decodes memory accesses to AGP memory address space as defined by the
following equations:

· Memory_Base_Address <= Address =< Memory_Limit_Address
· Prefetchable_Memory_Base_Address =< Address <= Prefetchable_Memory_Limit_Address

Plug-and-play configuration software programs the effective size of the range, which depends on the size
of memory claimed by the AGP device.

Note: The MCH-M Device #1 memory range registers described above are used to allocate memory address

space for any devices sitting on AGP bus that requires such a window.

4.2.1.

AGP DRAM Graphics Aperture

Memory-mapped, graphics data structures can reside in a Graphics Aperture to main DRAM memory.
This aperture is an address range defined by the APBASE and APSIZE configuration registers of the
MCH-M device #0. The APBASE register follows the standard base address register template as defined
by the PCI 2.1 specification. The size of the range claimed by the APBASE is programmed via "back-
end" register APSIZE (programmed by the chip-set specific BIOS before plug-and-play session is
performed). APSIZE allows the BIOS software to pre-configure the aperture size to be 4 MB, 8 MB, 16
MB, 32 MB, 64 MB, 128 MB or 256 MB. By programming APSIZE to specific size, the corresponding
lower bits of APBASE are forced to "0" (behave as hardwired). The default value of APSIZE forces an
aperture size of 256 MB. The aperture address range is naturally aligned.

Accesses within the aperture range are forwarded to the main DRAM subsystem. The MCH-M will
translate the originally issued addresses via a translation table maintained in main memory. The aperture
range should be programmed as non-cacheable in the processor caches.

Note: Plug-and-play software configuration model does not allow overlap of different address ranges.

Therefore, the AGP Graphics Aperture and AGP Memory Address Range are independent address
ranges that may abut, but cannot overlap one another.

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4.3.

System Management Mode (SMM) Memory Range

The MCH-M supports the use of main memory as System Management RAM (SMRAM) enabling the
use of System Management Mode. The MCH-M supports three SMRAM options: Compatible SMRAM
(C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management
RAM (SMRAM) space provides a memory area that is available for the SMI handler's and code and data
storage. This memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. MCH-M provides three SMRAM options:

· Below 1 MByte option that supports compatible SMI handlers.
· Above 1 MByte option that allows new SMI handlers to execute with write-back cacheable

SMRAM.

· Optional larger write-back cacheable T_SEG area from 128 KB to 1MB in size above 1 MByte that

is reserved from the highest area in system DRAM memory. The above 1 MByte solutions require
changes to compatible SMRAM handlers' code to properly execute above 1 MByte.

Note: Masters from the hub interface and AGP are not allowed to access the SMM space.

4.3.1.

SMM Space Definition

The addressed SMM space and the DRAM SMM space define SMM space. The addressed SMM space
is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM space
is defined as the range of physical DRAM memory locations containing the SMM code. SMM space can
be accessed at one of three transaction address ranges: Compatible, High and TSEG. The Compatible
and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same
address range. Since the High SMM space is remapped the addressed and DRAM SMM space is a
different address range. Note that the High DRAM space is the same as the Compatible Transaction
Address space. Therefore the table below describes three unique address ranges:

· Compatible Transaction Address (Adr C)
· High Transaction Address (Adr H)
· TSEG Transaction Address (Adr T)

These abbreviations are used later in the table describing SMM Space Transaction Handling.

Table 26. SMM Space

SMM Space Enabled

Transaction Address Space (Adr)

DRAM Space (DRAM)

Compatible©

A0000h to BFFFFh

High (H)

0FEDA0000h to 0FEDBFFFFh

A0000h to BFFFFh

TSEG (T)

(TOM-TSEG_SZ) to TOM

Note: High SMM: Note that this is different than in previous chipsets. In previous chipsets the High segment

was the 384-KB region from A0000h to FFFFFh. However, C0000h to FFFFFh was not practically
useful so it is deleted in MCH-M.

TSEG SMM: Note that this is different than in previous chip sets. In previous chip sets the TSEG
address space was offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just
under the TOM. In the MCH-M 256 MB do not offset the TSEG region and it is not remapped.

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4.3.2.

SMM Space Restrictions

If any of the following conditions are violated the results of SMM accesses are unpredictable and may
cause the system to hang:

1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space assigned to system

DRAM, the AGP aperture range, or to any "PCI" devices (including hub interface and AGP
devices). This is a BIOS responsibility.

3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available

DRAM. This is a BIOS responsibility.

5. Any address translated through the AGP Aperture GTLB must not target DRAM from 000A0000h

to 000FFFFFh.

4.4.

I/O Address Space

The Intel

845MP/845MZ Chipset MCH-M does not support the existence of any other I/O devices beside

itself on the system bus. The MCH-M generates either hub interface A or AGP bus cycles for all
processor I/O accesses. The MCH-M contains two internal registers in the processor I/O space,
Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register
(CONFIG_DATA). These locations are used to implement configuration space access mechanism and as
described in the Configuration Register section.

The processor allows 64K+3 bytes to be addressed within the I/O space. The MCH-M propagates the
processor I/O address without any translation on to the destination bus and therefore provides
addressability for 64K+3 byte locations. Note that the upper three locations can be accessed only during
I/O address wrap-around when signal A16# address signal is asserted. A16# is asserted on the system
bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also
asserted when an I/O access is made to 2 bytes from address 0FFFFh.

The I/O accesses (other than ones used for configuration space access) are forwarded normally to the hub
interface A unless they fall within the AGP I/O address range as defined by the mechanisms explained
below. The MCH-M will not post I/O write cycles to IDE.

The MCH-M never responds to I/O or configuration cycles initiated on AGP or any of the hub interfaces.
Hub interface transactions requiring completion are terminated with "master abort" completion packets
on the hub interfaces. Hub interface write transactions not requiring completion are dropped. AGP/PCI
I/O reads are never acknowledged by the MCH-M.

4.5.

MCH-M Decode Rules and Cross-Bridge Address

Mapping

The address map described above applies globally to accesses arriving on any of the three interfaces i.e.
Host bus, the hub interface A or AGP.

4.5.1.

Decode Rules for the Hub Interface A

The MCH-M accepts accesses from the hub interface A with the following address ranges:

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· All memory read and write accesses to Main DRAM (except SMM space).
· All memory write accesses from the hub interface A to AGP memory range defined by MBASE1,

MLIMIT1, PMBASE1, and PMLIMIT1.

· All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
· Memory writes to VGA range on AGP if enabled.

All memory reads from the hub interface A that are targeted > 4 GB memory range will be terminated
with Master Abort completion, and all memory writes (>4 GB) from the hub interface A will be ignored.

4.5.2.

AGP Interface Decode Rules

Cycles Initiated Using AGP FRAME# Protocol

The MCH-M does not support any AGP FRAME# access targeting the hub interface A. The MCH-M
will claim AGP initiated memory read and write transactions decoded to the main DRAM range or the
Graphics Aperture range. All other memory read and write requests will be master-aborted by the AGP
initiator as a consequence of MCH-M not responding to a transaction.

The MCH-M forwards AGP/PCI accesses addressed to the DOS Compatibility ranges between
0C0000h-0FFFFFh to main memory, regardless of the configuration of the Programmable Attributes
Map registers (PAM registers). The PAM registers govern the destination of host CPU accesses to the
DOS Compatibility ranges but do not similarly affect the destination of AGP/PCI accesses to this range.
MCH-M will forward to main memory any AGP/PCI initiated access to the PAM areas. Note that the
MCH-M may hang if an AGP originated access occurs to a Read Disabled or Write Disabled PAM
segment. Therefore, the following critical restriction is placed on the programming of the PAM regions:
at the time that an AGP accesses to a PAM region occurs, the targeted PAM segment must be
programmed to be both readable and writable. If an AGP master issues an I/O, PCI Configuration or PCI
Special Cycle transaction, the MCH-M will not respond and cycle will result in a master-abort.

Cycles Initiated Using AGP PIPE# or SBA Protocol

All cycles must reference main memory i.e. main DRAM address range (including PAM) or Graphics
Aperture range (also physically mapped within DRAM but using different address range). AGP accesses
to SMM space are not allowed. AGP protocol cycles that target DRAM are not snooped on the host bus,
even if they fall outside of the AGP aperture range.

If a cycle is outside of main memory range then it will terminate as follows:

· Reads: remapped to memory address 0h, data returned from address 0h, and IAAF error bit set in

ERRSTS register in device #0

· Writes: dropped "on the floor" i.e. terminated internally without affecting any buffers or main

memory

AGP Accesses to MCH-M that Cross Device Boundaries

The MCH-M will disconnect AGP FRAME# transactions on 4KB boundaries.

AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. Read accesses crossing out
of DRAM will return invalid data, and the IAAF Error bit will be set. Write accesses crossing out of
DRAM will be discarded, and the IAAF Error bit will be set.

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5. Functional

Description

5.1.

Host Interface Overview

The Intel

845MP/845MZ Chipset MCH-M supports the Mobile Intel Pentium 4 Processor-M at 100-

MHz bus frequency; the address signals run at 200 MT/s for a maximum address queue rate of 50M
addresses/sec. The data is quad pumped and an entire 64B cache line can be transferred in two bus
clocks. At 100-MHz bus frequency, the data signals run at 400 MT/s for a maximum bandwidth of 3.2
GB/s. A 12-deep IOQ is supported by the 845MP/845MZ Chipset.

The Intel

845MP/845MZ Chipset MCH-M supports two outstanding deferred transactions on the system

bus. The two transactions must target different IO interfaces as only one deferred transaction can be
outstanding to any single IO interface at a time.

5.1.1.

Dynamic Bus Inversion

The Intel

845MP/845MZ Chipset MCH-M supports Dynamic Bus Inversion (DBI) when driving, and

when receiving data from the Host Bus. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the power consumption of the MCH-M.
DINV[3:0]# indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped
data phase:

Table 27. Relation of DBI Bits to Data Bits

DINV[3:0]# Data

Bits

DBI0# HD[15:0]#

DIBI1# HD[31:16]#

DBI2# HD[47:32]#

DBI3# HD[63:48]#

Whenever the CPU or the MCH-M drives data, each 16-bit segment is analyzed. If more than 8 of the 16
signals would normally be driven low on the bus the corresponding DBI# signal will be asserted and the
data will be inverted prior to being driven on the bus. Whenever the CPU or the MCH-M receives data it
monitors DBI[3:0]# to determine if the corresponding data segment should be inverted.

5.1.2.

System Bus Interrupt Delivery

The Mobile Intel Pentium 4 Processor-M supports System Bus interrupt delivery, but they do not support
the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the System
Bus as "Interrupt Message Transactions". In an Intel

845MP/845MZ Chipset platform, System Bus

interrupts may originate from the processor on the System Bus, or from a downstream device on hub
interface, or AGP. In the later case the MCH-M drives the "Interrupt Message Transaction" onto the
System Bus.

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In an Intel

845MP/845MZ Chipset platform and its interrupts are generated as upstream hub interface

Memory Writes. Furthermore, PCI 2.2 defines MSI's (Message Signaled Interrupts) that are also in the
form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on it's PCI bus.
The MSI may be directed directly to the System bus. The target of an MSI is dependent on the address of
the interrupt Memory Write. The Intel

845MP/845MZ Chipset MCH-M forwards inbound hub interface

and AGP (PCI semantic only) Memory Writes to address 0FEEx_xxxxh, to the System bus as "Interrupt
Message Transactions".

5.1.3.

Upstream Interrupt Messages

The MCH-M accepts message based interrupts from AGP (PCI semantics only) or its hub interface and
forwards them to the System bus as Interrupt Message Transactions. The interrupt messages presented to
the MCH-M are in the form of Memory Writes to address 0FEEx_xxxxh. At the hub interface or AGP
interface the Memory Write interrupt message is treated like any other Memory Write; it is either posted
into the inbound data buffer (if space is available) or retried (if data buffer space is not immediately
available). Once posted, the Memory Write from AGP or the hub interface, to address 0FEEx_xxxxh, is
decoded as a cycle that needs to be propagated by the MCH-M to the System bus as an Interrupt
Message Transaction.

5.2.

System Memory Interface

5.2.1.

DDR Interface Overview

The Intel

845MP Chipset MCH-M supports DDR at 200 and 266 MHz and includes support for:

· Up to 1 GB of PC2100 DDR
· PC2100, unbuffered, 200-pin DDR SO-DIMMs
· Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided b
· Configurable optional ECC

The Intel

845MZ Chipset MCH-M supports DDR at 200 MHz and includes support for:

· Up to 512 MB of PC1600 DDR
· PC1600, unbuffered, 200-pin DDR SO-DIMMs
· Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided
· Configurable optional ECC

The 2 bank select lines SBS[1:0] and the 13 Address lines SMA[12:0] allow the Intel

845MP/845MZ

MCH-M to support 64 bit wide SO-DIMMs using 64-Mb, 128-Mb, 256-Mb, and 512-Mb DDR
technology. While address lines SMA[9:0] determine the starting address for a burst, burst lengths can
be 2, 4, or 8. Four chip selects SCS# lines allow a maximum of two rows of single-sided DDR SO-
DIMMs and four rows of double-sided DDR SO-DIMMs.

Intel

845MP/845MZ main memory controller targets CAS latencies of 2 and 2.5 for DDR. Intel

845MP/845MZ provides refresh functionality with a programmable rate (normal DDR rate is 1
refresh/15.6 us). For write operations of less than a Qword in size, the MCH-M will perform a byte-wise
write.

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5.2.2.

Memory Organization and Configuration

Refer to Section 1.3.

5.2.2.1.

Configuration Mechanism for SO-DIMMs

Detection of the type of DDR installed on the SO-DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 200-pin SO- DIMM specification. This uses the SCL, SDA, and
SA[2:0] pins on the SO-DIMMs to detect the type and size of the installed SO-DIMMs. No special
programmable modes

are provided on Intel

845MP/845MZ MCH-M for detecting the size and type of

memory installed. Type and size detection must be done via the serial presence detection pins.

5.2.2.1.1.

Memory Detection and Initialization

Before any cycles to the memory interface can be supported, the Intel

845MP/845MZ MCH-M DDR

registers must be initialized. The Intel

845MP/845MZ MCH-M must be configured for operation with

the installed memory types. Detection of memory type and size is done via the System Management Bus
(SMB) interface on the ICH3-M. This two-wire bus is used to extract the DDR type and size information
from the Serial Presence Detect port on the DDR SO-DIMMs. DDR SO-DIMMs contain a 5 pin Serial
Presence Detect interface, including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the
SMBus bus have a seven-bit address. For the DDR SO-DIMMs, the upper four bits are fixed at 1010.
The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the
System Management Bus on the ICH3-M. Thus, data is read from the Serial Presence Detect port on the
SO-DIMMs via a series of IO cycles to the south bridge. BIOS essentially needs to determine the size
and type of memory used for each of the rows of memory in order to properly configure the Intel

845MP/845MZ MCH-M memory interface.

5.2.2.1.2.

SMBus Configuration and Access of the Serial Presence Detect Ports

Refer to the Intel

ICH3-M Datasheet for more detail.

5.2.2.1.3.

Memory Register Programming

This section provides an overview of how the required information for programming the DDR registers is
obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence Detect ports are
used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis), DDR
Timings, Row Sizes, and Row Page Sizes. The following table lists a subset of the data available
through the onboard Serial Presence Detect ROM on each SO-DIMM.

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Table 28. Data Bytes on SO-DIMM Used for Programming DRAM Registers

Byte Function

Memory Type (SDR SDRAM or DDR SDRAM)

# of Row Addresses, not counting Bank Addresses

# of Column Addresses

# of SO-DIMM banks

ECC, no ECC

12 Refresh

Rate/Type

# Banks on each Device

The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively
provide enough data for programming the Intel

845MP/845MZ MCH-M SDRAM registers.

5.2.3.

DRAM Performance Description

The overall memory performance is controlled by the DRAM timing register, which pipelines depth used
in Intel

845MP/845MZ MCH-M, memory speed grade and the type of SDRAM used in the system.

Besides this, the exact performance in a system is also dependent on the total memory supported,
external buffering and memory array layout. The most important contribution to overall performance by
the System Memory controller is to minimize the latency required to initiate and complete requests to
memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One
measure of performance is the total flight time to complete a cache line request. A true discussion of
performance really involves the entire chipset, not just the System Memory controller.

5.2.3.1.

Data Integrity (ECC)

The Intel

845MP/845MZ MCH-M supports single-bit Error Correcting Code (or Error Checking and

Correcting) and multiple-bit EC (Error Checking) on the main memory interface. The Intel

845MP/845MZ MCH-M generates an 8-bit code word for each 64-bit Qword of memory. Intel

845MP/845MZ MCH-M performs two Qword writes at a time so two 8-bit codes are sent with each
write. Since the code word covers a full Qword, writes of less than a Qword require a read-merge-write
operation. Consider a Dword write to memory. In this case, when in ECC mode, the Intel

845MP/845MZ MCH-M will read the Qword where the addressed Dword will be written, merge in the
new Dword, generate a code covering the new Qword and finally write the entire Qword and code back
to memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected
before merging the new Dword. The Intel

845MP/845MZ MCH-M also supports another data integrity

mode, EC (Error Checking) mode. In this mode, the Intel

845MP/845MZ MCH-M generates and stores

a code for each Qword of memory. It then checks the code for reads from memory but does not correct
any errors that are found. Thus, the read performance hit associated with ECC is not incurred.

5.3.

AGP Interface Overview

The Intel

845MP/845MZ Chipset MCH-M supports 1.5 V AGP 1x/2x/4x devices. The AGP signal

buffers are 1.5 V drive/receive (buffers are not 3.3-V tolerant). The MCH-M supports 2x/4x source
synchronous clocking transfers for read and write data, and sideband addressing. The MCH-M also
supports 1x, 2x and 4x clocking for Fast Writes initiated from the MCH-M (on behalf of the processor).

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AGP PIPE# or SBA[7:0] protocol transactions to DRAM do not get snooped and are, therefore, not
coherent with the processor caches. AGP FRAME# protocol transactions to DRAM are snooped. AGP
PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access
from an AGP master to the hub interface are also not supported. Only AGP FRAME# memory writes
from the hub interface are supported.

5.3.1.

AGP Target Operations

The MCH-M supports AGP cycles targeting main memory only. The MCH-M supports interleaved AGP
PIPE#] and AGP FRAME# transactions, or AGP SBA[7:0] and AGP FRAME# transactions.

Table 29. AGP Commands Supported by the MCH-M When Acting as an AGP Target

MCH-M Host Bridge

AGP

Command

C/BE[3:0]#

Encoding

Cycle Destination

Response as PCIx Target

Read

0000

Main Memory

Low Priority Read

0000

The Hub interface

Complete with random data; does not go to the hub
interface

Hi-Priority Read

0001

Main Memory

High Priority Read

0000

The Hub interface

Complete with random data; does not go to the hub
interface

Reserved 0010

N/A

Response

Reserved 0011

N/A

Response

Write

0100

Main Memory

Low Priority Write

0100

The Hub interface

Cycle goes to DRAM with BE's inactive; does not go to
the hub interface

Hi-Priority Write

0101

Main Memory

High Priority Write

0101

The Hub interface

Cycle goes to DRAM with BE's inactive; does not go to
the hub interface

Reserved 0110

N/A

Response

Reserved 0111

N/A

Response

Long Read

1000

Main Memory

Low Priority Read

The Hub interface

Complete with random data; does not go to the hub
interface

Hi-Priority Long
Read

1001

Main Memory

High Priority Read

The Hub interface

Complete with random data; does not go to the hub
interface

Flush

1010

MCH-M

Complete with QW of Random Data

Reserved 1011

N/A

Response

Fence

1100

MCH-M

No Response - Flag inserted in MCH-M request queue

Reserved 1101

N/A

Response

Reserved 1110

N/A

Response

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MCH-M Host Bridge

AGP

Command

C/BE[3:0]#

Encoding

Cycle Destination

Response as PCIx Target

Reserved 1111

N/A

Response

NOTE: N/A refers to a function that is not applicable.

As a target of an AGP cycle, the MCH-M supports all memory read and write transactions targeted at
main memory (summarized in the table above). The MCH-M supports both normal and high priority read
and write requests. The MCH-M does not support AGP cycles to the hub interface. PIPE# and SBA
cycles do not require coherency management and all AGP initiator accesses to main memory using AGP
PIPE# or SBA protocol are treated as non-snoopable cycles. These accesses are directed to the AGP
aperture in main memory that should be programmed as either uncacheable (UC) memory or write
combining (WC) in the processor's MTRRs.

5.3.2.

AGP Transaction Ordering

The MCH-M observes transaction ordering rules as defined by the AGP Interface Specification Rev 2.0.

5.3.3.

AGP Signal Levels

The 1x/2x/4x data transfers use 1.5-V signaling levels as described in the AGP 2.0 specification.

5.3.4.

4x AGP Protocol

In addition to the 1x and 2x AGP protocol, the MCH-M supports 4x AGP read and write data transfers
and 4x sideband address. The 4x operation is compliant with the AGP 2.0 specification.

The MCH-M indicates that it supports 4x data transfers through RATE[2] (bit 2) of the AGP Status
Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system initialization,
the MCH-M performs AGP read/write data transactions using 4x protocol. This bit is not dynamic. Once
this bit is set during initialization, the data transfer rate may not be changed.

The 4x data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4x data
transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred on every 66-
MHz clock edge. The minimum throttleable block size remains four 66-MHz clocks, which means 64
bytes of data are transferred per block. Three additional signal pins are required to implement the 4x data
transfer protocol. These signal pins are complementary data transfer strobes for the AD bus (2) and the
SBA bus (1).

5.3.5. Fast

Writes

MCH-M supports 2x and 4x Fast Writes from the MCH-M to the graphics controller on AGP. Fast Write
operation is compliant with the AGP 2.0 specification.

The MCH-M will not generate Fast Back to Back (FB2B) cycles in 1x mode, but will generate FB2B
cycles in 2x and 4x Fast Write modes.

To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4 of the
AGP Command Register), must be set to 1.

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Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is
both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the
bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4x strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2x strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using standard
PCI protocol. Note that only one of the three DATA_RATE bits may be set by initialization software.
This is summarized in the following table.

Table 30. Fast Write Initialization

FWEN DATA_RATE

[2]

DATA_RATE

[1]

DATA_RATE

[0]

MCH-M =>AGP Master Write

Protocol

0 X x x

1 0 0 1

1 0 1 0

Strobing

1 1 0 0

Strobing

5.3.6.

AGP FRAME# Transactions on AGP

The MCH-M accepts and generates AGP FRAME# transactions on the AGP bus. The MCH-M
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.

5.3.6.1.

MCH-M Target and Initiator Operations for AGP FRAME# Transactions

The following table summarizes MCH-M target operation for AGP FRAME# initiators. The only cycles
that will be claimed are memory accesses to main memory.

Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target

MCH-M

PCI Command

C/BE[3:0]# Encoding

Cycle Destination

Response as aFRAME#

Target

Interrupt Acknowledge

0000

N/A

No Response

Special Cycle

0001

N/A

No Response

I/O Read

0010

N/A

No Response

I/O Write

0011

N/A

No Response

Reserved 0100

N/A

Response

Reserved 0101

N/A

Response

Memory Read

0110

Main Memory

Read

0110

The Hub interface

No Response

Memory Write

0111

Main Memory

Post Data

0111

The Hub interface

No Response

Reserved 1000

N/A

Response

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MCH-M

PCI Command

C/BE[3:0]# Encoding

Cycle Destination

Response as aFRAME#

Target

Reserved 1001

N/A

Response

Configuration

N/A No

Response

Configuration

Write 1011

N/A No

Response

Memory Read Multiple

1100

Main Memory

Read

1100

The Hub interface

No Response

Dual Address Cycle

1101

N/A

No Response

Memory Read Line

1110

Main Memory

Read

1110

The Hub interface

No Response

Memory Write and
Invalidate

1111 Main

Memory

Post

Data

1111

The Hub interface

No Response

NOTE: N/A refers to a function that is not applicable.

As a target of an AGP FRAME# cycle, the MCH-M only supports the following transactions:

· Memory Read. Recommended for reads of 32 bytes or less.
· Memory Read Line, and Memory Read Multiple. These commands are supported identically by the

MCH-M and allow the MCH-M to continuously supply data during MRL and MRM burst.
Recommended for reads of more than 32 bytes. The MCH-M does not support reads of the hub
interface bus from AGP.

· Memory Write and Memory Write and Invalidate. These commands are aliased and processed

identically. The MCH-M does not support writes of the hub interface bus from AGP.

· Other Commands. Other commands such as I/O R/W and Configuration R/W are not supported by

the MCH-M as a target and result in master abort.

· Exclusive Access. The MCH-M does not support PCI locked cycles as a target.
· Fast Back-to-Back Transactions. MCH-M as a target supports fast back-to-back cycles from an

AGP FRAME# initiator.

As an initiator of AGP FRAME# cycle, the MCH-M only supports the following transactions:

· Memory Read and Memory Read Line. MCH-M uses these commands to support read requests from

host to AGP. MCH-M does not support memory reads from the hub interface to AGP.

· Memory Read Multiple. This command is not supported by the MCH-M as an AGP FRAME#

initiator.

· Memory Write. MCH-M initiates AGP FRAME# write cycles on behalf of the host or the hub

interface. MCH-M does not issue Memory Write and Invalidate as an initiator. MCH-M does not
support write merging or write collapsing. MCH-M allows non-snoopable write transactions from
the hub interface to the AGP bus.

· I/O Read and Write. I/O reads and writes from the host are sent to the AGP bus if they fall within

the I/O base and limit address range for the AGP bus as programmed in the MCH-M's PCI
configuration registers. All other host-initiated I/O accesses that do not correspond to this

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programmed address range are forwarded to the hub interface. MCH-M does not support I/O
accesses from the hub interface to AGP.

· Exclusive Access. MCH-M does not issue a locked cycle on the AGP bus on behalf of either the host

or the hub interface. The hub interface and host locked transactions to AGP are initiated as unlocked
transactions by the MCH-M on the AGP bus.

· Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1

Configuration Cycles. MCH-M does not support configuration reads or writes from the hub
interface to AGP.

· Fast Back-to-Back Transactions. MCH-M as an initiator does not perform fast back-to-back cycles.

MCH-M Retry/Disconnect Conditions

The MCH-M generates retry/disconnect according to the AGP Specification rules when being accessed
as a target by the AGP master using a FRAME# protocol cycle.

Delayed Transactions

When an AGP FRAME#-to-DRAM read cycle is retried by the MCH-M, it is processed internally as a
Delayed Transaction.

The MCH-M supports the Delayed Transaction mechanism on the AGP target interface for the
transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI 2.1
Specification. The process of latching all information required to complete the transaction, terminating
with Retry, and completing the request without holding the master in wait-states is called a Delayed
Transaction. The MCH-M latches the Address and Command when establishing a Delayed Transaction.
The MCH-M generates a Delayed Transaction on the AGP only for AGP FRAME# to DRAM read
accesses. The MCH-M does not allow more than one Delayed Transaction access from AGP at any time.

5.4.

Power and Thermal Management

An Intel

845MP/845MZ Chipset platform is compliant with the following specifications:

· APM Rev 1.2
· ACPI Rev 1.0b
· ACPI Rev 2.0
· PCI Power Management Rev 1.0
· PC'99, Rev 1.0
· PC'99A
· PC'01, Rev 1.0

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5.4.1. Various

States

Table 32. Power Management State Combinations

Global (G)

state

Sleep (S)

State

CPU (C)

State

CPU

Clock

(FCLK)

MCH-M

Host Clock

(DCLK)

System Memory

Processor State

G0 S0 C0 On On

Full

G0 S0 C1 On On

Auto-Halt

G0 S0 C2 On On

Stop

Grant

Off

PwrDown Self Refresh

Deep Sleep

Off

PwrDown Self Refresh

DeepER Sleep

S1M

N/A

Off

PwrDown Self Refresh

N/A

Off

PwrDown Self Refresh

N/A

Off

PwrDown Self Refresh

N/A

Off

PwrDown Self Refresh

G3 N/A N/A Off Off

Off

5.4.2.

General Description of Supported CPU States

· C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is

deasserted and the processor core is active. The processor can service snoops and maintain cache
coherency in this state.

· C1 (Auto Halt): The first level of power reduction occurs when the processor executes an Auto-

Halt instruction. This stops the execution of the instruction stream and reduces the processor's
power consumption. The processor can service snoops and maintain cache coherency in this state.

· C2 (Stop Grant): To enter this low power state, STPCLK# is asserted. The processor can still

service snoops and maintain cache coherency in this state.

· C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The MCH-M assumes

that no AGP, AGP/PCI, or HubLink cycles (except special cycles) will occur while the MCH-M is
in this state. The processor cannot snoop its caches to maintain coherency while in the C3 state.

· C4 (DeepER Sleep): The C4 state appears to Intel

845MP/845MZ as identical to the C3 state, but

in this state the processor core voltage is lowered. There are no internal events in Intel

845MP/845MZ for the C4 state that differ from the C3 state.

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5.4.3.

General Description of ACPI System States

· S0 (Awake): In this state all power planes are active.
· S1-M (Powered on Suspend for Mobile Systems): Power is maintained to the CPU and all system

components, but most clocks are stopped by the clock synthesizer.

· S2: ACPI S2 state is not supported in the Intel 845MP/845MZ Chipset platform.
· S3 (Suspend To RAM): The next level of power reduction occurs when the clock synthesizer and

core well power planes for the processor and chipset are shut down, but the main memory power
plane and the ICH3-M resume well remain active. This is the Suspend To RAM (STR) state. All
clocks from synthesizers are shut down during the S3 state.

· S4 (Suspend to Disk) and S5 (Soft Off): In these states the main memory power plane is shut

down in addition to the clock synthesizer and core well power planes for the processor and chipset.
The ICH3-M resume well is still powered.

G3 (Mechanical Off): In this state only the RTC (Real Time Clock) well is powered. The system
can only be reactivated via the power switch.

5.4.4. Power

Transitions

Table 33. Intel

845MP/845MZ Power Transitions

ACPI

State/Feature

CO C1

C2/S1D

C3/C4

S1M

DDR Active/Standby

& Nap

Active/Standby

& Nap

Nap, Active, &

Standby

Power-down Power-down

RAC Active

Active Active

Power-down

DRCG Running Running Running

Clock

Stop

Mode

Power-down

Clock Gating

Yes (during

writes)

Yes (during

writes)

Yes (enabled

during snoops)

Yes Yes

GTL Control

Buffer Sense

Amp Disable

No No No Yes Yes

Hublink Interface

Active

Power-down

REQ1

CPU

PLL Running Running Running Running Running

AGP/Hublink

PLL

Running Running Running Running Running

Intel SpeedStep

Technology

Transition

No No No No No

Dynamic RAC

Power

Reduction

Enabled Enabled Enabled Enabled Enabled

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5.4.5. Intel

SpeedStep

Technology

Intel SpeedStep

technology allows the system to operate in multiple performance states. Intel SpeedStep

technology offers two CPU/system operational modes:

Maximum Performance Mode: Maximum CPU Core Frequency.

Battery Optimized Mode: Reduced CPU core frequency to extend battery life.

Intel SpeedStep technology transitions states only when AC power is connected or disconnected. It
transitions by changing the CPU PLL multiplier, which can only be done in the Deep Sleep CPU state
(clock going to the CPU is stopped), which is the C3 CPU power state.

Most of the control for Intel SpeedStep technology is done in the ICH3-M. However, the MCH-M must
cooperate on certain functions.

5.5. MCH-M

Clocking

The CK408 compliant clock synthesizer supports the Intel 845MP/845MZ Chipset. For details refer to
the Intel

Pentium

4 Processor in the 478 Pin Package and Intel

845MP/845MZ Chipset Platform

Design Guide.

5.6.

MCH-M System Reset and Power Sequencing

Please refer to the Intel

Pentium

4 Processor in the 478 Pin Package and Intel

845MP/845MZ

Chipset Platform Design Guide for details.

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6. Electrical

Characteristics

This chapter contains the absolute maximum operating ratings, power characteristics, and DC
characteristics for the 845MP/845MZ MCH-M.

6.1.

Absolute Maximum Ratings

Table 34 lists the Intel 845MP/845MZ Chipset MCH-M maximum environmental stress ratings.
Functional operation at the absolute maximum and minimum is neither implied nor guaranteed.
Functional operating parameters are listed in the AC and DC tables.

Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are

stress ratings only. Operating beyond the "operating conditions" is not recommended and extended
exposure beyond "operating conditions" may affect reliability.

Table 34. Absolute Maximum Ratings

Symbol Parameter Min

Max

Unit

Notes

die

Die Temperature under Bias (with heatsink)

0 98

°C

die

Die Temperature under Bias (without heatsink)

104

°C

storage

Storage

Temperature

-55 150

°C

VCC1_5

1.5 V Supply Voltage with respect to Vss

-0.72

2.69

VCC1_8

1.8 V Supply Voltage with respect to Vss

-0.88

2.5

VCCSM

2.5 V DDR Supply Voltage with respect to Vss

-3.60

6.3

VTT

AGTL+ buffer DC input voltage with respect to Vss

-0.55

2.3

IL,

(DDR)

Voltage on 2.5 V DDR tolerant input pins with
respect to Vss

-3.60 6.30 V

6.2. Thermal

Characteristics

The Intel 845MP/845MZ Chipset MCH-M is designed for operation at die temperatures between 0

°C

and 104

°C. The thermal resistance of the package is given in Table 35.

Table 35. Intel 845MP/845MZ Chipset MCH-M Package Thermal Resistance

Parameter

Airflow Velocity in Meters/Second

0 m/s

1 m/s

(

°C/Watt)** 0.5

1.8

(

°C/Watt)** 20.0

17.3

NOTE: ** Typical value measured in accordance with EIA/JESD 51-2 testing standard.

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6.3. Power

Characteristics

Table 36. Power Characteristics

Symbol Parameter Min

Typ

Max

Unit

Notes

TDP

Thermal Design Power

4.6

VTT

Intel 845MP/845MZ Chipset MCH-M
VTT supply Current

2.4

A 2

VCC1_5_CORE

1.5 V Core Supply Current

1.9

2,3

VCC1_5_AGP

1.5 V AGP Supply Current

0.37

2,3

VCC1_8

1.8 V Hub Interface Supply Current

0.20

VCCSM

DDR System Memory Interface (2.5
V) Supply Current

1.9

A 2

SUS_VCCSM

DDR System Memory Interface (2.5
V) Standby Supply Current

SDREF

DDR System Memory Interface
Reference Voltage (1.25 V) Supply
Current

SUS_SDREF

DDR System Memory Interface
Reference Voltage (1.25 V) Standby
Supply Current

TTRC

DDR System Memory Interface
Resister Compensation Voltage (1.25
V) Supply Current

SUS_TTRC

DDR System Memory Interface
Resister Compensation Voltage (1.25
V) Standby Supply Current

NOTES:

1. This spec is the Thermal Design Power and it is the estimated maximum possible expected power generated in

a component by a realistic application. It is based on extrapolations in both hardware and software technology
over the life of the component. It does not represent the expected power generated by a power virus. Studies
by Intel indicate that no application will cause thermally significant power dissipation exceeding this
specification, although it is possible to concoct higher power synthetic workloads that write but never read.
Under realistic read/write conditions, this higher power workload can only be transient, and is accounted in the
Icc (Max) spec.

2. Pre-silicon specs have a +20% / -10% tolerance.
3. These current levels can happen simultaneously, and can be summed into one supply.

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7. Signal

Groups

The signal description includes the type of buffer used for the particular signal.

AGTL+

Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete
details. The Intel 845MP/845MZ Chipset MCH-M integrates most AGTL+ termination
resistors.

AGP

AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling
Environment DC and AC Specifications. The buffers are not 3.3 V tolerant.

HI CMOS Hub Interface 1.8 V CMOS buffers.

DDR CMOS DDR System memory 2.5 V CMOS buffers.

Table 37. Signal Groups

Signal Group

Signal Type

Signals

Notes

Host Interface Signal Groups

(a)

AGTL+ I/O

ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#,

DRDY#,

HA[31:3]#, HADSTB[1:0] #,
HD[63:0]#,HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#,
HITM#, HREQ[4:0]#

(b) AGTL+

Common

Clock Output

BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#

Common

Clock Input

HLOCK#

(d) Host

Reference

Voltages

HVREF, HSWING[1:0]

AGP Interface Signal Groups

(e)

AGP I/O

AD_STB0, AD_STB0#, AD_STB1, AD_STB1#,
G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#,
G_DEVSEL#, G_AD[31:0], G_CBE[3:0]#, G_PAR

(f)

AGP Input

PIPE#, SBA[7:0], RBF#, WBF#, SB_STB,
SB_STB#, G_REQ#

(g)

AGP Output

ST[2:0], G_GNT#

(h) AGP

Reference

Voltage

AGPREF

Hub Interface Signal Groups

(i) Hub

Interface's

CMOS I/O

HI_[10:0], HI_STB, HI_STB#

(j) Hub

Interface

Reference
Voltage

HI_REF

DDR Interface Signal Groups

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8. DC

Characteristics

Table 38. DC Characteristics

Symbol Signal

Group

Parameter Min

Nom

Max

Unit

Notes

I/O Buffer Supply Voltage

VCCSM

(u)

DDR I/O Supply Voltage

2.375

2.5

2.625

VCC1_8

(t)

1.8V I/O Supply Voltage

1.71

1.8

1.89

VCC1_5

(s)

Core and AGP Voltage

1.425

1.5

1.575

VTT

(r)

Host AGTL+ Termination
Voltage

N/A

N/A 1.75 V

VTTactive

(r)

BK-M Active Range

1.0-5%

1.5+5%

VTTsleep

BK-M Inactive Range

0.85-2.5%

1.5+2.5%

Reference Voltages

HVREF

(d)

Host Address and Data
Reference Voltage

2/3 x VTT 2%

2/3 x VTT

2/3 x VTT + 2%

HSWING (d) Host

Compensation

Reference Voltage

1/3 x VTT 2%

1/3 x VTT

1/3 x VTT + 2%

HIREF

(j)

Hub Interface Reference
Voltage

0.48 x VCC1_8

1/2 x VCC1_8

0.52 x VCC1_8

SDREF

(n)

DDR Reference Voltage

0.48 x VCCSM

1/2 x VCCSM

0.52 x VCCSM

AGPREF

(h)

AGP Reference Voltage

0.48 x VCC1_5 1/2 x VCC1_5

0.52 x VCC1_5

Host Interface

IL_H

(a,c)

Host AGTL+ Input Low
Voltage

(2/3 x VTT) 0.1

IH_H

(a,c)

Host AGTL+ Input High
Voltage

(2/3 x VTT) + 0.1

OL_H

(a,b)

Host AGTL+ Output Low
Voltage

(1/3 x VTT) + 0.1

OH_H

(a,b)

Host AGTL+ Output High
Voltage

VTT-0.1

OL_H

(a,b)

Host AGTL+ Output Low
Current

VTT

max

/ 0.75Rtt

min

mA Rtt

min

=45

LEAK_H

(a,c)

Host AGTL+ Input
Leakage Current

±15

µA V

<Vpad<

VTT

PAD

(a,c)

Host AGTL+ Input
Capacitance

1.0

DDR Interface

IL(DC)

(k,m)

DDR Input Low Voltage

SDREF

0.15

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Symbol Signal

Group

Parameter Min

Nom

Max

Unit

Notes

IH(DC)

(k,m)

DDR Input High Voltage

SDREF

+ 0.15

IL(AC)

(k,m)

DDR Input Low Voltage

SDREF

0.31

IH(AC)

(k,m)

DDR Input High Voltage

SDREF

+ 0.31

DDR Interface cont.

(k,l)

DDR Output Low Voltage

0,975

(k,l)

DDR Output High Voltage

1.80

(k,l)

DDR Output Low Current

9.375

(k,l)

DDR Output High Current

-9.375

Leak

(k,m)

Input Leakage Current

sus_pullup

(k,m)

Internal Pull-up to Vccsm
in suspend

K 2.

I/O

(k, l, m) DDR Input/Output Pin

Capacitance

4.690 5.370

1.5 V AGP Interface

IL_A

(e,f)

AGP Input Low Voltage

0.4 x VCC1_5

IH_A

(e,f)

AGP Input High Voltage

0.6 x VCC1_5

OL_A

(e,g)

AGP Output Low Voltage

0.15 x VCC1_5

OH_A

(e,g)

AGP Output High Voltage

0.85 x VCC1_5

OL_A

(e,g)

AGP Output Low Current

OL_A

max

OH_A

(e,g)

AGP Output High Current

-0.2

OH_A

max

LEAK_A

(e,f)

AGP Input Leakage
Current

±15

µA 0<Vin<

VCC1_5

IN_A

(e,f)

AGP Input Capacitance

1.32

1.92

1.8 V Hub Interface

IL_HI

(i)

Hub Interface Input Low
Voltage

HIREF - 0.15

IH_HI

(i)

Hub Interface Input High
Voltage

HIREF + 0.15

OL_HI

(i)

Hub Interface Output Low
Voltage

0.1 x VCC1_8

= 1 mA

OH_HI

(i)

Hub Interface Output High
Voltage

0.9 x VCC1_8

= 1 mA

OL_HI

(i)

Hub Interface Output Low
Current

OL_HI

max

OH_HI

(i)

Hub Interface Output High
Current

-1

OH_HI

max

LEAK_HI

(i)

Hub Interface Input
Leakage Current

-150, +15

µA 0<Vin<

VCC1_8

IN_HI

(i)

Hub Interface Input
Capacitance

2.58 3.17

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Symbol Signal

Group

Parameter Min

Nom

Max

Unit

Notes

Miscellaneous Signals

(o)

Input Low Voltage

HIREF - 0.15

(o)

Input High Voltage

HIREF + 0.15

(o)

Output Low Voltage

0.1 x VCC1_8

= 1 mA

(o)

Output High Voltage

0.9 x VCC1_8

= 1 mA

(o)

Output Low Current

OL_HI

max

(o)

Output High Current

-1

OH_HI

max

LEAK

(o)

Input Leakage Current

-150, +15

µA 0<Vin<

VCC1_8

(o)

Input

Capacitance 2.58 3.17

(p)

Input Low Voltage

0.8

(p)

Input High Voltage

2.0

LEAK

(p)

Input Leakage Current

±100

µA

0<Vin<VCC3_3

(p)

Input

Capacitance 4.690 5.370

(q)

Input Low Voltage

(q)

Input High Voltage

0.660

0.710

0.850

CROSS

(q)

Crossing

Voltage

0.45x(V

- V

) 0.5x(V

- V

) 0.55x(V

- V

) V

(q)

Input

Capacitance

0.94

1.1

(v)

Input Low Voltage

0.8

(v)

Input High Voltage

2.4

(v)

Input

Capacitance 1.2 1.4

NOTES:

1. Determined with 0.75x MCH-M DDR buffer strength setting.
2.

In suspend, not all non-CKE pins will be pulled up; there will be an indeterminate number that will
be pulled low.

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Ballout and Package Information

9.1. Ballout

Diagram

Table 39. Top View (Left Side)

29 28 27 26 25 24 23 22

18 17 16 15

VSS

VCC1_5

VTT

VSS VSS

SBA0 SBA1 G_GNT#

VSS VSS VSS HD61# HD57#

VCC1_5 SBA2 SBA3 ST2

ST0 G_REQ# VTT VSS VTT VSS VTT VSS HD56# HD55# HD54#

SB_STB

SB_STB# VSS ST1 VCC1_5 PIPE# VSS VTT VSS VTT VSS HD59# VSS

VSS SBA4 SBA5 VCC1_5 SBA7 SBA6 WBF# RBF# VTT VSS VTT VSS

CPURST#

HD63# HD60#

NC GRCOMP

G_AD31

VCC1_5 VSS VCC1_5

VTT VSS VTT HD62# VSS DBI3#

VCC1_5

AD_STB1#

AD_STB1 VSS G_AD28

G_AD29 VSS G_AD30

VSS VSS VTT VSS HD58#

HDSTBP3#

HDSTBN3#

G_AD20 G_AD22 G_AD19 G_AD27 G_AD24 VSS VCC1_5 VTT VSS VTT HVREF

VSS

G_AD18

G_AD21

VCC1_5

G_AD26

G_AD25

G_CBE3#

VCC1_5 AGPREF

G_AD16

G_AD17

G_CBE2#

G_FRAME

G_AD23

VSS

VCC1_5

G_DEVSEL

G_IRDY#

VSS

G_PAR

G_TRDY#

G_STOP#

VCC1_5

G_AD9

G_AD8

G_CBE0#

G_AD15

G_CBE1#

VSS

G_AD7

G_AD6

VCC1_5

G_AD14

G_AD13

G_AD11

VCC1_5

VSSA1

VCC1_5 VSS

G_AD5 G_AD4 G_AD2 G_AD12

G_AD10 VSS

VCCA1

VSS VCC1_5

VCC1_5 G_AD1 G_AD0

VSS

G_AD3

AD_STB0

AD_STB0# VCC1_5

VSS

VCC1_5

VSS

HLRCOMP

HI_REF

HI_0

HI_1

HI_3

66IN

VCC1_5

VSS

VCC1_5

VSS

HI_9

HI_2 VCC1_8 HI_STB HI_STB# VCC1_8 VSS

VSS VCC1_5 VSS

HI_8 HI_4 HI_5 HI_10 VSS

VCC1_8

HI_6

HI_7

VSS

VCC1_8

VSS

VCCSM

VSS

VSS VCCSM RSVD VCCSM RSVD VCCSM

VSS

SMRCOMP

RSTIN# VSS RSVD SCK1 RSVD VSS

SDREF

RSVD TESTIN# SDQ4 VCCSM SCKE2 VCCSM VSS VCCSM VSS VCCSM

VSS VCCSM VSS

VCCSM SDQ0 SDQ5

VSS SCK#1 SCK#4

SCKE0 SMA12 SMA7 SMA8 SMA4 SMA3 RSVD RSVD SCK3

SDQ1

SDQS0

SDQ6

VSS

SCKE3

VCCSM

SMA9

VSS

SMA6

VCCSM

SMA1

VSS

SCK#0

VSS SDQ3 SDQ8 VSS SDQ15 SCK4

SDQ17 SCKE1 SDQ19 SMA11 SDQ29 SMA5 SDQ31

SMA2 SDQS8

SDQ13

SDQ14

VCCSM

SDQ16

VCCSM

SDQ22

VSS

SDQ25

VCCSM

SDQ27

VSS

SCB1

VCCSM

VCCSM SDQ2 SDQ9 SDQS1 SDQ11 SDQ20 SDQS2 SDQ18 SDQ24 SDQ28

SDQ26

SDQ30 SCB5 SCB0 SCB6

SDQ7

SDQ12 SDQ10 SDQ21

SDQ23

SDQS3

SCB4 SCB2

VSS

VCCSM

VSS

VCCSM

VSS

VCCSM

VSS

29 28 27 26 25 24 23 22

18 17 16 15

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

134

Datasheet

250687-002

Table 40. Top View (Right Side)

8 7 6 5 4 3 2 1

VSS

VSS VSS VSS

HD57#

HD49#

HD44#

DBI2#

HD24# HD31# HD25#

HD20#

HD54# HD52# HD48# HD45# HD42# HD43#

HD38#

HD27# HD28# HD29# HD16# DBI1# HD22# HD17# VSS

VSS HD51# VSS HD47# VSS HD41#

VSS

HD30# VSS HD19# VSS HD26# HD21#

HD60# HD53# HD46# HD40# HDSTBN2# HD36# HD34# HD18# HDSTBP1#

HDSTBN1# HD23#

VSS

HD8#

HD15#

VSS

DBI3# VSS

HSWNG

VSS HDSTBP2# VSS HD37# VSS HD10#

VSS

DBI0# HDSTBN0#

HDSTBP0#

HDSTBN3# HD50#

HRCOM

HD33# HD32# HD39#

HD35#

HD14# HD11# HD12# HD5#

VSS

HD13# HRCOMP0

VSS

VSS VSS VSS VSS HVREF VSS VSS VTT HD9# VSS HD1# HD4# HD3#

VTT

VSS

HSWNG0

HD7#

HD2#

VSS

HD6#

HD0#

VSS

HVREF

BPRI#

VSS

HIT#

DEFER#

HITM#

VSS

RS1#

RS2#

HLOCK#

VSS

BNR#

RS0#

VSS

BR0#

VSS

DBSY#

DRDY#

ADS#

VSS

VCC1_5

VSSA0

VTT

HTRDY#

HREQ0#

HREQ3#

VSS

HA6#

HREQ4#

VSS

VCC1_5 VSS

VCCA0

VSS

HREQ1#

VSS

HA4#

HA3#

HA5#

VSS

VCC1_5

VSS

HVREF

HREQ2#

HA11#

HADSTB0#

VSS

HA7#

HA9#

VSS

VCC1_5

VSS

VCC1_5

VSS

HA8#

VSS

HA12#

HA10#

HA13#

VSS

VCC1_5

VSS

HA15#

HADSTB1#

HA28#

VSS

HA16#

HA14#

VSS

VTT HVREF HA30# HA24# HA18# HA19#

VSS

HA31# VSS HA21# VSS HA20# HA26#

VSS

BCLK#

VSS

VCCSM

VSS

HA17#

HA22#

SDREF

BCLK

VCCSM VSS VCCSM VSS HA25# HA23# VSS

VSS VCCSM VSS VCCSM VSS VCCSM

VSS

VCCSM

RSVD RSVD SCK5

HA27#

RCVENOU

SCK3 SCK#3 SBS1 SBS0 SWE# RSVD

RSVD

SCAS# SCK#2 SCK2 SDQ63 VCCSM

RCVENIN#

HA29# VCCSM

SCK#0 VCCSM SMA10 VSS SRAS# VCCSM

SCS#2 VSS SCS#1 VCCSM SCK#5 SDQ58 SDQ59

SDQS8 SCK0 SDQ32 SMA0 SDQ44 SDQ40 SCS#0 SDQ43 SCS#3 SDQ52 SDQ55

VSS

SDQS7

SDQ62 VSS

VCCSM SCB7 VSS SDQS4 VCCSM SDQ39 VSS SDQ42 VCCSM SDQ49 VSS SDQ50 SDQ57

SCB6 SCB3 SDQ37 SDQ33 SDQ38 SDQ35

SDQ41

SDQS5 SDQ47 SDQ48 SDQS6

SDQ54 SDQ56 SDQ61

VCCSM

SCB2

SDQ36

SDQ34

SDQ45

SDQ46 SDQ53 SDQ51

SDQ60

VSS

VCCSM

VSS

VCCSM

VSS VCCSM VSS

8 7 6 5 4 3 2 1

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

135

9.2. Ballout

Table

Signal Name

Ball #

66IN P22

AD_STB0 R24

AD_STB0# R23

AD_STB1 AC27

AD_STB1# AC28

ADS# V3

AGPREF AA21

BCLK# K8

BCLK J8

BNR# W3

BPRI# Y7

BR0# V7

CPURST# AE17

DBSY# V5

DEFER# Y4

DBI0# AD5

DBI1# AG4

DBI2# AH9

DBI3# AD15

DRDY# V4

G_AD0 R27

G_AD1 R28

G_AD2 T25

G_AD3 R25

G_AD4 T26

G_AD5 T27

G_AD6 U27

G_AD7 U28

G_AD8 V26

G_AD9 V27

G_AD10 T23

G_AD11 U23

Signal Name

Ball #

G_AD12 T24

G_AD13 U24

G_AD14 U25

G_AD15 V24

G_AD16 Y27

G_AD17 Y26

G_AD18 AA28

G_AD19 AB25

G_AD20 AB27

G_AD21 AA27

G_AD22 AB26

G_AD23 Y23

G_AD24 AB23

G_AD25 AA24

G_AD26 AA25

G_AD27 AB24

G_AD28 AC25

G_AD29 AC24

G_AD30 AC22

G_AD31 AD24

G_CBE0# V25

G_CBE1# V23

G_CBE2# Y25

G_CBE3# AA23

G_DEVSEL# W28

G_FRAME# Y24

G_GNT# AH25

G_IRDY# W27

G_PAR W25

G_REQ# AG24

G_STOP# W23

G_TRDY# W24

Signal Name

Ball #

GRCOMP AD25

HA3# T4

HA4# T5

HA5# T3

HA6# U3

HA7# R3

HA8# P7

HA9# R2

HA10# P4

HA11# R6

HA12# P5

HA13# P3

HA14# N2

HA15# N7

HA16# N3

HA17# K4

HA18# M4

HA19# M3

HA20# L3

HA21# L5

HA22# K3

HA23# J2

HA24# M5

HA25# J3

HA26# L2

HA27# H4

HA28# N5

HA29# G2

HA30# M6

HA31# L7

HADSTB0# R5

HADSTB1# N6

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82845MP/82845MZ Chipset-Mobile (MCH-M)

136

Datasheet

250687-002

Signal Name

Ball #

HD0# AA2

HD1# AB5

HD2# AA5

HD3# AB3

HD4# AB4

HD5# AC5

HD6# AA3

HD7# AA6

HD8# AE3

HD9# AB7

HD10# AD7

HD11# AC7

HD12# AC6

HD13# AC3

HD14# AC8

HD15# AE2

HD16# AG5

HD17# AG2

HD18# AE8

HD19# AF6

HD20# AH2

HD21# AF3

HD22# AG3

HD23# AE5

HD24# AH7

HD25# AH3

HD26# AF4

HD27# AG8

HD28# AG7

HD29# AG6

HD30# AF8

HD31# AH5

HD32# AC11

HD33# AC12

HD34# AE9

HD35# AC9

Signal Name

Ball #

HD36# AE10

HD37# AD9

HD38# AG9

HD39# AC10

HD40# AE12

HD41# AF10

HD42# AG11

HD43# AG10

HD44# AH11

HD45# AG12

HD46# AE13

HD47# AF12

HD48# AG13

HD49# AH13

HD50# AC14

HD51# AF14

HD52# AG14

HD53# AE14

HD54# AG15

HD55# AG16

HD56# AG17

HD57# AH15

HD58# AC17

HD59# AF16

HD60# AE15

HD61# AH17

HD62# AD17

HD63# AE16

HDSTBN0# AD4

HDSTBP0# AD3

HDSTBN1# AE6

HDSTBP1# AE7

HDSTBN2# AE11

HDSTBP2# AD11

HDSTBN3# AC15

HDSTBP3# AC16

Signal Name

Ball #

HI_0 P25

HI_1 P24

HI_2 N27

HI_3 P23

HI_4 M26

HI_5 M25

HI_6 L28

HI_7 L27

HI_8 M27

HI_9 N28

HI_10 M24

HI_REF P26

HI_STB N25

HI_STB# N24

HIT# Y5

HITM# Y3

HLOCK# W5

HLRCOMP P27

HRCOMP0 AC2

HRCOMP1 AC13

HREQ0# U6

HREQ1# T7

HREQ2# R7

HREQ3# U5

HREQ4# U2

HSWNG0 AA7

HSWNG1 AD13

HTRDY# U7

HVREF M7,R8,Y8,AB11,

AB17

NC AD26,AD27

PIPE# AF22

RBF# AE22

RCVENIN# G3

RCVENOUT# H3

RS0# W2

RS1# W7

Intel

82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

137

Signal Name

Ball #

RS2# W6

RSTIN# J27

RSVD G9,G10,G16,G17,H6,H

7,H27J23,J25,K23,K25,

E15

SBA0 AH28

SBA1 AH27

SBA2 AG28

SBA3 AG27

SBA4 AE28

SBA5 AE27

SBA6 AE24

SBA7 AE25

SB_STB AF27

SB_STB# AF26

SCAS# G8

SCK0 E14

SCK1 J24

SCK2 G6

SCK3 G15

SCK4 E24

SCK5 H5

SBS0 G12

SBS1 G13

SCK#0 F15

SCK#1 G25

SCK#2 G7

SCK#3 G14

SCK#4 G24

SCK#5 F5

SCKE0 G23

SCKE1 E22

SCKE2 H23

SCKE3 F23

SCS#0 E9

SCS#1 F7

SCS#2 F9

Signal Name

Ball #

SCS#3 E7

SDQ0 G28

SDQ1 F27

SDQ2 C28

SDQ3 E28

SDQ4 H25

SDQ5 G27

SDQ6 F25

SDQ7 B28

SDQ8 E27

SDQ9 C27

SDQ10 B25

SDQ11 C25

SDQ12 B27

SDQ13 D27

SDQ14 D26

SDQ15 E25

SDQ16 D24

SDQ17 E23

SDQ18 C22

SDQ19 E21

SDQ20 C24

SDQ21 B23

SDQ22 D22

SDQ23 B21

SDQ24 C21

SDQ25 D20

SDQ26 C19

SDQ27 D18

SDQ28 C20

SDQ29 E19

SDQ30 C18

SDQ31 E17

SDQ32 E13

SDQ33 C12

SDQ34 B11

Signal Name

Ball #

SDQ35 C10

SDQ36 B13

SDQ37 C13

SDQ38 C11

SDQ39 D10

SDQ40 E10

SDQ41 C9

SDQ42 D8

SDQ43 E8

SDQ44 E11

SDQ45 B9

SDQ46 B7

SDQ47 C7

SDQ48 C6

SDQ49 D6

SDQ50 D4

SDQ51 B3

SDQ52 E6

SDQ53 B5

SDQ54 C4

SDQ55 E5

SDQ56 C3

SDQ57 D3

SDQ58 F4

SDQ59 F3

SDQ60 B2

SDQ61 C2

SDQ62 E2

SDQ63 G5

SCB0 C16

SCB1 D16

SCB2 B15

SCB3 C14

SCB4 B17

SCB5 C17

SCB6 C15

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82845MP/82845MZ Chipset-Mobile (MCH-M)

138

Datasheet

250687-002

Signal Name

Ball #

SCB7 D14

SDQS0 F26

SDQS1 C26

SDQS2 C23

SDQS3 B19

SDQS4 D12

SDQS5 C8

SDQS6 C5

SDQS7 E3

SDQS8 E15

SDREF J9,J21

SMA0 E12

SMA1 F17

SMA2 E16

SMA3 G18

SMA4 G19

SMA5 E18

SMA6 F19

SMA7 G21

SMA8 G20

SMA9 F21

SMA10 F13

SMA11 E20

SMA12 G22

SMRCOMP J28

SRAS# F11

ST0 AG25

ST1 AF24

ST2 AG26

SWE# G11

TESTIN# H26

VCC1_5 R22,R29,U22,U26,W22

,W29,AA22,

AA26,AB21,AC29,AD2

1,AD23,AE26,AF23,AG

29,AJ25

Signal Name

Ball #

VCC1_5 N14,N16,P13,P15,P17,

R14,R16,T15,U14,U16

VCCA1 T17

VCCA0

T13

VCC1_8 L25,L29,M22,N23,N26

VCCSM A5,A9,A13,A17,

A21,A25,C1,C29,

D7,D11,D15,D19,

D23,D25,F6,F10,
F14,F18,F22,G1,

G4,G29,H8,H10,

H12,H14,H16,H18,H20,
H22,H24,J5,J7,K6,K22,

K24,K26, L23

VSS A3,A7,A11,A15,A19,A2

3,A27,D5,D9,

D13,D17,D21,E1,

E4,E26,E29,F8,F12,F1

6,F20,F24,G26,H9,H11

,H13,H15,

H17,H19,H21,J1,J4,J6,

J22,J26,J29,K5,K7,K27

,L1,L4,L6,

L8,L22,L24,L26,

M23,N1,N4,N8,N13,N1
5,N17,N22,N29,P6,P8,

P14,P16,R1,R4,R13,R1

5,R17,

R26,T6,T8,T14,T16,T2

2,U1,U4,U15,

U29,V6,V8,V22,W1,W4

,W8,W26,Y6,Y22,AA1,

AA4,AA8,

AA29,AB6,AB9,

AB10,AB12,AB13,AB1

4,AB15,AB16,AB19,AB

22,AC1,

AC4,AC18,AC20,

AC21,AC23,AC26,AD6,

AD8,AD10,

AD12,AD14,AD16,AD1

9,AD22,AE1,

AE4,AE18,AE20,

AE29,AF5,AF7,AF9,AF

11,AF13,AF15,AF17,A

F19,AF21,

AF25,AG1,AG18,

AG20,AG22,AH19,AH2

1,AH23,AJ3,

AJ5,AJ7,AJ9,AJ11,AJ1

3,AJ15,AJ17, AJ27

Signal Name

Ball #

VSSA1

U17

VSSA0

U13

VTT M8,U8,AA9,AB8,

AB18,AB20,AC19,AD1

8,AD20,AE19,AE21,AF

18,AF20,

AG19,AG21,AG23,AJ1

9,AJ21,AJ23

WBF# AE23

Intel

845MZ Chipset:82845MZ (MCH-M)

250687-001

Datasheet

143

9.4. Testability

In the

MCH-M, testability for Automated Test Equipment (ATE) board level testing has been implemented

as and XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. Refer to
Figure 11 for an example XOR chain.

Figure 11. XORTree Chain

Input

XOR

Out

xor.vsd

Input

VCC1_8

The algorithm used for in circuit test is as follows

· Drive all input pins to an initial logic level `1'. Observe the output corresponding to scan chain being

tested.

· Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its

initial logic level to the opposite logic level. Observe the output changes with each pin toggle.

9.4.1.

XOR Test Mode Initialization

XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition
of RSTINB. The signals that need to be pulled are as follows:
GGNTB = 0 (Global strap enable)
SBA[1] = 0 (XOR strap)
ST[2]

= 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)