Intel
850 Chipset Family:
82850/82850E Memory Controller
Hub (MCH)
Datasheet
October 2002
Document Number:
290691-004
R
Intel
82850/82850E MCH
R
2
Datasheet
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Copyright 2000-2002, Intel Corporation
Intel
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Datasheet
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Contents
1.
Introduction .................................................................................................................................11
1.1.
Related Documents .......................................................................................................11
1.2.
Terminology ...................................................................................................................12
1.3.
Intel
850/850E Chipset Family System.........................................................................13
1.4.
Intel
82850/82850E MCH Overview .............................................................................14
2.
Signal Description.......................................................................................................................19
2.1.
Host Interface Signals ....................................................................................................20
2.2.
Direct RDRAM* Interface A............................................................................................22
2.3.
Direct RDRAM* Interface B............................................................................................23
2.4.
Hub Interface Signals.....................................................................................................23
2.5.
AGP Interface Signals....................................................................................................24
2.5.1.
AGP Addressing Signals..............................................................................24
2.5.2.
AGP Flow Control Signals............................................................................25
2.5.3.
AGP Status Signals .....................................................................................25
2.5.4.
AGP Strobes ................................................................................................26
2.5.5.
AGP/PCI Signals-Semantics........................................................................27
2.6.
Clocks, Reset, and Miscellaneous .................................................................................29
2.7.
Voltage References, PLL Power ....................................................................................30
2.8.
Pin States during Reset .................................................................................................31
3.
Register Description ...................................................................................................................33
3.1.
Register Nomenclature, Definitions, and Access Attributes...........................................33
3.2.
PCI Configuration Space Access...................................................................................34
3.3.
I/O Mapped Registers ....................................................................................................36
3.3.1.
CONF_ADDR--Configuration Address Register.........................................36
3.3.2.
CONF_DATA--Configuration Data Register ...............................................37
3.4.
Host-Hub Interface Bridge Device Registers (Device 0)...............................................38
3.4.1.
VID--Vendor Identification Register (Device 0)...........................................40
3.4.2.
DID--Device Identification Register (Device 0) ...........................................40
3.4.3.
PCICMD--PCI Command Register (Device 0)............................................41
3.4.4.
PCISTS--PCI Status Register (Device 0) ...................................................42
3.4.5.
RID--Revision Identification Register (Device 0) ........................................43
3.4.6.
SUBC--Sub-Class Code Register (Device 0) .............................................43
3.4.7.
BCC--Base Class Code Register (Device 0) ..............................................43
3.4.8.
MLT--Master Latency Timer Register (Device 0) .......................................44
3.4.9.
HDR--Header Type Register (Device 0) .....................................................44
3.4.10.
APBASE--Aperture Base Configuration Register (Device 0)......................44
3.4.11.
SVID--Subsystem Vendor ID (Device 0).....................................................45
3.4.12.
SID--Subsystem ID (Device 0)....................................................................46
3.4.13.
CAPPTR--Capabilities Pointer (Device 0) ..................................................46
3.4.14.
GAR[0:15]--RDRAM* Group Architecture Register (Device 0)...................47
3.4.15.
MCHCFG--MCH Configuration Register (Device 0) ...................................48
3.4.16.
FDHC--Fixed DRAM Hole Control Register (Device 0) ..............................49
3.4.17.
PAM[0:6]--Programmable Attribute Map Registers (Device 0)...................50
3.4.18.
GBA[0:15]--RDRAM* Group Boundary Address Register (Device 0)........53
3.4.19.
RDPS--RDRAM* Pool Sizing Register (Device 0) ......................................54
3.4.20.
DRD--RDRAM* Device Register Data Register (Device 0) ........................55
3.4.21.
RICM--RDRAM* Initialization Control Management Register (Device 0) ...55
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Datasheet
3.4.22.
SMRAM--System Management RAM Control Register (Device 0) ........... 57
3.4.23.
ESMRAMC--Extended System Management RAM Control Register
(Device 0) .................................................................................................... 58
3.4.24.
ACAPID--AGP Capability Identifier Register (Device 0)............................. 59
3.4.25.
AGPSTAT--AGP Status Register (Device 0) ............................................. 60
3.4.26.
AGPCMD--AGP Command Register (Device 0) ........................................ 61
3.4.27.
AGPCTRL--AGP Control Register ............................................................. 62
3.4.28.
APSIZE--Aperture Size (Device 0) ............................................................. 62
3.4.29.
ATTBASE--Aperture Translation Table Base Register (Device 0)............ 63
3.4.30.
AMTT--AGP Interface Multi-Transaction Timer Register (Device 0) ........ 63
3.4.31.
LPTT--Low Priority Transaction Timer Register (Device 0) ....................... 64
3.4.32.
RDTR--RDRAM* Timing Register (Device 0)............................................. 65
3.4.33.
TOM--Top of Low Memory Register (Device 0) ......................................... 66
3.4.34.
ERRSTS--Error Status Register (Device 0) ............................................... 66
3.4.35.
ERRCMD--Error Command Register (Device 0) ....................................... 68
3.4.36.
SMICMD--SMI Command Register (Device 0) .......................................... 69
3.4.37.
SCICMD--SCI Command Register (Device 0) ........................................... 70
3.4.38.
DRAMRC--RDRAM* Refresh Control Register (Device 0) ........................ 70
3.4.39.
SKPD--Scratchpad Data (Device 0) ........................................................... 71
3.4.40.
DERRCTL_STS--DRAM Error Control/Status Register (Device 0)........... 71
3.4.41.
EAP--Error Address Pointer Register (Device 0) ....................................... 72
3.4.42.
MISC_CNTL--Miscellaneous Control Register (Device 0) ......................... 72
3.5.
AGP Bridge Registers (Device 1) .................................................................................. 73
3.5.1.
VID1--Vendor Identification Register (Device 1) ........................................ 74
3.5.2.
DID1--Device Identification Register (Device 1)......................................... 74
3.5.3.
PCICMD1--PCI-PCI Command Register (Device 1) .................................. 75
3.5.4.
PCISTS1--PCI-PCI Status Register (Device 1).......................................... 76
3.5.5.
RID1--Revision Identification Register (Device 1) ...................................... 76
3.5.6.
SUBC1--Sub-Class Code Register (Device 1)........................................... 77
3.5.7.
BCC1--Base Class Code Register (Device 1)............................................ 77
3.5.8.
MLT1--Master Latency Timer Register (Device 1) ..................................... 77
3.5.9.
HDR1--Header Type Register (Device 1)................................................... 78
3.5.10.
PBUSN1--Primary Bus Number Register (Device 1) ................................. 78
3.5.11.
SBUSN1--Secondary Bus Number Register (Device 1) ............................ 78
3.5.12.
SUBUSN1--Subordinate Bus Number Register (Device 1)........................ 79
3.5.13.
SMLT1--Secondary Master Latency Timer Register (Device 1) ................ 79
3.5.14.
IOBASE1--I/O Base Address Register (Device 1) ..................................... 80
3.5.15.
IOLIMIT1--I/O Limit Address Register (Device 1) ...................................... 80
3.5.16.
SSTS1--Secondary PCI-PCI Status Register (Device 1) ........................... 81
3.5.17.
MBASE1--Memory Base Address Register (Device 1) .............................. 82
3.5.18.
MLIMIT1--Memory Limit Address Register (Device 1) ............................... 82
3.5.19.
PMBASE1--Prefetchable Memory Base Address Register (Device 1) ...... 83
3.5.20.
PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1) ....... 83
3.5.21.
BCTRL1--PCI-to-PCI Bridge Control Register (Device 1).......................... 84
3.5.22.
ERRCMD1--Error Command Register (Device 1) ..................................... 85
4.
System Address Map ................................................................................................................. 87
4.1.
Memory Address Ranges .............................................................................................. 87
4.1.1.
VGA and MDA Memory Space.................................................................... 88
4.1.2.
PAM Memory Spaces.................................................................................. 89
4.1.3.
ISA Hole Memory Space ............................................................................. 89
4.1.4.
TSEG SMM Memory Space ........................................................................ 91
4.1.5.
I/O APIC Memory Space ............................................................................. 91
4.1.6.
System Bus Interrupt APIC Memory Space ................................................ 91
4.1.7.
High SMM Memory Space........................................................................... 91
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4.1.8.
AGP Aperture Space (Device 0 BAR)..........................................................92
4.1.9.
AGP Memory and Prefetchable Memory .....................................................92
4.1.10.
Hub Interface Subtractive Decode ...............................................................92
4.2.
AGP Memory Address Ranges ......................................................................................92
4.2.1.
AGP DRAM Graphics Aperture....................................................................93
4.3.
System Management Mode (SMM) Memory Range......................................................93
4.3.1.
SMM Space Definition .................................................................................94
4.3.2.
SMM Space Restrictions..............................................................................94
4.4.
I/O Address Space.........................................................................................................95
4.5.
MCH Decode Rules and Cross-Bridge Address Mapping .............................................95
4.5.1.
Hub Interface Decode Rules........................................................................95
4.5.2.
AGP Interface Decode Rules.......................................................................96
5.
Memory Interface Description.....................................................................................................97
5.1.
RDRAM* Organization and Configuration......................................................................99
5.1.1.
Rules for Populating RDRAM* Devices .......................................................99
5.1.2.
RDRAM* CMOS Signals............................................................................100
5.1.3.
Direct RDRAM* Core Refresh....................................................................101
5.2.
Direct RDRAM* Command Encoding ..........................................................................102
5.2.1.
Row Packet (ROWA/ROWR) ....................................................................102
5.2.2.
Column Packet (COLC/COLX) ..................................................................103
5.2.2.1.
Data Packet...................................................................................105
5.3.
Direct RDRAM* Register Programming .......................................................................105
5.4.
Direct RDRAM* Operating States ................................................................................105
5.5.
RDRAM* Operating Pools............................................................................................106
5.5.1.
Pool "A", Pool "B", and Pool "C" Operation ................................................106
5.6.
RDRAM* Power Management .....................................................................................106
5.7.
Data Integrity................................................................................................................107
5.8.
RDRAM* Array Thermal Management.........................................................................107
6.
Electrical Characteristics ..........................................................................................................109
6.1.
Absolute Maximum Ratings .........................................................................................109
6.2.
Thermal Characteristics ...............................................................................................110
6.3.
Power Characteristics ..................................................................................................110
6.4.
I/O Interface Signal Groupings.....................................................................................111
6.5.
DC Characteristics .......................................................................................................113
7.
Pinout and Package Information ..............................................................................................117
7.1.
Ballout Information .......................................................................................................117
7.2.
Package Information ....................................................................................................126
7.3.
MCH RSL Package Dimensions ..................................................................................127
7.3.1.
MCH RSL Compensation and Normalized Trace Length Data .................128
7.3.2.
MCH System Bus Signal Normalized Trace Length Data..........................129
8.
Testability..................................................................................................................................131
8.1.
XOR Test Mode Initialization........................................................................................132
8.2.
XOR Chains .................................................................................................................132
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