R
Intel
852GM Chipset Graphics and
Memory Controller Hub (GMCH)
Datasheet
January 2003
Order Number: 252407-001
R
2
Intel
852GM Chipset GMCH Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power
characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its
customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations. Intel provides
this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers, and Intel's
customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel 852GM Chipset Graphics and Memory Controller Hub (GMCH) may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips*. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN* is a result of the Intel and IBM* Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
Intel, the Intel logo, Pentium, and Intel SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States
and other countries.
*Other brands and names may be claimed as the property of others.
Copyright Intel Corporation 2003
R
Intel
852GM Chipset GMCH Datasheet
3
Contents
1.
Introduction .................................................................................................................................15
1.1.
Terminology ...................................................................................................................15
1.2.
Reference Documents ...................................................................................................16
1.3.
System Architecture Overview.......................................................................................17
1.3.1.
Intel 852GM GMCH System Architecture.........................................................17
1.4.
Processor Host Interface ...............................................................................................18
1.4.1.
Intel 852GM GMCH Processor Host Interface .................................................18
1.5.
Intel 852GM GMCH Host Bus Error Checking...............................................................18
1.6.
Intel 852GM GMCH System Memory Interface .............................................................18
1.7.
Intel 852GM GMCH Internal Graphics...........................................................................19
1.7.1.
Intel 852GM GMCH Analog Display Port .........................................................19
1.7.2.
Intel 852GM GMCH Integrated LVDS Port.......................................................20
1.7.3.
Intel 852GM GMCH Integrated DVO Port ........................................................20
1.8.
Hub Interface .................................................................................................................20
1.9.
Address Decode Policies...............................................................................................20
1.10.
Intel 852GM GMCH Clocking ........................................................................................20
1.11.
System Interrupts...........................................................................................................21
2.
Signal Description.......................................................................................................................23
2.1.
Host Interface Signals....................................................................................................24
2.2.
DDR SDRAM Interface ..................................................................................................26
2.3.
Hub Interface Signals.....................................................................................................27
2.4.
Clocks ............................................................................................................................28
2.5.
Internal Graphics Display Signals..................................................................................30
2.5.1.
Dedicated LFP LVDS Interface ........................................................................30
2.5.2.
Digital Video Port C (DVOC) ............................................................................31
2.5.3.
Analog Display..................................................................................................32
2.5.4.
General Purpose Input/Output Signals.............................................................33
2.6.
Voltage References, PLL Power....................................................................................35
3.
Register Description ...................................................................................................................37
3.1.
Conceptual Overview of the Platform Configuration Structure......................................37
3.2.
Nomenclature for Access Attributes ..............................................................................38
3.3.
Standard PCI Bus Configuration Mechanism ................................................................39
3.4.
Routing Configuration Accesses....................................................................................39
3.4.1.
PCI Bus #0 Configuration Mechanism .............................................................39
3.4.2.
Primary PCI and Downstream Configuration Mechanism................................39
3.5.
Register Definitions........................................................................................................40
3.6.
I/O Mapped Registers ....................................................................................................41
3.6.1.
CONFIG_ADDRESS Configuration Address Register..................................41
3.6.2.
CONFIG_DATA Configuration Data Register ...............................................43
3.7.
VGA I/O Mapped Registers ...........................................................................................44
3.8.
Intel 852GM GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function
#0)..................................................................................................................................45
3.8.1.
VID Vendor Identification...............................................................................46
3.8.2.
DID Device Identification ...............................................................................46
3.8.3.
PCICMD PCI Command Register .................................................................47
3.8.4.
PCI Status Register ..........................................................................................48
R
4
Intel
852GM Chipset GMCH Datasheet
3.8.5.
RID Register Identification ............................................................................ 49
3.8.6.
SUBC Sub Class Code ................................................................................. 49
3.8.7.
BCC Base Class Code.................................................................................. 50
3.8.8.
HDR Header Type......................................................................................... 50
3.8.9.
SVID Subsystem Vendor Identification ......................................................... 50
3.8.10.
SID Subsystem Identification ........................................................................ 51
3.8.11.
CAPPTR Capabilities Pointer ....................................................................... 51
3.8.12.
CAPID
Capability Identification Register (Device 0) ..................................... 52
3.8.13.
RRBAR Register Range Base Address Register (Device 0)........................ 53
3.8.14.
GMC GMCH Miscellaneous Control Register (Device 0) ............................. 54
3.8.15.
GGC GMCH Graphics Control Register (Device 0)...................................... 55
3.8.16.
DAFC Device and Function Control Register (Device 0).............................. 56
3.8.17.
FDHC Fixed DRAM Hole Control Register (Device 0).................................. 56
3.8.18.
PAM(6:0) Programmable Attribute Map Register (Device 0)........................ 57
3.8.19.
SMRAM System Management RAM Ctrl Register (Device 0)...................... 61
3.8.20.
ESMRAMC Extended System Management RAM Control (Device 0) ......... 62
3.8.21.
ERRSTS Error Status Register (Device 0) ................................................... 63
3.8.22.
ERRCMD Error Command Register (Device 0)............................................ 64
3.8.23.
SMICMD SMI Error Command Register (Device 0) ..................................... 66
3.8.24.
SCICMD SCI Error Command Register (Device 0) ...................................... 67
3.8.25.
CAPD Capability Disable Bits ....................................................................... 68
3.9.
Intel 852GM GMCH Main Memory Control, Memory I/O Control Registers (Device #0,
Function #1) .................................................................................................................. 69
3.9.1.
VID Vendor Identification .............................................................................. 70
3.9.2.
DID Device Identification............................................................................... 70
3.9.3.
PCICMD PCI Command Register................................................................. 71
3.9.4.
PCISTS PCI Status Register ........................................................................ 72
3.9.5.
RID Revision Identification............................................................................ 73
3.9.6.
SUBC Sub-Class Code................................................................................. 73
3.9.7.
BCC Base Class Code.................................................................................. 73
3.9.8.
HDR Header Type......................................................................................... 74
3.9.9.
SVID Subsystem Vendor Identification ......................................................... 74
3.9.10.
SID Subsystem Identification ........................................................................ 74
3.9.11.
CAPPTR Capabilities Pointer ....................................................................... 75
3.9.12.
DRB DRAM Row Boundary Register - Device #0 ........................................ 75
3.9.13.
DRA DRAM Row Attribute Register - Device #0 .......................................... 76
3.9.14.
DRT DRAM Timing Register - Device #0...................................................... 77
3.9.15.
PWRMG DRAM Controller Power Management Control Register
Device #0 ......................................................................................................... 80
3.9.16.
DRC DRAM Controller Mode Register - Device #0 ...................................... 81
3.9.17.
DTC DRAM Throttling Control Register (Device 0) ...................................... 83
3.10.
Intel 852GM GMCH Configuration Process and Registers (Device #0, Function #3) .. 87
3.10.1.
VID Vendor Identification .............................................................................. 87
3.10.2.
DID Device Identification............................................................................... 88
3.10.3.
PCICMD PCI Command Register................................................................. 89
3.10.4.
PCISTS PCI Status Register ........................................................................ 90
3.10.5.
RID Revision Identification............................................................................ 91
3.10.6.
SUBC Sub-Class Code................................................................................. 91
3.10.7.
BCC Base Class Code.................................................................................. 91
3.10.8.
HDR Header Type......................................................................................... 92
3.10.9.
SVID Subsystem Vendor Identification ......................................................... 92
3.10.10.
ID Subsystem Identification .......................................................................... 92
3.10.11.
CAPPTR Capabilities Pointer ....................................................................... 93
3.10.12.
HPLLCC HPLL Clock Control Register (Device 0) ....................................... 93
R
Intel
852GM Chipset GMCH Datasheet
5
3.11.
Intel 852GM GMCH Integrated Graphics Device Registers (Device #2, Function #0)..94
3.11.1.
VID2 Vendor Identification Register Device #2 ..........................................95
3.11.2.
DID2 Device Identification Register - Device #2 ...........................................95
3.11.3.
PCICMD2 PCI Command Register - Device #2 ............................................96
3.11.4.
PCISTS2 PCI Status Register - Device #2....................................................97
3.11.5.
RID2 Revision Identification Register - Device #2.........................................97
3.11.6.
CC Class Code Register - Device #2 ............................................................98
3.11.7.
CLS Cache Line Size Register - Device #2...................................................98
3.11.8.
MLT2 Master Latency Timer Register - Device #2........................................98
3.11.9.
HDR2 Header Type Register - Device #2 .....................................................99
3.11.10.
GMADR Graphics Memory Range Address Register - Device #2 ................99
3.11.11.
MMADR Memory Mapped Range Address Register - Device #2 ...............100
3.11.12.
IOBAR I/O Base Address Register - (Device #2)........................................100
3.11.13.
SVID2 Subsystem Vendor Identification Register - Device #2....................101
3.11.14.
SID2 Subsystem Identification Register - Device #2...................................101
3.11.15.
ROMADR Video BIOS ROM Base Address Registers - Device #2 ............101
3.11.16.
INTRLINE
Interrupt Line Register - Device #2.............................................102
3.11.17.
INTRPIN
Interrupt Pin Register - Device #2 ................................................102
3.11.18.
MINGNT Minimum Grant Register - Device #2 ...........................................102
3.11.19.
MAXLAT Maximum Latency Register - Device #2 ......................................102
3.11.20.
PMCAP Power Management Capabilities Register - Device #2 .................103
3.11.21.
PMCS Power Management Control/Status Register - Device #2 ...............103
4.
Intel 852GM GMCH System Address Map...............................................................................105
4.1.
System Memory Address Ranges ...............................................................................105
4.2.
Compatibility Area........................................................................................................107
4.3.
Extended System Memory Area ..................................................................................109
4.4.
Main System Memory Address Range (0010_0000h to Top of Main Memory) ..........110
4.4.1.
15 MB-16 MB Window....................................................................................110
4.4.2.
Pre-allocated System Memory .......................................................................110
4.4.2.1.
Extended SMRAM Address Range (HSEG and TSEG) ...............111
4.4.2.2.
HSEG ............................................................................................111
4.4.2.3.
TSEG.............................................................................................111
4.4.2.4.
Intel Dynamic Video Memory Technology (DVMT).......................111
4.4.2.5.
PCI Memory Address Range (Top of Main System Memory to 4
GB) ................................................................................................111
4.4.2.6.
APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh)........................................................112
4.4.2.7.
High BIOS Area (FFE0_0000h -FFFF_FFFFh) ............................112
4.4.3.
System Management Mode (SMM) Memory Range......................................112
4.4.3.1.
SMM Space Restrictions...............................................................113
4.4.3.2.
SMM Space Definition...................................................................113
4.4.4.
System Memory Shadowing...........................................................................113
4.4.5.
I/O Address Space .........................................................................................113
4.4.6.
GMCH Decode Rules and Cross-Bridge Address Mapping...........................114
4.4.7.
Hub Interface Decode Rules ..........................................................................114
4.4.7.1.
Hub Interface Accesses to GMCH that Cross Device
Boundaries ....................................................................................115
5.
Functional Description ..............................................................................................................117
5.1.
Host Interface Overview...............................................................................................117
5.2.
Dynamic Bus Inversion ................................................................................................117
5.2.1.
System Bus Interrupt Delivery........................................................................117
PDF 
ZIP