87C196CA/87C196CB 16 MHz
ADVANCED 16-BIT CHMOS
MICROCONTROLLER WITH
INTEGRATED CAN 2.0

Express

Advance Information

Datasheet

Product Features

40°C to +85°C Ambient

High Performance CHMOS 16-Bit CPU

Up to 32 Kbytes of On-Chip EPROM

Up to 1 Kbyte of On-Chip Register RAM

Up to 512 Bytes of Additional RAM
(Code RAM)

8 Channel/10-Bit A/D with Sample/Hold

37 Prioritized Interrupts

Up to Seven 8-Bit (56) I/O Ports

Full Duplex Serial I/O Port

Dedicated Baud Rate Generator

Interprocessor Communication Slave Port

Selectable Bus Timing Modes for Flexible
Interfacing

Oscillator Fail Detection Circuitry

High Speed Peripheral Transaction Server
(PTS)

Two Dedicated 16-Bit High-Speed
Compare Registers

10 High Speed Capture/Compare (EPA)

Full Duplex Synchronous Serial I/O Port
(SSIO)

Two Flexible 16-Bit Timer Counters

Quadrature Counting Inputs

Flexible 8-/16-Bit External Bus
(Programmable)

Programmable Bus (HLD/HLDA)

1.4 µs 16 x 16 Multiply

2.4 µs 32/16 Divide

68-Pin PLCC Package for 87C196CA

84-Pin PLCC Package for 87C196CB

16 MHz Operation

Order No: 273151-001

January 1998

Notice:

This document contains information on products in the sampling and initial production

phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.

87C196CA/87C196CB -

Express

Advance Information

Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 87C196CA/87C196CB -

Express may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation
PO Box 5937
Denver CO 80217-9808
call 1-800-548-4725

*Third-party brands and names are the property of their respective owners.

Advance Information

Datasheet

iii

87C196CA/87C196CB -

Express

Contents

1.0

INTRODUCTION

..................................................................................................... 1

2.0

BLOCK DIAGRAM

.................................................................................................. 2

3.0

PROCESS INFORMATION

................................................................................. 3

4.0

PIN DESCRIPTIONS

............................................................................................. 6

5.0

ELECTRICAL CHARACTERISTICS

...............................................................11

5.1

DC CHARACTERISTICS .............................................................................. 11
5.1.1

8xC196CB Additional Bus Timing Modes ........................................ 14
5.1.1.1 MODE 3............................................................................... 14
5.1.1.2 MODE 0............................................................................... 14

5.2

AC CHARACTERISTICS .............................................................................. 14
5.2.1

Test Conditions ................................................................................ 14

5.2.2

87C196CA/87C196CB - Express Timings ....................................... 17

5.2.3

87C196CB Timings .......................................................................... 18

5.2.4

8xC196CB Timings .......................................................................... 19

5.2.5

8xC196CB AC Characteristics - Slave Port ..................................... 20

5.2.6

Explanation of AC Symbols.............................................................. 24

5.3

EPROM Specifications .................................................................................. 25
5.3.1

AC EPROM Programming Characteristics....................................... 25

5.3.2

EPROM Programming Waveforms .................................................. 26

5.4

AC CHARACTERISTICS - Serial Port - Shift Register Mode........................ 28
5.4.1

A/D Characteristics........................................................................... 28
5.4.1.1 A/D Converter Specification ................................................ 29

5.4.2

87C196CA Design Considerations................................................... 32

5.4.3

87C196CA ERRATA ........................................................................ 33

5.4.4

87C196CA DESIGN CONSIDERATIONS........................................ 33

6.0

DATASHEET REVISION HISTORY

................................................................34

87C196CA/87C196CB -

Express

Advance Information

Datasheet

Figures

8XC196CB Block Diagram ...............................................................................2

The 87C196CA/87C196CB - Express Family Nomenclature...........................3

84-Pin PLCC TN87C196CB Diagram ..............................................................4

68-Pin PLCC TN87C196CA Diagram ..............................................................5

Chip Configuration Registers .........................................................................10

87C196CA I

vs Frequency .........................................................................13

87C196CB I

vs Frequency .........................................................................13

87C196CA/87C196CB - Express System Bus Timing ...................................17

87C196CA/87C196CB - Express Ready Timings (One Wait State) ..............18

87C196CB Buswidth Timings ........................................................................18

87C196CB HOLD#/HOLDA# Timings............................................................19

Slave Port Waveform - (SLPL = 0).................................................................20

Slave Port Waveform - (SLPL = 1).................................................................21

Synchronous Serial Port ................................................................................23

External Clock Drive Waveforms ...................................................................24

Input Test Conditions .....................................................................................24

Output Test Conditions ..................................................................................24

Slave Programming Mode Data Program Mode with Single Program Pulse .26

Slave Programming Mode in Word Dump or Data Verify Mode
with Auto Increment .......................................................................................27

Slave Programming Mode Timing in Data Program Mode
with Repeated Program Pulse and Auto Increment .......................................27

Waveform - Serial Port - Shift Register Mode 0 .............................................28

AD_TIME 1FAFH:Byte ...................................................................................29

Tables

Device Overview ..............................................................................................1

Thermal Characteristics ...................................................................................3

Pin Descriptions ...............................................................................................6

87C196CB Memory Map..................................................................................8

87C196CA Memory Map..................................................................................9

DC Characteristics (Under Listed Operating Conditions)...............................11

AC Characteristics the 87C196CA/87C196CB - Express Meets ...................14

AC Characteristics System Must Meet to Work
with 87C196CA/87C196CB - Express ...........................................................16

8xC196CB HOLD#/HOLDA# Timings
(Over Specified Operation Conditions) ..........................................................19

Slave Port Timing - (SLPL = 0, 1, 2, 3) ..........................................................20

Slave Port Timing - (SLPL = 1, 2, 3) ..............................................................21

Normal Master/Slave Operation .....................................................................22

Handshake Operation ....................................................................................22

External Clock Drive.......................................................................................23

Explanation of AC Symbols............................................................................25

AC EPROM Programming Characteristics.....................................................25

DC EPROM Programming Characteristics ....................................................26

Serial Port Timing - Shift Register Mode ........................................................28

10-Bit Mode A/D Operating Conditions ..........................................................29

10-Bit Mode A/D Characteristics (Using Above Operating Conditions) .........30

8-Bit Mode A/D Operating Conditions ............................................................30

8-Bit Mode A/D Characteristics (Using Above Operating Conditions) ...........31

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

1.0

INTRODUCTION

The 87C196CA/87C196CB - Express are members of the MCS

96 microcontroller family. These

devices are based upon the MCS 96 Kx/Jx microcontroller product families with enhancements
ideal for automotive and industrial applications. The CA/CB are the first devices in the Kx family
to support networking through the integration of the CAN 2.0 (Controller Area Network)
peripheral on-chip. The 87C196CB offers the highest memory density of the MCS 96
microcontroller family, with 56K of on-chip EPROM, 1.5K of on-chip register RAM, and 512
bytes of additional RAM (Code RAM). In addition, the 87C196CB provides up to 16 Mbyte of
Linear Address Space. The 87C196CA is a sub-set of the CB, offering 32K of on-chip EPROM, up
to 1.0 K of on-chip register.

Table 1. Device Overview

Device

Pins/Pac

kage

EPROM

Reg

RAM

Code

RAM

I/O

EPA

SIO

SSIO

CAN

A/D

Addr

Space

87C196CB

84-Pin
PLCC

56K

1.5K

512b

1 Mbyte

87C196CA

68-Pin
PLCC

32K

1.0K

256b

64 Kbyte

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

2.0

BLOCK DIAGRAM

The MCS 96 microcontroller family members are all high-performance microcontrollers with a
16-bit CPU. The 87C196CB is composed of the high-speed (16 MHz) macrocore with up to
16 Mbyte linear address space, 56 Kbytes of program EPROM, up to 1.5 Kbytes of register RAM,
and up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this
RAM space. It supports the high-speed, serial communications protocol CAN 2.0, with 15 message
objects of 8 bytes data length, an 8-channel, 10-bit / 3 LSB analog to digital converter with
programmable S/H times, and conversion times k 20 ms at 16 MHz. It has an
asynchronous/synchronous serial I/O port (SIO) with a dedicated 16-bit baud rate generator, an
additional synchronous serial I/O port (SSIO) with full duplex master/slave transceivers, a flexible
timer/counter structure with prescaler, cascading, and quadrature capabilities. There are ten
modularized, multiplexed, high-speed I/O for capture and compare (called Event Processor Array)
with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt
structure with programmable Peripheral Transaction Server (PTS) implementing several channel
modes, including single/burst block transfers from any memory location to any memory location, a
PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode.

Note:

This is an advance information data sheet. The AC and DC parameters contained within this data
sheet may change after full express temperature characterization of the device has been performed.
Contact your local sales office before finalizing the timing and DC characteristics of a design to
verify you have the latest information.

Figure 1. 8XC196CB Block Diagram

A4546-01

A/D

Converter

Sync

Serial

Port and

Baud Gen

Watchdog

Timer

Event

Processor

Array

ALU

CPU

Microcode

Engine

Interrupt

Controller

512 Bytes

Internal RAM

56K On-chip

EPROM

(optional)

Peripheral

Transaction

Server

Memory

Controller

1.5K
Byte

File

S/H

MUX

Port 0

Serial

Port

Baud

Rate

Gen

Port 6

Port 1

Port 2

CAN 2.0

Timer 1
Timer 2

Queue

Port 6

SSIO

A/D

Port 0

Port 1

EPA

Port 2 /

Hold Control

RXCAN
TXCAN

Port 5
Control
Signals

Port 3
AD0-7

Port 4
AD8-15

EPORT
A16-23

REF

ANGND

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

3.0

PROCESS INFORMATION

These devices are manufactured on P629.5, a CHMOS III-E process. Additional process and
reliability information is available in Intel's Components Quality and Reliability Handbook, Order
Number 210997.

All thermal impedance data is approximate for static air conditions at 1 W of power dissipation.
Values change depending on operation conditions and applications. See the Intel Packaging
Handbook (order number 240800) for a description of Intel's thermal impedance test methodology.

Figure 2. The 87C196CA/87C196CB -

Express

Family Nomenclature

Table 1. Thermal Characteristics

Device and Package

TN87C196CB
(84-Lead PLCC Package)

35°C/W

11°C/W

TN87C196CA
(68-Lead PLCC Package)

36.5°C/W

10°C/W

NOTES:

= Thermal resistance between junction and the surrounding environment (ambient) measurements are

taken 1 ft. away from case in air flow environment.

= Thermal resistance between junction and package face (case).

2. All values of

and

may fluctuate depending on the environment (with or without airflow, and how

much airflow) and device power dissipation at temperature of operation. Typical variations are ± 2°C/W.

3. Values listed are at a maximum power dissipation of 1 W.

A4582-01

T N 8 7 C

C A / B

1 9 6

7 = EPROM, OTP
0 = CPU

Product Designation
Product Family
CHMOS Technology

Program Memory Options:

N = PLCC (plastic leaded chip carrier)

Package Type Options:

T = -40

C to + 85

ambient with
Intel Standard Burn-in

Temperature and Burn-in Options:

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Figure 3. 84-Pin PLCC TN87C196CB Diagram

A4581-01

PLLEN
P6.3 / T1DIR
P6.2 / T1CLK
P6.1 / EPA9
P6.0 / EPA8
P1.0 / EPA0
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / EPA4
P1.5 / EPA5
P1.6 / EPA6
P1.7 / EPA7
V

SS1

REF

AGND
P0.7 / ACH7
P0.6 / ACH6
P0.5 / ACH5
P0.4 / ACH4

P5.2 / WR#

P5.5 /BHE#

P5.3 / RD#

P5.0 / ALE

P5.1 / INST

P5.6 / READY

P5.4 / SLPINT

EP3.3 / A19

SS1

RXCAN

TXCAN

XTAL1

XTAL2

P6.7 / SD1

P6.6 / SC1

P6.5 / SD0

P6.4 / SC0

PS.7 / BUSW

EP3.1 / A17
EP3.0 / A16

P4.7 / AD15
P4.6 / AD14
P4.5 / AD13
P4.4 / AD12
P4.3 / AD11
P4.2 / AD10

P4.1 / AD9
P4.0 / AD8

SS1

P3.7 / AD7
P3.6 / AD6
P3.5 / AD5
P3.4 / AD4
P3.3 / AD3
P3.2 / AD2
P3.1 / AD1

EP3.2 / A18

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

TN87C196CB

84-Lead PLCC

View of component as
mounted on PC board

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

P3.0 / AD0

RESET

NMI

EA#

SS1

P2.0 / TXD

P2.1 / RXD

P2.2 / EXTINT

P2.3 / INTB#

P2.4 / INTINTOUT#

P2.5 / HLD#

P2.6 / HLDA#

P2.7 / CLKOUT

SS1

P0.0 / ACH0

P0.1 / ACH1

P0.2 / ACH2

P0.3 / ACH3

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

Figure 4. 68-Pin PLCC TN87C196CA Diagram

A4583-01

NC
NC
V

EPA9 / P6.1
EPA8 / P6.0
EPA0 / P1.0 / T2CLK
EPA1 / P1.1
EPA2 / P1.2 / T2DIR
EPA3 / P1.3
NC
V

REF

ANGND
ACH7 / P0.7
ACH6 / P0.6
ACH5 / P0.5
ACH4 / P0.4
NC

WR# / P5.2

WRH# / P5.5

RD# / P5.3

ALE / P5.0

READY / P5.6

P5.4

SS1

XTAL1

XTAL2

RXCAN

TXCAN

SD1 / P6.7

SC1 / P6.6

SD0 / P6.5

SC0 / P6.4

AD15 / P4.7
AD14 / P4.6
AD13 / P4.5
AD12 / P4.4
AD11 / P4.3
AD10 / P4.2

AD9 / P4.1
AD8 / P4.0
AD7 / P3.7
AD6 / P3.6
AD5 / P3.5
AD4 / P3.4
AD3 / P3.3

AD2 / P3.2

NC
NC

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

TN87C196CA

68 ld PLCC

View of component as
mounted on PC board

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

P3.1 / AD1

P3.0 / AD0

RESET#

NMI

EA#

SS1

TXD / P2.0

RXD / P2.1

EXTINT / P2.2

P2.4

P2.6

CLKOUT / P2.7

ACH2 / P0.2

ACH3 / P0.3

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

4.0

PIN DESCRIPTIONS

Table 2. Pin Descriptions (Sheet 1 of 3)

Name

Description

Main supply voltage (+5 V).

, V

SS1

Digital circuit ground (0 V). There are seven V

pins CB (4 on CA), all of which MUST

be connected to a single ground plane.

REF

Reference for the A/D converter (+5 V). V

REF

is also the supply voltage to the analog

portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.

Programming voltage for the EPROM parts. It should be +12.5 V for programming. It is
also the timing pin for the return from powerdown circuit. Connect this pin with a 1 µF
capacitor to V

and a 1 M

resistor to V

. If this function is not used, V

may be tied

to V

ANGND

Reference ground for the A/D converter. Must be held at nominally the same potential as
V

XTAL1

Input of the oscillator inverter and the internal clock generator.

XTAL2

Output of the oscillator inverter.

RESET#

Reset input to the chip. Input low for at least 16 state times resets the chip. The
subsequent low-to-high transition resynchronizes CLKOUT and commences a 10-state
time sequence in which the PSW is cleared, bytes are read from 2018H, 201AH and
201CH (if enabled) loading the CCBs, and a jump to location 2080H is executed. Input
high for normal operation. RESET# has an internal pullup.

NMI

A positive transition causes a non-maskable interrupt vector through memory location
203EH. If not used, this pin should be tied to V

. May be used by Intel Evaluation

boards.

EA#

Input for memory select (External Access). EA# equal to a high causes memory
accesses to locations 0FF2000H through 0FFFFFH to be directed to on-chip
EPROM/ROM. EA# equal to a low causes accesses to these locations to be directed to
off- chip memory. EA# = +12.5 V causes execution to begin in the Programming Mode.
EA# latched at reset.

PLLEN
(196CB only)

Selects between PLL mode or PLL bypass mode. This pin must be either tied high or
low. PLLEN pin = 0, bypass PLL mode. PLLEN pin = 1, places a 4x PLL at the input of
the crystal oscillator. Allows for a low frequency crystal to drive the device
(i.e., 5 MHz = 16 MHz operation).

P6.4-6.7/SSIO

Dual-function I/O ports that have a system function as Synchronous Serial I/O. Two pins
are clocks and two pins are data, providing full duplex capability. Also, LSIO when not
used as SSIO.

P6.3/T1DIR
(CB only)

Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may
also be used as a TIMER1 Direction input. The TIMER1 increments when this pin is high
and decrements when this pin is low.

P6.2/T1CLK
(CB only)

Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however may also
be used as a TIMER1 Clock input. The TIMER1 increments or decrements on both
positive and negative edges of this pin.

P6.0-6.1/EPA8-9

Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is
that of High Speed capture and compare.

P5.7/BUSWIDTH
(CB only)

Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is "0" and
CCR1 bit 2 is "1", all bus cycles are 8-bit, if CCR bit 1 is "1" and CCR1 bit 2 is "0", all bus
cycles are 16-bit. CCR bit 1 = "0" and CCR1 bit 2 = "0" is illegal. Also an LSIO pin when
not used as BUSWIDTH.

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

P5.6/READY

Ready input to lengthen external memory cycles, for interfacing with slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes
into a wait state mode until the next positive transition in CLKOUT occurs with READY
high. When external memory is not used, READY has no effect. The max number of wait
states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if
READY is not selected.

P5.5/BHE#/WRH#

Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects the
bank of memory that is connected to the high byte of the data bus. A0 = 0 selects the
bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide
memory can be to the low byte only (A0 = 0, BHE# = 1), to the high byte only (A0 = 1,
BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is selected, the pin
goes low if the bus cycle is writing to an odd memory location. BHE#/WRH# is only valid
during 16-bit external. Also an LSIO pin when not BHE/WRH#.

P5.4/SLPINT

Dual-function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only).

P5.3/RD#

Read signal output to external memory. RD# is active only during external memory reads
or LSIO when not used as RD#.

P5.2/WR#/WRL#

Write and Write Low output to external memory, as selected by the CCR, WR# goes low
for every external write, while WRL# goes low only for external writes where an even
byte is being written. WR#/WRL# is active during external memory writes. Also an LSIO
pin when not used as WR#/WRL#.

P5.1/INST
(CB only)

Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST.

P5.0/ALE/ADV#

Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV#, it goes inactive (high) at the end of the bus cycle. ADV# can be used as a chip
select for external memory. ALE/ADV# is active only during external memory accesses.
Also LSIO when not used as ALE.

PORT3 and 4

8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.

P2.7/CLKOUT

Output of the internal clock generator. The frequency is the oscillator frequency.
CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.

P2.6/HLDA#

Bus Hold Acknowledge. Active-low output indicates that the bus controller has
relinquished control of the bus. Occurs in response to an external device asserting the
HLD# signal. Also LSIO when not used as HLDA#.

P2.5/HLDÝ
(CB only)

Bus Hold. Active-low signal indicates that an external device is requesting control of the
bus. Also LSIO when not used as HLD#.

P2.4/INTOUT#

Interrupt Output. This active-low output indicates that a pending interrupt requires use of
the external bus. Also LSIO when not used as INTOUT#.

P2.3/BREQ#
(CB only)

Bus Request. This active-low output signal is asserted during a HOLD cycle when the
bus controller has a pending external memory cycle. Also LSIO when not used as
BREQ#.

P2.2/EXTINT

A positive transition on this pin causes a maskable interrupt vector through memory
location 203CH. Also LSIO when not used as EXTINT.

P2.1/RXD

Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD.

P2.0/TXD

Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD.

PORT 1/EPA07

Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is
that of High Speed capture and compare. EPA0 and EPA2 have another function of
T2CLK and T2DIR of the TIMER2 timer/counter.

Table 2. Pin Descriptions (Sheet 2 of 3)

Name

Description

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

PORT 0/ACH07

8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.

EPORT (CB only)

8-bit bidirectional standard and I/O Port. These bits are shared with the extended
address bus, A16A19 for CB PLCC. Pin function is selected on a per pin basis.

TXCAN

Push-pull output to the CAN bus line.

RXCAN

High impedance input-only from the CAN bus line.

Table 3. 87C196CB Memory Map

Address

Description

Notes

FFFFFFH
FF2080H

Program Memory - Internal EPROM or External Memory (Determined by EA#
Pin)

FF207FH
FF2000H

Special Purpose Memory - Internal EPROM or External Memory (Determined
by EA# Pin)

FF1FFFH
FF0600H

External Memory

FF05FFH
FF0400H

Internal RAM (Identically Mapped into 00400H±005FFH)

FF03FFH
FF0100H

External Memory

FF00FFH
FF0000H

Reserved for ICE

FEFFFFH
0F0000H

Overlaid Memory (External)

(5)

0EFFFFH
010000H

900 Kbytes External Memory

00FFFFH
002080H

External Memory or Remapped OTPROM (Program Memory)

(1)

00207FH
002000H

External Memory or Remapped OTPROM (Special Purpose Memory)

(1,3)

001FFFH
001FE0H

Memory Mapped Special Function Registers (SFR's)

001FDFH
001F00H

Internal Peripheral Special Function Registers (SFR's)

(5)

001EFFH
001E00H

Internal CAN Peripheral Memory

(5)

001DFFH
001C00H

Internal Register RAM

001BFFH
000600H

External Memory

NOTES:

1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they

are external memory.

2. Code executed in locations 0000H to 003FFH is forced external.
3. Reserved memory locations must contain 0FFH unless noted.
4. Reserved SFR bit locations must be written with 0.
5. Refer to

8XC196CB User's Guide

for SFR, CAN and Paging Descriptions.

Table 2. Pin Descriptions (Sheet 3 of 3)

Name

Description

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

0005FFH
000400H

Internal RAM (Code RAM) (Address with Indirect or Indexed Modes)

0003FFH
000100H

(2)

0000FFH
000018H

(2)

000017H
000000H

CPU SFR's

(4)

Table 4. 87C196CA Memory Map

Address

Description

Notes

00FFFFH
00A000H

External Memory

009FFFH
002080H

Internal EPROM (32 Kbytes)

00207FH

002000H

(Determined by EA# Pin) Reserved Memory (Internal EPROM or External
Memory)

001FFFH
001FE0H

Memory Mapped Special Function Registers (SFR's)

001FDFH
001F00H

Internal Special Function Registers (SFR's)

(1)

001EFFH
001E00H

Internal CAN Peripheral Memory

001DFFH
000500H

External Memory

0004FFH

000400H

(Address with Indirect or Indexed Modes) Internal RAM (Code RAM)

0003FFH
000100H

Internal Register RAM Upper Register File (Address with Indirect or Indexed
Modes or through Windows)

(2)

0000FFH
000018H

Internal Register RAM Lower Register File (Address with Direct, Indirect, or
Indexed Modes.

(2)

000017H
000000H

CPU Special Function Registers (SFR's)

(2,3)

NOTES:

1. Refer to

8XC196KX Family User's Guide

for SFR Description.

2. Code executed in locations 0000H to 003FFH is forced external.
3. Reserved SFR bit locations must be written with 0.

Table 3. 87C196CB Memory Map

Address

Description

Notes

NOTES:

1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they

are external memory.

2. Code executed in locations 0000H to 003FFH is forced external.
3. Reserved memory locations must contain 0FFH unless noted.
4. Reserved SFR bit locations must be written with 0.
5. Refer to

8XC196CB User's Guide

for SFR, CAN and Paging Descriptions.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Figure 5. Chip Configuration Registers

CCB (2018H: Byte)

BW0

ALE

IRC0

IRC1

LOC0

LOC1

"1" Enables Powerdown

See Table

"1" = WR#/BHE - "0" = WRL#/WRH#

"1" = ALE - "0" = ADV

}

See Table

}

See Table

CCB1 (201AH: Byte)

CCR2

IRC2

BW1

WDE

MEMSEL0

MEMSEL1

"1" Fetch CCB2 ("0" for CA)

See Table

"0" = Always Enabled

Reserved Must Be "1"

See Table

LOC1

LOC0

Function

IRC2

IRC1

IRC0

Max Wait States

Read and Write Protected

Write Protected Only

Read Protected Only

No Protection

Zero Wait States

1 Wait State

2 Wait States

3 Wait States

INFINITE

MSEL1

MSEL0

"CB" Bus Timing Mode

BW1

BW0

Bus Width

Mode 0 (1-Wait KR)

Mode 1

Mode 2

Mode 3 (KR)

ILLEGAL

16-Bit Only

8-Bit Only

BW Pin Controlled

Mode 0
(1-Wait KR):

Designed to be similar to the 87C196KR bus timing with 1 automatic wait state.

See AC Timings section for actual timings data.

Mode 3 (KR):

Designed to be similar to the 87C196KR bus timing.

See AC Timings section for actual timings data.

CCB2 (201CH: Byte) (CB Only)

MODE16

REMAP

Reserved Must Be "0"

Select 16-Bit or 24-Bit Mode

"0"Select EPROM/CODERAM in Segment 0FFH only
"1"Select Both Segment 0FFH and Segment 00H

Reserved Must Be "1"

}

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

5.0

ELECTRICAL CHARACTERISTICS

5.1

DC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature

60°C to +150°C

Voltage from V

or EA# to

or ANGND................................ 0.5 V to +13.0 V

Voltage from any other pin to

or ANGND................................ 0.5 V to +7.0 V

This includes V

on ROM and CPU devices.

Power Dissipation ................................. 0.5 W

OPERATING CONDITIONS

(Ambient Temperature Under Bias).....40°C to +85°C

(Digital Supply Voltage)

4.5 V to 5.5 V

REF

(Analog Supply Voltage)

4.5 V to 5.5 V

OSC

(Oscillator Frequency) .................... 4 MHz to 16 MHz

NOTE: ANGND and V

should be nominally at the same

potential.

NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice. Verify with
your local Intel sales office that you have the latest
datasheet before finalizing a design.

*WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause
permanent damage. These are stress ratings
only. Operation beyond the "Operating
Conditions" is not recommended and extended
exposure beyond the "Operating Conditions"
may affect device reliability.

Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Units

Test

Conditions

Supply Current

(40°C to +85°C Ambient)

CA
CB

100

XTAL1 = 16 MHz

= V

REF

= 5.5 V

(While Device in Reset)

REF

A/D Reference Supply
Current

IDLE

Idle Mode Current

CA
CB

40
35

XTAL1 = 16 MHz

= V

REF

= 5.5 V

Powerdown Mode Current

TBD

µA

= V

REF

= 5.5 V

(Notes 6,9)

Input Low Voltage (All Pins)

0.5

0.3 V

For PORT0 (Note 8)

Input High Voltage

0.7 V

+ 0.5

For PORT0 (Note 8)

NOTES:

1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being

weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT
(P5.4) and HLDA (P2.6).

2. Standard Input pins include XTAL1, EA#, RESET and Port 1/2/5/6 when setup as inputs.
3. All Bidirectional I/O pins when configured as Outputs (Push/Pull).
4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum I

currents per pin are characterized and published at a later date.

6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room

temperature and V

REF

= V

= 5 V.

7. Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6).
8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic.
9. For temperatures < 100°C typical is 10 µA.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Output Low Voltage
(Outputs Configured as
Complementary)

0.3

0.45

1.5

= 200 µA (Note 3,5)

= 3.2 mA

= 7 mA

Output High Voltage
(Output Configured as
Complementary)

0.3

0.7

1.5

= 200 µA (Note 3,5)

= 3.2 mA

= 7 mA

Input Leakage Current
(Standard Inputs)

±10

µA

LI1

Input Leakage Current
(Port 0)

CA ±1.5

CB ±1

µA

REF

OH1

SPLINT (P5.4) and
HLDA (P2.6) Output High
Voltage in RESET

= 0.8 mA (Note 7)

OH2

Output High Voltage in
RESET

= 15 µA (Note 1)

Pin Capacitance
(Any Pin to V

)

10 pF

TEST

= 1 MHz (Note 6)

RST

Reset Pull-up Resistor (CB)

65 K

180 K

For CB

RST

Reset Pull-up Resistor (CA)

6 K

65 K

For CA

WPU

Weak Pull-up Resistance
(Approximate)

150 K

(Note 6)

Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 2 of 2)

Symbol

Parameter

Min

Typ

Max

Units

Test

Conditions

NOTES:

1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being

weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT
(P5.4) and HLDA (P2.6).

currents per pin are characterized and published at a later date.

6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room

temperature and V

REF

= V

= 5 V.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.1.1

8xC196CB Additional Bus Timing Modes

The 8xC196CB device has two bus timing modes for external memory interfacing.

5.1.1.1

MODE 3

Mode 3 is the standard timing mode. Use this mode for systems that emulate the 8xC196KR bus
timings.

5.1.1.2

MODE 0

Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus
cycles.

5.2

AC CHARACTERISTICS

5.2.1

Test Conditions

Capacitive load on all pins = 100 pF

Rise and Fall Times = 10 ns

Table 6. AC Characteristics the 87C196CA/87C196CB - Express Meets (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Units

XTAL

Frequency on XTAL1

MHz (1)

OSC

XTAL1 Period (1/F

XTAL

)

62.5

250

XHCH

XTAL1 High to CLKOUT High or Low

+ 20

110

OFD

Clock Failure to Reset Pulled Low

µs (6)

CLCL

CLKOUT Period

OSC

CHCL

CLKOUT High Period

OSC

+15

CLLH

CLKOUT Low to ALE/ADV High

+ 10

LLCH

ALE/ADV# Lowe to CLKOUT High

+ 15

LHLH

ALE/ADV# Cycle Time

OSC

ns (5)

LHLL

ALE/ADV# High Time

OSC

+10

AVLL

Address Valid to ALE Low

OSC

LLAX

Address Hold after ALE/ADV# Low

OSC

LLRL

ALE/ADV# Low to RD# Low

OSC

NOTES:

1. Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2T

OSC

x n = number of wait states. If mode 0 (1 automatic wait state added)

operation is selected, add 2T

OSC

to specification.

6. T

OFD

is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is

enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

RLCL

RD Low to CLKOUT Low

CA
CB

+ 4

+ 30

+ 20

RLRH

RD# Low Period

OSC

ns (5)

RHLH

RD# High to ALE/ADV# High

OSC

+25

ns (3)

RLAZ

RD# Low to Address Float

LLWL

ALE/ADV# Low to WR# Low

OSC

CLWL

CLKOUT Low to WR# Low

+ 25

QVWH

Data Valid before WR# High

OSC

CHWH

CLKOUT High to WR# High

+ 15

WLWH

WR# Low Period

CA
CB

OSC

ns (5)

WHQX

Data Hold after WR# High

OSC

WHLH

WR# High to ALE/ADV# High

OSC

+15

ns (3)

WHBX

BHE#, INST Hold after WR# High

OSC

WHAX

AD8-15 Hold after WR# High

OSC

ns (4)

RHBX

BHE#, INST Hold after RD# High

OSC

RHAX

AD8-15 Hold after RD# High

OSC

ns (4)

Table 6. AC Characteristics the 87C196CA/87C196CB - Express Meets (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

NOTES:

OSC

x n = number of wait states. If mode 0 (1 automatic wait state added)

operation is selected, add 2T

OSC

to specification.

6. T

OFD

is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is

enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Table 7. AC Characteristics System Must Meet to Work with 87C196CA/87C196CB - Express

Symbol

Parameter

Min

Max

Units

AVYV

Address Valid to Ready Setup

ns (3)

LLYV

ALE Low to Ready Setup

250

ns (3)

YLYH

Non Ready Time

No Upper Limit

CLYX

READY Hold after CLKOUT Low

OSC

ns (1)

AVGV

Address Valid to BUSWIDTH Setup

OSC

ns (2,3)

LLGV

ALE Low to BUSWIDTH Setup

OSC

ns (2,3)

CLGX

BUSWIDTH Hold after CLKOUT Low

AVDV

Address Valid to Input Data Valid

OSC

ns (2)

RLDV

RD# Active to Input Data Value

CA
CB

OSC

ns (2)

CLDV

CLKOUT Low to Input Data Valid

OSC

RHDZ

End of RD# to INput Data Valid

RHDX

Data Hold after RD# High

NOTES:

OSC

x n = number of wait states. If mode 0 (1 automatic wait state added)

operation is selected, add 2T

OSC

to specification.

6. T

OFD

is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is

enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

5.2.4

8xC196CB Timings

Table 8. 8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions)

Symbol

Parameter

Min

Max

Units

HVCH

HOLD Setup Time

+ 65

ns (1)

CLHAL

CLKOUT Low to HLDA Low

+ 15

CLBRL

CLKOUT Low to BREQ Low

+ 15

AZHAL

HLDA Low to Address Float

+ 25

BZHAL

HLDA Low to BHE#, INST, RD#, WR# Weakly Driven

+ 25

CLHAH

CLKOUT Low to HLDA High

+ 15

CLBRH

CLKOUT Low to BREQ High

+ 25

HAHAX

HLDA High to Address No Longer Float

HAHBV

HLDA High to BHE#, INST, RD#, WR# Valid

+ 15

NOTE:

1. To guarantee recognition at next clock.

Figure 11. 87C196CB HOLD#/HOLDA# Timings

A5848-01

CLKOUT

HOLD#

HOLDA#

BREQ#

BUS

BHE#, INST,

RD#, WR#

ALE

CHLH

CLHAH

CLBRH

HAHAX

HALBZ

HALAZ

CLBRL

CLHAL

HVCH

OSC

Hold Latency

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.2.5

8xC196CB AC Characteristics - Slave Port

Figure 12. Slave Port Waveform - (SLPL = 0)

Table 9. Slave Port Timing - (SLPL = 0, 1, 2, 3)

Symbol

Parameter

Min

Max

Units

SAVWL

Address Valid to WR# Low

SRHAV

RD# High to Address Valid

SRLRH

RD# Low Period

OSC

SWLWH

WR# Low Period

OSC

SRLDV

RD# Low to Output Data Valid

SDVWH

Input Data Setup to WR# High

SWHQX

WR# High to Data Invalid

SRHDZ

RD# High to Data Float

NOTE:

1. Test Conditions:

· F

OSC

= 16 MHz

· T

OSC

= 60 ns

· Rise/Fall Time = 10 ns
· Capacitive Pin Load = 100 pF

2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory

tests.

3. Specifications above are advance information and are subject to change.

A5847-01

ALE / A1

SWLWH

SRLDV

SRHAV

SAVWL

SRLRH

SDVWH

SWHQX

SRHDZ

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

Figure 13. Slave Port Waveform - (SLPL = 1)

Table 10. Slave Port Timing - (SLPL = 1, 2, 3)

Symbol

Parameter

Min

Max

Units

SELLL

CS# Low to ALE Low

SRHEH

RD# or WR# High to CS# High

SLLRL

ALE Low to RD# Low

OSC

SRLRH

RD# Low Period

OSC

SWLWH

WR# Low Period

OSC

SAVLL

Address Valid to ALE Low

SLLAX

ALE Low to Address Invalid

SRLDV

RD# Low to Output Data Valid

SDVWH

Input Data Setup to WR# High

SWHQX

WR# High to Data Invalid

SRHDZ

RD# High to Data Float

NOTE:

1. Test Conditions:

· F

OSC

= 16 MHz

· T

OSC

= 60 ns

· Rise/Fall Time = 10 ns
· Capacitive Pin Load = 100 pF

2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory

tests.

3. Specifications above are advance information and are subject to change.

A5846-01

ALE

SRLDV

SWLWH

SLLRL

SELLL

SRHEH

SRLRH

SAVLL

SLLAX

SDVWH

SWHQX

SRHDZ

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Table 11. Normal Master/Slave Operation

Symbol

Parameter

Min (1)

Max

Units

CHCH

Clock Period

CLCH

Clock Low Time/Clock High Time

2t10

ns (2)

CLDV

Clock Falling to Data Out Valid (Master)

0.5t

1.5t + 20

CLDV1

Clock Falling to Data Out Valid (Slave)

0.5t

1.5t + 20

DVCH

Data In Setup to Clock Rising Edge

CHDX

Clock Rising Edge to Data In Invalid

t + 15

NOTE:

1. t = 1 state time (125 ns @ 16 MHz).
2. Timings are guaranteed by design.

Table 12. Handshake Operation

Symbol

Parameter

Min (1)

Max

Units

CHCH

Clock Period

CLCH

Clock Low Time/Clock High Time

2t10

ns (2)

CLDV

Clock Falling to Data Out Valid (Master)

0.5t

1.5t + 20

CLDV1

Clock Falling to Data Out Valid (Slave)

0.5t

1.5t + 20

DVCH

Data In Setup to Clock Rising Edge

CHDX

Clock Rising Edge to Data In Invalid

t + 15

NOTE:

1. t = 1 state time (125 ns @ 16 MHz).
2. This specification refers to input clocks during slave operation. During master operation, the device outputs

a nominal 50% duty cycle clock.

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

Figure 14. Synchronous Serial Port

Table 13. External Clock Drive

Symbol

Parameter

Min (1)

Max

Units

1/T

XLXL

Oscillator Frequency

MHz

XLXL

Oscillator Period (T

OSC

)

62.5

250

XHXX

High TIme

0.35 x T

OSC

0.65 T

OSC

XLXX

Low Time

0.35 x T

OSC

0.65 T

OSC

XLXH

Rise TIme

XHXL

Fall Time

NOTE:

1. t = 1 state time (125 ns @ 16 MHz).
2. This specification refers to input clocks during slave operation. During master operation, the device outputs

a nominal 50% duty cycle clock.

MSB

valid

x (out)

x (in)

(Handshake Mode)

Slave Receiver Pulls SC

x low

A5845-01

CHCH

CHCL

CLCH

STE Bit

D1DV

CXDX

CXDV

DVCX

DXCX

The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal.
The CSx signal will be different for other configurations, however, setup and hold timings will still be the same in relation
to the latching edge of SCx.

NOTE:

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.2.6

Explanation of AC Symbols

Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a
signal and its condition, respectively. Symbols represent the time between the two signal/condition
points.

Figure 15. External Clock Drive Waveforms

Figure 16. Input Test Conditions

Figure 17. Output Test Conditions

XLXX

A5842-01

XHXX

XHXL

XLXL

0.3 V

0.5 V

0.7 V

+ 0.5 V

XLXH

0.7 V

+ 0.5 V

0.3 V

0.5 V

0.7 V

+ 0.5 V

Test Points

2.0 V

0.8 V

Note:
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic
"0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for
a logic "0".

3.5 V

0.45 V

A5843-01

INPUTS

OUTPUTS

LOAD

0.15 V

LOAD

+ 0.15 V

Timing Reference

Points

0.15 V

+ 0.15 V

Note:
For timing purposes, a port pin is no longer floating when a 150 mV change from load
voltage occurs and begins to float when a 150 mV change from the loading V

level occurs with I

15 mA.

A5844-01

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

5.3

EPROM Specifications

5.3.1

AC EPROM Programming Characteristics

Operating Conditions:

Table 14. Explanation of AC Symbols

Conditions

Signals

H High

A Address

HA HLDA#

L Low

B BHE#

L ALE/ADV#

V Valid

BR BREQ#

Q Data Out

X No Longer Valid

C CLKOUT

R RD#

Z Floating

D DATA

W WR#/WRH#/WRI#

G Buswidth

X XTAL1

H HOLD#

Y READY

Load Capacitance = 150 pF

= 25°C ± 5°C

REF

= 5.0 V ± 0.5 V

ANGND = 0 V

= 12.5 V ± 0.25 V

EA# = 12.5 V ± 0.25 V

OSC

= 5.0 MHz

Table 15. AC EPROM Programming Characteristics (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Units

AVLL

Address Setup Time

OSC

LLAX

Address Hold Time

100

OSC

DVPL

Data Setup Time

OSC

PLDX

Data Hold Time

400

OSC

LLLH

PALE# Pulse Width

OSC

PLPH

PROG# Pulse Width (2)

CA
CB

100

OSC

LHPL

PALE# High to PROG# Low

220

OSC

PHLL

PROG# High to Next PALE# Low

220

OSC

PHDX

Word Dump Hold Time

OSC

PHPL

PROG# High to Next PROG# Low

220

OSC

LHPL

PALE# High to PROG# Low

220

OSC

PLDV

PROG# Low to Word Dump Valid

CA
CB

100

OSC

SHLL

RESET# High to First PALE# Low

1100

OSC

PHIL

PROG# High to AINC# Low

OSC

ILIH

AINC# Pulse Width

240

OSC

ILVH

PVER Hold after AINC# Low

OSC

ILPL

AINC# Low to PROG# Low

170

OSC

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.3.2

EPROM Programming Waveforms

PHVL

PROG# High to PVER# Valid

220

OSC

NOTES:

1. Run time programming is done with F

OSC

= 6 MHz to 10 MHz, V

, V

REF

= 5 V ±0.5 V,

= 25°C ±5°C and V

= 12.5 V ± 0.25 V. For run-time programming over a full operating range, contact

factory.

2. Programming Specifications are not tested, but guaranteed by design.
3. This specification is for the word dump mode. For programming pulses use 300 T

OSC

+ 100 µs.

Table 16. DC EPROM Programming Characteristics

Symbol

Parameter

Min

Max

Units

Programming Supply Current

200

NOTE: V

must be within 1 V of V

while V

< 4.5 V. V

must not have a low impedance path to ground

or V

while V

> 4.5 V.

Figure 18. Slave Programming Mode Data Program Mode with Single Program Pulse

Table 15. AC EPROM Programming Characteristics (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

PORTS 3/4

RESET#

Address/Command

AVLL

Data

Address/Command

SHLL

LLLH

DVPL

PLDX

PROG#

P2.2

PALE#

P2.1

LHPL

PLPH

LLAX

PHLL

PVER#

P2.0

PHVL

Valid

LLVH

A5838-01

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.4

AC CHARACTERISTICS - Serial Port - Shift Register Mode

Operating Conditions:

= 40°C +85°C

= 0.0 V

= 5.0 V ±10%

Load Capacitance = 100 pF

5.4.1

A/D Characteristics

The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed
by loading a byte into the AD_TIME Special Function Register. This allows optimizing the A/D
operation for specific applications. The AD_TIME register is functional for all possible values, but
the accuracy of the A/D converter is only guaranteed for the times specified in the operating
conditions table.

The value loaded into AD_TIME bits 5, 6, 7 determines the sample time, SAMP. The value loaded
into AD_TIME bits 0, 1, 2, 3 and 4 determines the bit conversion time, CONV. These bits, as well
as the equation for calculating the total conversion time, T, are shown in

Figure 22

Table 17. Serial Port Timing - Shift Register Mode

Symbol

Parameter

Min

Max

Units

XLXL

Serial Port Clock Period

8 T

OSC

XLXH

Serial Port Clock Falling Edge to Rising Edge

4 T

OSC

4 T

OSC

+ 50

QVXH

Output Data Setup to Clock Rising Edge

3 T

OSC

XHQX

Output Data Hold after Clock Rising Edge

2 T

OSC

XHQV

Next Output Data Valid after Clock Rising Edge

2 T

OSC

+ 50

DVXH

Input Data Setup to Clock Rising Edge

2 T

OSC

200

XHDX

(1)

Input Data Hold after Clock Rising Edge

XHQZ

(1)

Last Clock Rising to Output Float

OSC

NOTE:

1. Parameter not tested.

Figure 21. Waveform - Serial Port - Shift Register Mode 0

A5841-01

Valid

RXD

(In)

TXD

QVXH

XLXL

DVXH

XHQV

XHQZ

XHDX

XHQX

XLXH

RXD

(Out)

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of
V

REF

. V

REF

must be closed to V

since it supplies both the resistor ladder and the analog portion

of the converter and input port pins. There is also an AD_TEST SFR that allows for conversion on
ANGND and V

REF

as well as adjusting the zero offset. The absolute error listed is without doing

any adjustments.

5.4.1.1

A/D Converter Specification

The specifications given assume adherence to the operating conditions section of this data sheet.
Testing is performed with V

REF

= 5.12 V and 16 MHz operating frequency. After a conversion is

started, the device is placed in IDLE mode until the conversion is completed.

Figure 22. AD_TIME 1FAFH:Byte

(SAMP)

4n + 1 state times

n = 1 to 7

(CONV)

n + 1 state times

n = 2 to 31

Equation: T = (SAMP + Bx (CONV) + 25

T = total conversion time (states)
B = number of bits conversion (8 or 10)
n = programmed register value

Sample Time

Bit Conversion Time

Table 18. 10-Bit Mode A/D Operating Conditions

Symbol

Parameter

Min

Max

Units

Ambient Temperature

+85

°C

Digital Supply Voltage

4.5

5.5

REF

Analog Supply Voltage

4.5

5.5 (1)

SAM

Sample Time

µs (2)

CONV

Conversion Time

µs (2)

OSC

Oscillator Frequency

MHz

NOTES:

1. V

REF

must be within+0.5 V of V

2. The value of AD_TIME is selected to meet these specifications.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

Table 19. 10-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)

Parameter

Typical (2,3)

Min

Max

Units (4)

Notes

Resolution

1024

Levels

Bits

Absolute Error

LSBs

Full-scale Error

0.25 ±

0.5

LSBs

Zero Offset Error

0.25 ±

0.5

LSBs

Non-Linearity

1 ±

LSBs

Differential Non-Linearity

> 0.75

+ 0.75

LSBs

Channel-to-Channel Matching

0.1

LSBs

Repeatability

0.25

LSBs

(2)

Temperature Coefficients:

Offset
Fullscale
Differential Non-Linearity

0.009

LSB/C

(2)

Off Isolation

(2,4,5)

Feedthrough

(2,4)

Power Supply Rejection

(2,4)

Input Resistance

750

1.2 K

(2)

DC Input Leakage

µA

Voltage on Analog Input Pin

ANGND 0.5

REF

+ 0.5

(7)

Sampling Capacitor

NOTES:

1. All conversions performed with processor in IDLE mode.
2. These values are expected for most parts at 25°C but are not tested or guaranteed.
3. These values are not tested in production and are based on theoretical estimates and/or laboratory test.
4. An "LSB", as used here, has a value of approximately 5 mV
5. DC to 100 KHz
6. Multiplexer Break-Before-Make Guaranteed.
7. Applying voltages beyond these specifications will degrade the accuracy of other channels being

converted.

Table 20. 8-Bit Mode A/D Operating Conditions

Symbol

Parameter

Min

Max

Units

Ambient Temperature

+85

°C

Digital Supply Voltage

4.5

5.5

REF

Analog Supply Voltage

4.5

5.5 (1)

SAM

Sample Time

µs (2)

CONV

Conversion Time

µs (2)

OSC

Oscillator Frequency

MHz

NOTES:

1. V

REF

must be within+0.5 V of V

2. The value of AD_TIME is selected to meet these specifications.

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

Table 21. 8-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)

Parameter

Typical (2,3)

Min

Max

Units (4)

Notes

Resolution

256

1024

Levels

Bits

Absolute Error

LSBs

Full-scale Error

0.5

LSBs

Zero Offset Error

0.5

LSBs

Non-Linearity

LSBs

Differential Non-Linearity

> 0.75

+ 0.5

LSBs

Channel-to-Channel Matching

LSBs

Repeatability

0.25

LSBs

(2)

Temperature Coefficients:

Offset
Fullscale
Differential Non-Linearity

0.003

LSB/C

(2)

Off Isolation

(2,4,5)

Feedthrough

(2,4)

Power Supply Rejection

(2,4)

Input Resistance

750

1.2 K

(2)

DC Input Leakage

1.5

µA

Voltage on Analog Input Pin

ANGND 0.5

REF

+ 0.5

(7)

Sampling Capacitor

NOTES:

converted.

87C196CA/87C196CB -

Express

ADVANCE INFORMATION Datasheet

5.4.2

87C196CA Design Considerations

The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2.0. The
CA is designed for strict functional and electrical compatibility to the Kx family as well as
integration of on-chip networking capability. The 87C196CA has fewer peripheral functions than
the 196KR, due in part to the integration of the CAN peripheral. Following are the functionality
differences between the 196KR and 196CA devices.

196KR Features Unsupported on the 196CA:

1. External Memory. Removal of the Buswidth pin means the bus cannot dynamically switch

from 8- to 16-bit bus mode or vice versa. The programmer must define the bus mode by setting
the associated bits in the CCB.

2. Auto-Programming Mode. The 87C196CA device will ONLY support the 16-bit zero wait

state bus during auto-programming.

3. EPA4 through EPA7. Since the CA device is based on the KR design, these functions are in

the device, however there are no associated pins. A programmer can use these as compare only
channels or for other functions like software timer, start an A/D conversion, or reset timers.

4. Slave Port Support. The Slave port can not be used on the 196CA due to a function change

for P5.4/SLPINT and P5.1/SLPCS not being bonded-out.

5. Port Functions. Some port pins have been removed. P5.1, P6.2, P6.3, P1.4 through P1.7,

P2.3, P2.5, P0.0 and P0.1. The PxREG, PxSSEL, and PxIO registers can still be updated and
read. The programmer should not use the corresponding bits associated with the removed port
pins to conditionally branch in software. Treat these bits as RESERVED.

Additionally, these port pins should be setup internally by software as follows:

· Written to PxREG as ``1'' or ``0''.

· Configured as Push/Pull, PxIO as ``0''.

· Configured as LSIO.

This configuration will effectively strap the pin either high or low. DO NOT Configure
as Open Drain output `'1'', or as an Input pin. This device is CMOS.

6. EPA Timer RESET/Write Conflict. If the user writes to the EPA timer at the same time that

the timer is reset, it is indeterminate which will take precedence. Users should not write to a
timer if using EPA signals to reset it.

7. Valid Time Matches. The timer must increase/decrease to the compare value for a match to

occur. A match does not occur if the timer is loaded with a value equal to an EPA compare
value. Matches also do not occur if a timer is reset and 0 is the EPA compare value.

8. Write Cycle during Reset. If RESET occurs during a write cycle, the contents of the external

memory device may be corrupted.

9. Indirect Shift Instruction. The upper 3 bits of the byte register holding the shift count are not

masked completely. If the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the
operand will be shifted 32 times. This should have resulted in no shift taking place.

10. P2.7 (CLKOUT). P2.7 (CLKOUT) does not operate in open drain mode.

Analog Channels 0 and 1

INST Pin Functionality

SLPINT and SLPCS Pin Support

HLD/HLDA Functionality

External Clocking/Direction of Timer1

Quadrature Clocking Timer 1

Dynamic Buswidth

EPA Capture Channels 4±7

ADVANCE INFORMATION Datasheet

87C196CA/87C196CB -

Express

5.4.3

87C196CA ERRATA

This data sheet was published prior to first available silicon. Consequently, there is no known
errata at this time.

5.4.4

87C196CA DESIGN CONSIDERATIONS

1. PORT0

On the 87C196CA the analog inputs for P0.0 and P0.1 have been multiplexed and tied to V

REF

Therefore, initiating an analog conversion on ACH0 or ACH1 results in a value equal to full scale
(3FFh). On the CA, the digital inputs for these two channels are tied to ground, therefore, reading
P0.0 or P0.1 results in a digital "0".

2. PORT1

On the 87C196CA, P1.4, P1.5, P1.6 and P1.7 have been removed from the device and is not
available to the programmer. Corresponding bits in the port registers have been "hard-wired" to
provide the following results when read:

3. PORT2

On the 87C196CA, P2.3 and P2.5 have been removed from the device and are not available to the
programmer. Corresponding bits in the port registers have been "hard-wired" to provide the
following results when read.

4. PORT5

On the 87C196CA, P5.1 and P5.7 have been removed from the device and are not available to the
programmer. Corresponding bits in the port registers have been "hard-wired" to provide the
following results when read:

Register Bits

When Read

P1_PIN.x

(x = 4,5,6,7)

P1_REG.x

(x = 4,5,6,7)

P1_DIR.x

(x = 4,5,6,7)

P1_MODE.x

(x = 4,5,6,7)

NOTE: Writing to these bits has no effect.

Register Bits

When Read

P2_PIN.x

(x = 3,5)

P2_REG.x

(x = 3,5)

P2_DIR.x

(x = 3,5)

P2_MODE.x

(x = 3,5)

NOTE: Writing to these bits has no effect.

Register Bits

When Read

P5_PIN.x

(x = 1,7)

P5_REG.x

(x = 1,7)

P5_DIR.x

(x = 1,7)

P5_MODE.x

(x = 1)

P5_MODE.x

(x = 7)

NOTE: Writing to these bits has no effect.

Document Outline

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Document Outline

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