PRELIMINARY
COPYRIGHT INTEL CORPORATION, 1996
May 1996
Order Number: 272783-003
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code
compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
s
Real-time and Programmed Wait State
Bus Operation
s
Binary-code Compatible with MCS
51
s
Pin Compatible with 44-pin PLCC and 40-
pin PDIP MCS 51 Sockets
s
Register-based MCS
251 Architecture
-- 40-byte Register File
-- Registers Accessible as Bytes, Words,
or Double Words
s
Enriched MCS 51 Instruction Set
-- 16-bit and 32-bit Arithmetic and Logic
Instructions
-- Compare and Conditional Jump
Instructions
-- Expanded Set of Move Instructions
s
Linear Addressing
s
256-Kbyte Expanded External Code/Data
Memory Space
s
ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
s
16-bit Internal Code Fetch
s
64-Kbyte Extended Stack Space
s
On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
s
8-bit, 2-clock External Code Fetch in
Page Mode
s
Fast MCS 251 Instruction Pipeline
s
User-selectable Configurations:
-- External Wait States (0-3 wait states)
-- Address Range & Memory Mapping
-- Page Mode
s
32 Programmable I/O Lines
s
Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
s
Three Flexible 16-bit Timer/counters
s
Hardware Watchdog Timer
s
Programmable Counter Array
-- High-speed Output
-- Compare/Capture Operation
-- Pulse Width Modulator
-- Watchdog Timer
s
Programmable Serial I/O Port
-- Framing Error Detection
-- Automatic Address Recognition
s
High-performance CHMOS Technology
s
Static Standby to 16-MHz Operation
s
Complete System Development
Support
-- Compatible with Existing Tools
-- New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
s
Package Options (PDIP, PLCC, and
Ceramic DIP)
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
PRELIMINARY
3
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
SRC2 (8)
Code Address (24)
Clock & Reset
Code Bus (16)
Data RAM
512 Bytes
or
1024 Bytes
Code
OTPROM/ROM
8 Kbytes
or
16 Kbytes
Watchdog
Timer
Timer/
Counters
PCA
Serial I/O
Peripherals
Port 2
Drivers
P2.7:0
Port 0
Drivers
P0.7:0
Port 3
Drivers
P3.7:0
Port 1
Drivers
P1.7:0
Data Address (24)
Data Bus (8)
Memory Address (16)
MCS
251 Microcontroller Core
System Bus and I/O Ports
I/O Ports and
Peripheral Signals
SRC1 (8)
IB Bus (8)
Peripheral
Interface
Interrupt
Handler
Clock
&
Reset
Bus Interface
Instruction Sequencer
DST (16)
ALU
Data
Memory
Interface
Memory Data (16)
Register
File
8XC251SA/SB/SP/SQ Microcontroller
A4214-01
4
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
1.0
NOMENCLATURE
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in
Options
no mark
Commercial operating temperature range (0C to 70C) with
Intel standard burn-in.
T
Express operating temperature range (-40C to 85C) with
Intel standard burn-in.
Packaging Options
N
44-pin Plastic Leaded Chip Carrier (PLCC)
P
40-pin Plastic Dual In-line Package (PDIP)
C
40-pin Ceramic Dual In-line Package (Ceramic DIP)
Program Memory Options
0
Without ROM/OTPROM/EPROM
3
ROM
7
User programmable OTPROM/EPROM
Process Information
C
CHMOS
Product Family
251
8-bit control architecture
Device Memory Options
SA
1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM
SB
1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
SP
512-byte RAM/8-Kbyte ROM/OTPROM/EPROM
SQ
512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
Device Speed
16
External clock frequency
Program-memory Options
XXXXX
XX
X
X
8
XX
X
Packaging Options
Temperature and Burn-in Options
A2815-01
Process Information
Product Family Device Speed
PRELIMINARY
5
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ family nomenclature.
.
Table 3 lists the 8XC251SA/SB/SP/SQ packages.
Table 3. Package Information
Table 2. Proliferation Options
8XC251SA/SB/SP/SQ
(0 16 MHz; 5 V 10%)
80C251SB16
CPU-only
80C251SQ16
CPU-only
83C251SA16
ROM
83C251SB16
ROM
83C251SP16
ROM
83C251SQ16
ROM
87C251SA16
OTPROM/EPROM
87C251SB16
OTPROM/EPROM
87C251SP16
OTPROM/EPROM
87C251SQ16
OTPROM/EPROM
Pkg.
Definition
Temperature
N
44 ld. PLCC
0C to +70C
P
40 ld. Plastic DIP
0C to +70C
C
40 ld. Ceramic DIP
0C to +70C
TN
44 ld. PLCC
-40C to +85C
TP
40 ld. Plastic DIP
-40C to +85C
6
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
2.0
PINOUT
Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA# / V
PP
V
SS2
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
P1.4 / CEX1
P1.3 / CEX0
P1.2 / ECI
P1.1 / T2EX
P1.0 /
T2
V
SS1
V
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
A4205-02
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
V
CC2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
39
38
37
36
35
34
33
32
31
30
29
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
View of component as
mounted on PC board
7
8
9
10
11
12
13
14
15
16
17
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
SS
V
SS2
A8 / P2.0
A9 / P2.1
A10 / P2.2
A11 / P2.3
A12 / P2.4
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
PRELIMINARY
7
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA# / V
PP
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
A12 / P2.4
A11 / P2.3
A10 / P2.2
A9 / P2.1
A8 / P2.0
P1.0 / T2
P1.1 / T2EX
P1.2 / ECI
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
SS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
View of
component
as mounted
on PC board
A4206-03
8
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 4. 8XC251SA/SB/SP/SQ Pin Assignment
PLCC
DIP
Name
PLCC
DIP
Name
1
V
SS
1
23
V
SS
2
2
1
P1.0/T2
24
21
A8/P2.0
3
2
P1.1/T2EX
25
22
A9/P2.1
4
3
P1.2/ECI
26
23
A10/P2.2
5
4
P1.3/CEX0
27
24
A11/P2.3
6
5
P1.4/CEX1
28
25
A12/P2.4
7
6
P1.5/CEX2
29
26
A13/P2.5
8
7
P1.6/CEX3/WAIT#
30
27
A14/P2.6
9
8
P1.7/CEX4/A17/WCLK
31
28
A15/P2.7
10
9
RST
32
29
PSEN#
11
10
P3.0/RXD
33
30
ALE/PROG#
12
V
CC
2
34
V
SS
2
13
11
P3.1/TXD
35
31
EA#/V
PP
14
12
P3.2/INT0#
36
32
AD7/P0.7
15
13
P3.3/INT1#
37
33
AD6/P0.6
16
14
P3.4/T0
38
34
AD5/P0.5
17
15
P3.5/T1
39
35
AD4/P0.4
18
16
P3.6/WR#
40
36
AD3/P0.3
19
17
P3.7/RD#/A16
41
37
AD2/P0.2
20
18
XTAL2
42
38
AD1/P0.1
21
19
XTAL1
43
39
AD0/P0.0
22
20
V
SS
44
40
V
CC
PRELIMINARY
9
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category
Address & Data
Input/Output
Name
PLCC
DIP
Name
PLCC
DIP
AD0/P0.0
43
39
P1.0/T2
2
1
AD1/P0.1
42
38
P1.1/T2EX
3
2
AD2/P0.2
41
37
P1.2/ECI
4
3
AD3/P0.3
40
36
P1.3/CEX0
5
4
AD4/P0.4
39
35
P1.4/CEX1
6
5
AD5/P0.5
38
34
P1.5/CEX2
7
6
AD6/P0.6
37
33
P1.6/CEX3/WAIT#
8
7
AD7/P0.7
36
32
P1.7/CEX4/A17/WCLK
9
8
A8/P2.0
24
21
P3.0/RXD
11
10
A9/P2.1
25
22
P3.1/TXD
13
11
A10/P2.2
26
23
P3.4/T0
16
14
A11/P2.3
27
24
P3.5/T1
17
15
A12/P2.4
28
25
A13/P2.5
29
26
Power & Ground
A14/P2.6
30
27
Name
PLCC
DIP
A15/P2.7
31
28
V
CC
44
40
P3.7/RD#/A16
19
17
V
CC
2
12
P1.7/CEX4/A17/WCLK
9
8
V
SS
22
20
V
SS
1
1
V
SS
2
23, 34
Processor Control
EA#/V
PP
35
31
Name
PLCC
DIP
P3.2/INT0#
14
12
Bus Control & Status
P3.3/INT1#
15
13
Name
PLCC
DIP
EA#/V
PP
35
31
P3.6/WR#
18
16
RST
10
9
P3.7/RD#/A16
19
17
XTAL1
21
18
ALE/PROG#
33
30
XTAL2
20
19
PSEN#
32
29
10
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
3.0
SIGNALS
Table 6. Signal Descriptions
Signal
Name
Type
Description
Alternate
Function
A17
O
18th Address Bit (A17). Output to memory as 18th external address
bit (A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,
"Device Configuration," of the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User's Manual). See also RD# and PSEN#.
P1.7/CEX4/
WCLK
A16
O
Address Line 16. See RD#.
RD#
A15:8
O
Address Lines. Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
P0.7:0
ALE
O
Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
PROG#
CEX4:0
I/O
Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
P1.6:3
P1.7/A17/
WAIT#
EA#
I
External Access. Directs program memory accesses to on-chip or off-
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EPROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
V
PP
ECI
I
PCA External Clock Input. External clock input to the 16-bit PCA
timer.
P1.2
INT1:0#
I
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
P3.3:2
PROG#
I
Programming Pulse. The programming pulse is applied to this pin for
programming the on-chip OTPROM.
ALE
P0.7:0
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
P1.1
P1.2
P1.7:3
I/O
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
T2EX
ECI
CEX3:0
CEX4/A17/
WAIT#/
WCLK
P2.7:0
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
PRELIMINARY
11
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PSEN#
O
Program Store Enable. Read signal output. This output is asserted
for a memory address range that depends on bits RD0 and RD1 in
configuration byte UCONFIG0 (see RD# and Chapter 4, "Device Con-
figuration," in the 8XC251SA/SB/SP/SQ Embedded Microcontroller
User's Manual).
--
RD#
O
Read or 17th Address Bit (A16). Read signal output to external data
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
Chapter 4, "Device Configuration," in the 8XC251SA/SB/SP/SQ
Embedded Microcontroller User's Manual).
P3.7/A16
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins
are driven to their reset conditions when a voltage greater than V
IH1
is
applied, whether or not the oscillator is running. This pin has an inter-
nal pulldown resistor, which allows the device to be reset by connect-
ing a capacitor between this pin and V
CC
.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
--
RXD
I/O
Receive Serial Data. RXD sends and receives data in serial I/O mode
0 and receives data in serial I/O modes 1, 2, and 3.
P3.0
T1:0
I
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
T2
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
P1.0
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge ini-
tiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determines the count direction: 1 = up, 0 =
down.
P1.1
TXD
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3.
P3.1
V
CC
PWR
Supply Voltage. Connect this pin to the +5V supply voltage.
--
V
CC
2
PWR
Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the 8XC51FX, V
SS
2
can be uncon-
nected without loss of compatibility. (Not available on DIP)
--
Table 6. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate
Function
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
12
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
V
PP
I
Programming Supply Voltage. The programming supply voltage is
applied to this pin for programming the on-chip OTPROM/EPROM.
EA#
V
SS
GND
Circuit Ground. Connect this pin to ground.
--
V
SS
1
GND
Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SA/SB/SP/SQ as
a pin-for-pin replacement for the 8XC51BH, V
SS
1
can be unconnected
without loss of compatibility. (Not available on DIP)
--
V
SS
2
GND
Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this pin to
ground is recommended. However, when using the 8XC251SB as a
pin-for-pin replacement for the 8XC51FX, V
SS
2
can be unconnected
without loss of compatibility. (Not available on DIP)
--
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal `system ready' to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at port 1.7
(WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with
a period of one-half the oscillator frequency.
P1.7/CEX4/
A17
WR#
O
Write. Write signal output to external memory.
P3.6
XTAL1
I
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
--
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
--
Table 6. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate
Function
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
PRELIMINARY
13
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 7. Memory Signal Selections (RD1:0)
RD1:0
P1.7/CEX/
A17/WCLK
P3.7/RD#/A16 PSEN#
WR#
Features
0 0
A17
A16
Asserted for
all addresses
Asserted for writes to
all memory locations
256-Kbyte external
memory
0 1
P1.7/CEX4/
WCLK
A16
Asserted for
all addresses
Asserted for writes to
all memory locations
128-Kbyte external
memory
1 0
P1.7/CEX4/
WCLK
P3.7 only
Asserted for
all addresses
Asserted for writes to
all memory locations
64-Kbyte external
memory. One
additional port pin.
1 1
P1.7/CEX4/
WCLK
RD# asserted
for addresses
7F:FFFFH
Asserted for
80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.
14
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
4.0
ADDRESS MAP
Table 8. 8XC251SA/SB/SP/SQ Address Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory except the top eight bytes (FF:FFF8HFF:FFFFH) which are
reserved for the configuration array.
1, 3, 10
FF:3FFFH
FF:0000H
External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH,
16Kbytes FF:0000H - FF:3FFFH).
3, 4, 5
FE:FFFFH
FE:0000H
External Memory
3
FD:FFFFH
02:0000H
Reserved
6
01:FFFFH
01:0000H
External Memory
3
00:FFFFH
00:E000H
External memory or with configuration bit EMAP# = 0, addresses in this range
access on-chip code memory in region FF: (16 Kbyte devices only).
5, 7
00:DFFFH
00:0420H
External Memory
7
00:041FH
00:0080H
On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H -
00:041FH)
7
00:007FH
00:0020H
On-chip RAM
8
00:001FH
00:0000H
Storage for R0R7 of Register File
2, 9
NOTES:
1.
18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2.
The special function registers (SFRs) and the register file have separate internal address spaces.
3.
Data in this area is accessible by indirect addressing only.
4.
Devices reset into internal or external starting locations depending on the state of EA# and configura-
tion byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB/SP/SQ
Embedded Microcontroller User's Manual.
5.
The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000HFF:3FFFH to map
into region 00:. In this case, if EA# = 1, a data read to 00:E000H00:FFFFH is redirected to internal
ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte
ROM/OTPROM/EPROM devices.
6.
This reserved area returns indeterminate values.
7.
Data is accessible by direct and indirect addressing.
8.
Data is accessible by direct, indirect, and bit addressing.
9.
Data is accessible by direct, indirect, and register addressing.
10. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
PRELIMINARY
15
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.0
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ................................... -65C to +150C
Voltage on EA#/V
PP
Pin to V
SS
......................... 0 V to +13.0 V
Voltage on Any other Pin to V
SS
..................... -0.5 V to +6.5 V
I
OL
per I/O Pin ................................................................. 15 mA
Power Dissipation .......................................................... 1.5 W
OPERATING CONDITIONS
T
A
(Ambient Temperature Under Bias):
Commercial ................................................. 0C to +70C
Express .................................................... -40C to +85C
V
CC
(Digital Supply Voltage) .............................. 4.5 V to 5.5 V
V
SS
..................................................................................... 0 V
NOTE
Maximum power dissipation is
based on package heat-transfer
limitations, not device power
consumption.
NOTICE: This document contains preliminary
information on new products in production. The
specifications are subject to change without notice.
Verify with your local Intel sales office that you
have the latest datasheet before finalizing a
design.
WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause perma-
nent damage. These are stress ratings only. Oper-
ation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.
16
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.1
D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Table 9. DC Characteristics at V
CC
= 4.5 5.5 V
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
V
IL
Input Low Voltage
(except EA#)
-0.5
0.2V
CC
0.1
V
V
IL
1
Input Low Voltage
(EA#)
0
0.2V
CC
0.3
V
V
IH
Input High Voltage
(except XTAL1, RST)
0.2V
CC
+ 0.9
V
CC
+ 0.5
V
V
IH
1
Input High Voltage
(XTAL1, RST)
0.7V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
V
I
OL
= 100 A
I
OL
= 1.6 mA
I
OL
= 3.5 mA
(Note 1, Note 2)
V
OL
1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
I
OL
= 200 A
I
OL
= 3.2 mA
I
OL
= 7.0 mA
(Note 1, Note 2)
V
OH
Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)
V
CC
0.3
V
CC
0.7
V
CC
1.5
V
I
OH
= -10 A
I
OH
= -30 A
I
OH
= -60 A
(Note 3)
NOTES:
1.
Under steady-state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
port 0
26 mA
ports 13
15 mA
Maximum Total I
OL
for
all output pins
71 mA
If I
OL
exceeds the test conditions, V
OL
may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2.
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3.
Capacitive loading on ports 0 and 2 causes the V
OH
on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4.
Typical values are obtained using V
CC
= 5.0, T
A
= 25C and are not guaranteed.
PRELIMINARY
17
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
V
OH
1
Output High Voltage
(Port 0 in External
Address)
V
CC
0.3
V
CC
0.7
V
CC
1.5
V
I
OH
= -200 A
I
OH
= -3.2 mA
I
OH
= -7.0 mA
V
OH
2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
V
CC
0.3
V
CC
0.7
V
CC
1.5
V
I
OH
= -200 A
I
OH
= -3.2 mA
I
OH
= -7.0 mA
I
IL
Logical 0 Input Cur-
rent (Port 1, 2, 3)
-50
A
VIN = 0.45 V
I
LI
Input Leakage Cur-
rent (Port 0)
+/-10
A
0.45 < VIN < V
CC
I
TL
Logical 1-to-0 Transi-
tion Current (Port 1,
2, 3)
-650
A
VIN = 2.0 V
R
RST
RST Pulldown Resis-
tor
40
225
k
C
IO
Pin Capacitance
10
(Note 4)
pF
F
OSC
= 16 MHz
T
A
= 25 C
I
PD
Powerdown Current
10
(Note 4)
20
A
I
DL
Idle Mode Current
12
(Note 4)
15
mA
F
OSC
= 16 MHz
I
CC
Operating Current
45
(Note 4)
80
mA
F
OSC
= 16 MHz
Table 9. DC Characteristics at V
CC
= 4.5 5.5 V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
NOTES:
1.
Under steady-state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
port 0
26 mA
ports 13
15 mA
Maximum Total I
OL
for
all output pins
71 mA
If I
OL
exceeds the test conditions, V
OL
may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2.
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3.
Capacitive loading on ports 0 and 2 causes the V
OH
on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4.
Typical values are obtained using V
CC
= 5.0, T
A
= 25C and are not guaranteed.
18
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 5. I
PD
Test Condition, Powerdown Mode, V
CC
= 2.0 5.5V
Figure 6. I
CC
vs. Frequency (Mhz)
A4208-01
V
CC
V
CC
V
CC
I
PD
P0
EA#
XTAL1
V
SS
XTAL2
RST
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
(NC)
All other 8XC251SA/SB/SP/SQ pins are unconnected.
A4400-01
70
60
50
40
30
20
10
0
2
1
3
4
5
6
7
8
9
10
16
Frequency at XTAL (MHz)
11
12
13
14
15
typ Active mode (mA)
max Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
I
CC
(mA)
PRELIMINARY
19
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.2
Definition of AC Symbols
5.3
A.C. Characteristics
Test Conditions: Capacitive load on all pins = 50 pF.
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD#/PSEN#
Z
Floating
W
WR#
Table 11 lists AC timing parameters for the
8XC251SA/SB/SP/SQ with no wait states. External
wait states can be added by extending
PSEN#/RD#/WR# and/or by extending ALE. In the
table, Notes 3 and 5 mark parameters affected by an
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Figures 810 show the bus cycles with the timing
parameters.
Table 11. AC Characteristics
Symbol
Parameter
@ Max F
osc
(1)
F
osc
Variable
Units
Min
Max
Min
Max
F
OSC
XTAL1 Frequency
N/A
N/A
0
16
MHz
T
OSC
1/F
OSC
@ 12 MHz
@ 16 MHz
N/A
N/A
83.3
62.5
ns
T
LHLL
ALE Pulse Width
@ 12 MHz
@ 16 MHz
73.3
52.5
(1+2M)
T
OSC
10
ns
(3)
T
AVLL
Address Valid to ALE Low
@ 12 MHz
@ 16 MHz
58.3
37.5
(1+2M)
T
OSC
25
ns
(3)
T
LLAX
Address Hold after ALE Low
@ 12 MHz
@ 16 MHz
15
15
15
ns
NOTES:
1.
16 MHz.
2.
Specifications for PSEN# are identical to those for RD#.
3.
In the formula, M=Number of wait states (0 or 1) for ALE.
4.
In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
5.
"Typical" specifications are untested and not guaranteed.
20
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
RLRH
(2)
RD# or PSEN# Pulse Width
@ 12 MHz
@ 16 MHz
146.6
105
2(1+N)
T
OSC
20
ns
(4)
T
WLWH
WR# Pulse Width
@ 12 MHz
@ 16 MHz
146.6
105
2(1+N)
T
OSC
20
ns
(4)
T
LLRL
(2)
ALE Low to RD# or PSEN# Low
@ 12 MHz
@ 16 MHz
58.3
37.5
T
OSC
25
ns
T
LHAX
ALE High to Address Hold
@ 12 MHz
@ 16 MHz
83.3
62.5
(1+2M)T
OSC
ns
(3)
T
RLDV
(2)
RD#/PSEN# Low to valid Data/Instruction In
@ 12 MHz
@ 16 MHz
106.6
65
2(1+N)
Tosc 60
ns
(4)
T
RHDX
(2)
Data/Instruction Hold Time. Occurs after
RD#/PSEN# are exerted to V
OH
0
0
ns
T
RLAZ
(2)
RD#/PSEN# Low to Address Float
Typ.=0
(5)
2
Typ. = 0
(5)
2
ns
T
RHDZ
1
Instruction Float after RD#/PSEN# High
commercial @ 12 MHz and 16 MHz
express @ 12 MHz and 16 MHz
Typ.=2
5
Typ.=2
5
(5)
18
10
Typ.=25
Typ.=25
(5)
18
10
ns
T
RHDZ
2
Data Float after RD#/PSEN# High
@ 12 MHz
@ 16 MHz
156.6
115
2Tosc 10
ns
T
RHLH
1
RD#/PSEN# High to ALE High (Instruction)
@ 12 MHz
@ 16 MHz
10
10
10
ns
T
RHLH2
RD#/PSEN# High to ALE High (Data)
@ 12 MHz
@ 16 MHz
156.6
115
2T
osc
- 10
ns
T
WHLH
WR# High to ALE High
@ 12 MHz
@ 16 MHz
171.6
130
2T
osc
+ 5
ns
Table 11. AC Characteristics (Continued)
Symbol
Parameter
@ Max F
osc
(1)
F
osc
Variable
Units
Min
Max
Min
Max
NOTES:
1.
16 MHz.
2.
Specifications for PSEN# are identical to those for RD#.
3.
In the formula, M=Number of wait states (0 or 1) for ALE.
4.
In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
5.
"Typical" specifications are untested and not guaranteed.
PRELIMINARY
21
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
AVDV
1
Address (P0) Valid to Valid Data/Instruction In
@ 12 MHz
@ 16 MHz
243.2
160
4(1+M/2)
T
OSC
90
ns
(3)
T
AVDV
2
Address (P2) Valid to Valid Data/Instruction In
@ 12 MHz
@ 16 MHz
268.2
185
4(1+M/2)
T
OSC
65
ns
(3)
T
AVDV
3
Address (P0) Valid to Valid Instruction In
@ 12 MHz
@ 16 MHz
116.6
75
2T
OSC
50
ns
T
AVRL
(2)
Address Valid to RD#/PSEN# Low
@ 12 MHz
@ 16 MHz
121.6
80
2(1+M)
T
OSC
45
ns
(3)
T
AVWL
1
Address (P0) Valid to WR# Low
@ 12 MHz
@ 16 MHz
126.6
85
2(1+M)
T
OSC
40
ns
(3)
T
AVWL
2
Address (P2) Valid to WR# Low
@ 12 MHz
@ 16 MHz
146.6
105
2(1+M)
T
OSC
20
ns
(3)
T
WHQX
Data Hold after WR# High
@ 12 MHz
@ 16 MHz
63.3
42.5
T
OSC
20
ns
T
QVWH
Data Valid to WR# High
@ 12 MHz
@ 16 MHz
138.6
97
2(1+N)
T
OSC
28
ns
(4)
T
WHAX
WR# High to Address Hold
@ 12 MHz
@ 16 MHz
156.6
115
2T
OSC
10
ns
Table 11. AC Characteristics (Continued)
Symbol
Parameter
@ Max F
osc
(1)
F
osc
Variable
Units
Min
Max
Min
Max
NOTES:
1.
16 MHz.
2.
Specifications for PSEN# are identical to those for RD#.
3.
In the formula, M=Number of wait states (0 or 1) for ALE.
4.
In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
5.
"Typical" specifications are untested and not guaranteed.
22
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.3.1
EXTERNAL BUS CYCLES, NONPAGE MODE
Figure 7. External Bus Cycle: Code Fetch (Nonpage Mode)
XTAL1
ALE
TLHLL
A7:0
TRHDZ1
RD#/PSEN#
P0
P2/A16/A17
TRHDX
TRHLH1
TRLRH
TLLRL
TAVLL
TRLDV
TAVRL
TAVDV1
TAVDV2
TOSC
A4211-03
TLHAX
Instruction In
The value of this parameter depends on wait states. See the table of AC characteristics.
A15:8/A16/A17
D7:0
TRLAZ
TLLAX
PRELIMINARY
23
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 8. External Bus Cycle: Data Read (Nonpage Mode)
XTAL1
ALE
TLHLL
A7:0
D7:0
RD#/PSEN#
P0
P2/A16/A17
TRHDX
TRHLH2
TRLRH
TLLRL
TAVLL
TLLAX
TRLDV
TAVRL
TAVDV1
TAVDV2
TOSC
A4210-03
TLHAX
Data In
The value of this parameter depends on wait states. See the table of AC characteristics.
A15:8/A16/A17
TRHDZ2
TRLAZ
24
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 9. External Bus Cycle: Data Write (Nonpage Mode)
WR#
P0
P2/A16/A17
TLHLL
TWLWH
TWHLH
A4179-01
XTAL1
ALE
TOSC
TWHQX
TQVWH
TWHQX
TAVWL1
TAVWL2
TWHAX
A7:0
D7:0
Data Out
A15:8/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
TLLAX
TLHAX
TAVLL
PRELIMINARY
25
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.3.2
EXTERNAL BUS CYCLES, PAGE MODE
Figure 10. External Bus Cycle: Code Fetch (Page Mode)
XTAL1
ALE
TLHLL
A15:8
D7:0
TRHDZ1
RD#/PSEN#
P2
P0/A16/A17
TRHDX
TLLRL
TAVLL
TRLDV
TRLAZ
TAVRL
TAVDV1
TAVDV2
TOSC
A4213-02
TLHAX
Instruction In
A7:0/A16/A17
D7:0
Instruction In
A7:0/A16/A17
Page Miss
Page Hit
TAVDV3
The value of this parameter depends on wait states. See the table of AC characteristics.
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2T
OSC
); a page miss requires two states (4T
OSC
).
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
TLLAX
26
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 11. External Bus Cycle: Data Read (Page Mode)
XTAL1
ALE
TLHLL
TRHDZ2
RD#/PSEN#
P2
P0/A16/A17
TRHDX
TRHLH2
TRLRH
TLLRL
TAVLL
TRLDV
TRLAZ
TAVRL
TAVDV1
TAVDV2
TOSC
A4212-03
TLHAX
Data In
The value of this parameter depends on wait states. See the table of AC characteristics.
A15:8
A7:0/A16/A17
D7:0
TLLAX
PRELIMINARY
27
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 12. External Bus Cycle: Data Write (Page Mode)
WR#
P2
P0/A16/A17
TLHLL
TWLWH
TWHLH
A4182-01
XTAL1
ALE
TOSC
TWHQX
TQVWH
TWHQX
TAVWL1
TAVWL2
TWHAX
A15:8
D7:0
Data Out
A7:0/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
TAVLL
TLLAX
TLHAX
28
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.3.3
DEFINITION OF REAL-TIME WAIT SYMBOLS
5.3.4
EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES
Figure 13. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)
Table 12. Real-time Wait Timing Symbol Definitions
Signals
Conditions
A
Address
L
Low
D
Data
X
Hold
C
WCLK
V
Setup
Y
WAIT#
W
WR#
R
RD#/PSEN#
A0-A7
WCLK
ALE
RD#/PSEN#
WAIT#
P0
P2
A8-A15
A5000-01
State 1
State 2
State 3
State 1 (next cycle)
T
CLYX
min
T
CLYV
A0-A7
D0-D7
stretched
A8-A15
stretched
RD#/PSEN# stretched
T
CLYX
max
T
RLYV
T
RLYX
max
T
RLYX
min
PRELIMINARY
29
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 14. External Bus Cycle: Data Write (Nonpage Mode)
Figure 15. External Bus Cycle: Code Fetch/Data Read (Page Mode)
A0-A7
WCLK
ALE
WR#
T
WLYV
WAIT#
P0
P2
A5002-01
State 1
State 2
State 3
State 4
T
CLYX
min
T
CLYV
D0-D7
stretched
A8-A15
stretched
WR# stretched
T
WLYX
max
T
WLYX
min
T
CLYX
max
A8-A15
WCLK
ALE
RD#/PSEN#
WAIT#
P2
P0
A0-A7
A5001-01
State 1
State 2
State 3
State 1 (next cycle)
T
CLYX
min
T
CLYV
A8-A15
D0-D7
stretched
A0-A7
stretched
RD#/PSEN# stretched
T
CLYX
max
T
RLYV
T
RLYX
max
T
RLYX
min
30
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 16. External Bus Cycle: Data Write (Page Mode)
Table 13. Real-time Wait AC Timing
Symbol
Parameter
Min
Max
Units
T
CLYV
Wait Clock Low to Wait Set-up
0
T
OSC
20
ns
T
CLYX
Wait Hold after Wait Clock Low
(2W)T
OSC
+ 5
(1+2W)T
OSC
20
ns
T
RLYV
PSEN#/RD# Low to Wait Set-up
0
T
OSC
20
ns
T
RLYX
Wait Hold after PSEN#/RD# Low
(2W)T
OSC
+ 5
(1+2W)T
OSC
20
ns
T
WLYV
WR# Low to Wait Set-up
0
T
OSC
20
ns
T
WLYX
Wait Hold after WR# Low
(2W)T
OSC
+ 5
(1+2W)T
OSC
20
ns
A8-A15
WCLK
ALE
WR#
T
WLYV
WAIT#
P2
P0
A5003-01
State 1
State 2
State 3
State 4
T
CLYX
min
T
CLYV
D0-D7
stretched
A0-A7
stretched
WR# stretched
T
WLYX
max
T
WLYX
min
T
CLYX
max
PRELIMINARY
31
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.4
AC Characteristics -- Serial Port, Shift Register Mode
Figure 17. Serial Port Waveform -- Shift Register Mode
5.5
External Clock Drive
Table 14. Serial Port Timing -- Shift Register Mode
Symbol
Parameter
Min
Max
Units
T
XLXL
Serial Port Clock Cycle Time
12T
OSC
ns
T
QVSH
Output Data Setup to Clock Rising Edge
10T
OSC
133
ns
T
XHQX
Output Data hold after Clock Rising Edge
2T
OSC
117
ns
T
XHDX
Input Data Hold after Clock Rising Edge
0
ns
T
XHDV
Clock Rising Edge to Input Data Valid
10T
OSC
133
ns
Table 15. External Clock Drive
Symbol
Parameter
Min
Max
Units
1/T
CLCL
Oscillator Frequency (F
OSC
)
16
MHz
T
CHCX
High Time
20
ns
T
CLCX
Low Time
20
ns
T
CLCH
Rise Time
10
ns
T
CHCL
Fall Time
10
ns
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RXD
(In)
RXD
(Out)
TXD
0
1
2
3
4
5
6
7
TQVXH
TXLXL
TXHDX
TXHQX
TXHDV
A2592-02
Set TI
Set RI
TAV
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
32
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 18. External Clock Drive Waveforms
Figure 19. AC Testing Input, Output Waveforms
Figure 20. Float Waveforms
0.7 V
CC
A4119-01
0.45 V
V
CC
0.5
0.2 V
CC
0.1
T
CHCL
T
CLCX
T
CLCL
T
CLCH
T
CHCX
AC inputs during testing are driven at V
CC
0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
0.45 V
Inputs
Outputs
A4118-01
V
IH MIN
V
OL MAX
V
CC
0.5
0.2 V
CC
+ 0.9
0.2 V
CC
0.1
a min of V
IH
for a logic 1 and V
OL
for a logic 0.
V
LOAD
+ 0.1 V
V
LOAD
0.1 V
Timing Reference
Points
V
LOAD
V
OH
0.1 V
V
OL
+ 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading V
OH
/V
OL
level occurs
with I
OL/
I
OH
=
20 mA.
A4117-01
33
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.0
THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
change depending on operating conditions and
application requirements. The Intel
Packaging
Handbook
(order number 240800) describes Intel's
thermal impedance test methodology.
Table 16. Thermal Characteristics
Package Type
JA
JC
44-pin PLCC
46
C/W
16
C/W
40-pin PDIP
45
C/W
16
C/W
40-pin Ceramic DIP
30.5
C/W
10
C/W
7.0
NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION
CHARACTERISTICS
7.1
Definition of Nonvolatile Memory Symbols
Table 17. Nonvolatile Memory Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
Q
Data Out
V
Valid
S
Supply
X
No Longer Valid
G
PROG#
Z
Floating
E
Enable
34
PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
7.2
Programming and Verification Timing for Nonvolatile Memory
Figure 21. Timing for Programming and Verification of Nonvolatile Memory
Table 18. Nonvolatile Memory Programming and Verification Characteristics at
T
A
= 21 27 C, V
CC
= 5 V, and V
SS
= 0 V
Symbol
Definition
Min
Max
Units
V
PP
Programming Supply Voltage
12.5
13.5
D.C. Volts
I
PP
Programming Supply Current
75
mA
F
OSC
Oscillator Frequency
4.0
6.0
MHz
T
AVGL
Address Setup to PROG# Low
48T
OSC
T
GHAX
Address Hold after PROG#
48T
OSC
T
DVGL
Data Setup to PROG# Low
48T
OSC
T
GHDX
Data Hold after PROG#
48T
OSC
T
EHSH
ENABLE High to V
PP
48T
OSC
T
SHGL
V
PP
Setup to PROG# Low
10
s
T
GHSL
V
PP
Hold after PROG#
10
s
T
GLGH
PROG# Width
90
110
s
PROG#
EA#/V
PP
P1, P3
A4128-01
Address
Address (16 Bits)
P2
Data Out
Data In (8 Bits)
TAVQV
TGHDX
TGHAX
TDVGL
TAVGL
TGHGL
TGHSL
1
2
3
4
5
TGLGH
TSHGL
P0
Mode
Mode (8 Bits)
TEHSH
TELQV
TEHQZ
12.75V
Programming Cycle
Verification Cycle
5V
PRELIMINARY
35
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
AVQV
Address to Data Valid
48T
OSC
T
ELQV
ENABLE Low to Data Valid
48T
OSC
T
EHQZ
Data Float after ENABLE
0
48T
OSC
T
GHGL
PROG# High to PROG# Low
10
s
Table 18. Nonvolatile Memory Programming and Verification Characteristics at
T
A
= 21 27 C, V
CC
= 5 V, and V
SS
= 0 V(Continued)
8.0
ERRATA
There are no known errata for this product.
9.0
REVISION HISTORY
This (-003) revision of the 8XC251SA/SB/SP/SQ
datasheet contains information on products with
"[M] [C] '94 '95 C" as the last line of the topside
marking. This datasheet replaces earlier product
information. The following changes appear in the -
003 datasheet:
1.
Real-time wait state operation is described in
the datasheet.
2.
Memory map reserved locations are newly
defined and the Memory Map is now referred
to as the "Address Map."
3.
AC Characteristics have been updated. The
following AC parameters have changed: T
LLAX
,
T
RLRH
, T
WLWH
, T
LLRL
, T
RLDV
, T
RHDZ
1
, T
RHDZ
2
, T
RHLH
2
,
T
WHLH
, T
AVDV
1
, T
AVDV
2
, T
AVRL
, T
AVWL
1
, T
AVWL
2
,
T
QVWH
, and T
WHAX
.
4.
DC Characteristics have been updated. The
following DC specs have changed: I
PD
max, I
DL
typical, I
DL
max, I
CC
typical, and I
CC
max.
5.
An I
CC
vs. Frequency graph is included.
6.
Process information is no longer contained in
the datasheet.
7.
The section "Programming and Verifying Non-
volatile Memory" has been deleted. See the
8XC251SA/SB/SP/SQ Embedded Microcon-
troller User's Manual. Timing and Characteris-
tics for Programming and Verifying Nonvolatile
memory have been retained in this datasheet.
8.
Signature Byte information has been deleted.
See the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User's Manual.
9.
Sections in the datasheet are numbered.
10. New sections have been created to provide
better organization. These include "Nomencla-
ture," "Pinout," "Signals," "Address Map,"
"Electrical Characteristics," "Thermal Charac-
teristics," "Nonvolatile Memory Programming
and Verification Characteristics", "Errata," and
"Revision History"
11.
Proliferation Options and Package Options are
in the Nomenclature section.
12. Temperature range is contained in the Electri-
cal Characteristics section under "Operating
Conditions"
13. Bus timing diagrams have been organized into
subsections.
The (-002) revision of the 8XC251SA/SB/SP/SQ
datasheet contains information on products with
"[M] [C] '94 '95 B" as the last line of the topside
marking. This datasheet replaces earlier product
information. The following changes appear in the -
002 datasheet:
1.
A corrected PDIP diagram appears on page 7.
2.
A corrected formula to calculate T
LHLL
is
described on page 17.
3.
The RD#/PSEN# waveform is changed in Fig-
ure 11 on page 25.
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