November, 1997

Order Number: 273129-001

ADVANCE INFORMATION

8xC251TA/TB/TP/TQ

HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Commercial/Express

Real-time and Programmed Wait State
Bus Operation

Binary-code Compatible with MCS

Pin Compatible with 44-pin PLCC and
40-pin PDIP MCS 51 Sockets

Register-based MCS

251 Architecture

-- 40-byte Register File
-- Registers Accessible as Bytes,

Words, or Double Words

Enriched MCS 51 Instruction Set
-- 16-bit and 32-bit Arithmetic and

Logic Instructions

-- Compare and Conditional Jump

Instructions

-- Expanded Set of Move Instructions

Linear Addressing

256-Kbyte Expanded External
Code/Data Memory Space

ROM Options:
16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or
without ROM

16-bit Internal Code Fetch

64-Kbyte Extended Stack Space

On-chip Data RAM Options:
1-Kbyte (TA/TB) or 512-Byte (TP/TQ)

8-bit, 2-clock External Code Fetch in
Page Mode

Fast MCS 251 Instruction Pipeline

User-selectable Configurations:
-- External Wait States (0-3 wait

states)

-- Address Range & Memory Mapping
-- Page Mode
-- Extended Data Float Timings or

8xC251Sx Compatible AC Timings

32 Programmable I/O Lines

Eight Maskable Interrupt Sources with
Four Programmable Priority Levels

Three Flexible 16-bit Timer/counters

Hardware Watchdog Timer

Programmable Counter Array
-- High-speed Output
-- Compare/Capture Operation
-- Pulse Width Modulator
-- Watchdog Timer

Two Programmable Serial I/O Ports
-- Framing Error Detection
-- Automatic Address Recognition

High-performance CHMOS Technology

Static Standby to 24-MHz Operation

Complete System Development
Support
-- Compatible with Existing Tools
-- MCS 251 Tools Available:

Compiler, Assembler, Debugger,
ICE

Package Options (PDIP and PLCC)

Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications. Intel may make changes to specifications and product descriptions at any time, without
notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before
placing your product order.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.

The 8xC251TA/TB/TP/TQ may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.

Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:

Intel Corporation
P.O. Box 5937
Denver CO 80217-9808
or call 1-800-548-4725.

Many documents are available for download from Intel's website at http://www.intel.com.

*Third party brands and names are the property of their respective owners.

Contents

ADVANCE INFORMATION

iii

8xC251TA/TB/TP/TQ

HIGH-PERFORMANCE CHMOS Microcontroller

Commercial/Express

1.0 INTRODUCTION ......................................................................................................................................... 1

2.0 NOMENCLATURE ...................................................................................................................................... 2

3.0 PINOUT ....................................................................................................................................................... 4

4.0 SIGNALS ..................................................................................................................................................... 8

5.0 ADDRESS MAP ........................................................................................................................................ 11

6.0 ELECTRICAL CHARACTERISTICS ......................................................................................................... 12

6.1 D.C. Characteristics ........................................................................................................................... 12

6.2 Definition of AC Symbols ................................................................................................................... 14

6.3 A.C. Characteristics ........................................................................................................................... 14

6.3.1 External Bus Cycles, Nonpage Mode ..................................................................................... 18

6.3.2 External Bus Cycles, Page Mode ........................................................................................... 21

6.3.3 Definition of Real-Time Wait Symbols .................................................................................... 24

6.3.4 External Bus Cycles, Real-Time Wait States .......................................................................... 24

6.4 AC Characteristics -- Serial Port, Shift Register Mode ..................................................................... 28

6.5 External Clock Drive .......................................................................................................................... 29

7.0 THERMAL CHARACTERISTICS .............................................................................................................. 30

Contents

ADVANCE INFORMATION

FIGURES

Figure 1.

8xC251TA/TB/TP/TQ Block Diagram ........................................................................................ 1

Figure 2.

The 8xC251TA/TB/TP/TQ Family Nomenclature....................................................................... 2

Figure 3.

8xC251TA/TB/TP/TQ 44-pin PLCC Package ............................................................................ 4

Figure 4.

8xC251TA/TB/TP/TQ 40-pin PDIP Packages............................................................................ 5

Figure 5.

External Bus Cycle: Code Fetch (Nonpage Mode) .................................................................. 18

Figure 6.

External Bus Cycle: Data Read (Nonpage Mode) ................................................................... 19

Figure 7.

External Bus Cycle: Data Write (Nonpage Mode).................................................................... 20

Figure 8.

External Bus Cycle: Code Fetch (Page Mode) ........................................................................ 21

Figure 9.

External Bus Cycle: Data Read (Page Mode).......................................................................... 22

Figure 10.

External Bus Cycle: Data Write (Page Mode).......................................................................... 23

Figure 11.

External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)................................................ 24

Figure 12.

External Bus Cycle: Data Write (Nonpage Mode).................................................................... 25

Figure 13.

External Bus Cycle: Code Fetch/Data Read (Page Mode) ...................................................... 26

Figure 14.

External Bus Cycle: Data Write (Page Mode).......................................................................... 27

Figure 15.

Serial Port Waveform -- Shift Register Mode.......................................................................... 28

Figure 16.

External Clock Drive Waveforms ............................................................................................. 29

Figure 17.

AC Testing Input, Output Waveforms ...................................................................................... 29

Figure 18.

Float Waveforms...................................................................................................................... 30

TABLES

Table 1.

Description of Product Nomenclature ........................................................................................ 2

Table 2.

Proliferation Options .................................................................................................................. 3

Table 3.

Package Information .................................................................................................................. 3

Table 4.

8xC251TA/TB/TP/TQ Pin Assignment ....................................................................................... 6

Table 5.

8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category .............. 7

Table 6.

Signal Descriptions .................................................................................................................... 8

Table 7.

Memory Signal Selections (RD1:0) .......................................................................................... 10

Table 8.

8xC251TA/TB/TP/TQ Address Map ......................................................................................... 11

Table 9.

DC Characteristics at V

= 4.5 5.5 V .................................................................................. 12

Table 10.

AC Timing Symbol Definitions ................................................................................................. 14

Table 11.

AC Characteristics ................................................................................................................... 14

Table 12.

Real-time Wait Timing Symbol Definitions ............................................................................... 24

Table 13.

Real-Time Wait AC Timing ...................................................................................................... 27

Table 14.

Serial Port Timing -- Shift Register Mode ............................................................................... 28

Table 15.

External Clock Drive ................................................................................................................ 29

Table 16.

Thermal Characteristics ........................................................................................................... 30

ADVANCE INFORMATION

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

1.0

INTRODUCTION

A member of the Intel family of 8-bit MCS 251 micro-
controllers, the 8xC251TA/TB/TP/TQ is binary-code
compatible with MCS 51 microcontrollers and pin
compatible with 40-pin PDIP and 44-pin PLCC
MCS 51 microcontrollers. MCS 251 microcontrollers

feature an enriched instruction set, linear
addressing, and efficient C-language support. The
8xC251TA/TB/TP/TQ has 512 bytes or 1 Kbyte of
on-chip RAM and is available with 8 Kbytes or 16
Kbytes of on-chip ROM, or without ROM. A variety of
features can be selected by new user-programmable
configurations.

Figure 1. 8xC251TA/TB/TP/TQ Block Diagram

A4530-01

SRC2 (8)

Code Address (24)

Clock & Reset

Code Bus (16)

Data RAM

512 Bytes

1024 Bytes

Code

OTPROM/ROM

8 Kbytes

16 Kbytes

Watchdog

Timer

Timer/

Counters

PCA

Two

Serial I/O

Ports

Peripherals

Port 2

Drivers

P2.7:0

Port 0

Drivers

P0.7:0

Port 3

Drivers

P3.7:0

Port 1

Drivers

P1.7:0

Data Address (24)

Data Bus (8)

Memory Address (16)

MCS

251 Microcontroller Core

System Bus and I/O Ports

I/O Ports and

Peripheral Signals

SRC1 (8)

IB Bus (8)

Peripheral

Interface

Interrupt

Handler

Clock

Reset

Bus Interface

Instruction Sequencer

DST (16)

ALU

Data

Memory

Interface

Memory Data (16)

File

8XC251TA/TB/TP/TQ Microcontroller

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

2.0

NOMENCLATURE

Figure 2. The 8xC251TA/TB/TP/TQ Family Nomenclature

Table 1. Description of Product Nomenclature

Parameter

Options

Description

Temperature and Burn-in
Options

no mark

Commercial operating temperature range (0°C to 70°C) with
Intel standard burn-in.

Express operating temperature range (-40°C to 85°C)
without Intel standard burn-in.

Packaging Options

44-pin Plastic Leaded Chip Carrier (PLCC)

40-pin Plastic Dual In-line Package (PDIP)

40-pin Ceramic Dual In-line Package (Ceramic DIP)

Program Memory Options

Without ROM

ROM

Process Information

CHMOS

Product Family

251

8-bit control architecture

Device Memory Options

1-Kbyte RAM/8-Kbyte ROM

1-Kbyte RAM/16-Kbyte ROM or without ROM

512-byte RAM/8-Kbyte ROM

512-byte RAM/16-Kbyte ROM or without ROM

Device Speed

External clock frequency

Program-memory Options

XXXXX

Packaging Options

Temperature and Burn-in Options

A2815-01

Process Information

Product Family Device Speed

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

Table 4. 8xC251TA/TB/TP/TQ Pin Assignment

PLCC

DIP

Name

PLCC

DIP

Name

SS1

SS2

P1.0/T2

A8/P2.0

P1.1/T2EX

A9/P2.1

P1.2/ECI/RXD1

A10/P2.2

P1.3/CEX0/TXD1

A11/P2.3

P1.4/CEX1

A12/P2.4

P1.5/CEX2

A13/P2.5

P1.6/CEX3/WAIT#

A14/P2.6

P1.7/CEX4/A17/WCLK

A15/P2.7

RST

PSEN#

P3.0/RXD

ALE

CC2

SS2

P3.1/TXD

EA#

P3.2/INT0#

AD7/P0.7

P3.3/INT1#

AD6/P0.6

P3.4/T0

AD5/P0.5

P3.5/T1

AD4/P0.4

P3.6/WR#

AD3/P0.3

P3.7/RD#/A16

AD2/P0.2

XTAL2

AD1/P0.1

XTAL1

AD0/P0.0

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

Table 5. 8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category

Address & Data

Input/Output

Name

PLCC

DIP

Name

PLCC

DIP

AD0/P0.0

P1.0/T2

AD1/P0.1

P1.1/T2EX

AD2/P0.2

P1.2/ECI/RXD1

AD3/P0.3

P1.3/CEX0/TXD1

AD4/P0.4

P1.4/CEX1

AD5/P0.5

P1.5/CEX2

AD6/P0.6

P1.6/CEX3/WAIT#

AD7/P0.7

P1.7/CEX4/A17/WCLK

A8/P2.0

P3.0/RXD

A9/P2.1

P3.1/TXD

A10/P2.2

P3.4/T0

A11/P2.3

P3.5/T1

A12/P2.4

A13/P2.5

Power & Ground

A14/P2.6

Name

PLCC

DIP

A15/P2.7

P3.7/RD#/A16

CC2

P1.7/CEX4/A17/WCLK

SS1

SS2

23, 34

Processor Control

EA#

Name

PLCC

DIP

P3.2/INT0#

Bus Control & Status

P3.3/INT1#

Name

PLCC

DIP

EA#

P3.6/WR#

RST

P3.7/RD#/A16

XTAL1

ALE

XTAL2

PSEN#

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

4.0

SIGNALS

Table 6. Signal Descriptions (Sheet 1 of 3)

Signal

Name

Type

Description

Alternate

Function

A17

18th Address Bit (A17). Output to memory as 18th external address bit
(A17) in extended bus applications, depending on the values of bits RD0
and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#.

P1.7/CEX4/
WCLK

A16

Address Line 16. See RD#.

RD#

A15:8

Address Lines. Upper address lines for the external bus.

P2.7:0

AD7:0

I/O

Address/Data Lines. Multiplexed lower address lines and data lines for
external memory.

P0.7:0

ALE

Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.

CEX4:0

I/O

Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.

P1.6:4
P1.7/A17/
WAIT#
P1.3/TXD1

EA#

External Access. Directs program memory accesses to on-chip or off-
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM if the address is within
the range of the on-chip ROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip ROM, EA# must
be strapped to ground.

ECI

PCA External Clock Input. External clock input to the 16-bit PCA timer.

P1.2/RXD1

INT1:0#

External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a
falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by
a low level on INT1:0#.

P3.3:2

P0.7:0

I/O

Port 0. This is an 8-bit, open-drain, bidirectional I/O port.

AD7:0

P1.0
P1.1
P1.2
P1.7:3

I/O

Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.

T2
T2EX
ECI/RXD1
CEX3:1
CEX4/A17/
WAIT#/
WCLK
CEX0/TXD1

P2.7:0

I/O

Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.

A15:8

P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7

I/O

Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.

RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16

PSEN#

Program Store Enable. Read signal output. This output is asserted for a
memory address range that depends on bits RD0 and RD1 in configu-
ration byte UCONFIG0 (see RD#).

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

RD#

Read or 17th Address Bit (A16). Read signal output to external data
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#).

P3.7/A16

RST

Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins are
driven to their reset conditions when a voltage greater than V

IH1

applied, whether or not the oscillator is running. This pin has an internal
pulldown resistor, which allows the device to be reset by connecting a
capacitor between this pin and V

Asserting RST when the chip is in idle mode or powerdown mode returns
the chip to normal operation.

RXD

I/O

Receive Serial Data. RXD sends and receives data in serial I/O mode 0
and receives data in serial I/O modes 1, 2, and 3.

P3.0

RXD1

I/O

Receive Serial Data 1. RXD1 sends and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2, and 3 for the 2nd
serial port.

P1.2/ECI

T1:0

Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter,
a falling edge on the T1:0 pin increments the count.

P3.5:4

I/O

Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is
the external clock input. For the clock-out mode, it is the timer 2 clock
output.

P1.0

T2EX

Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a
capture of the timer 2 registers. In auto-reload mode, a falling edge
causes the timer 2 registers to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1 = up, 0 = down.

P1.1

TXD

Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3.

P3.1

TXD1

Transmit Serial Data 1. TXD1 outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3 for the 2nd serial
port.

P1.3/CEX0

PWR

Supply Voltage. Connect this pin to the +5V supply voltage.

CC2

PWR

Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB as
a pin-for-pin replacement for the 8XC51FX, V

can be unconnected

without loss of compatibility. (Not available on DIP)

GND

Circuit Ground. Connect this pin to ground.

SS1

GND

Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TA/TB/TP/TQ as a pin-
for-pin replacement for the 8XC51BH, V

SS1

can be unconnected without

loss of compatibility. (Not available on DIP)

SS2

GND

Secondary Ground 2. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TA/TB/TP/TQ as a pin-
for-pin replacement for the 8XC51FX, V

SS2

can be unconnected without

loss of compatibility. (Not available on DIP)

Table 6. Signal Descriptions (Sheet 2 of 3)

Signal

Name

Type

Description

Alternate

Function

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

WAIT#

Real-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal `system ready' to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.

P1.6/CEX3

WCLK

Wait Clock Output. The real-time WCLK output is driven at port 1.7
(WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with a
period of one-half the oscillator frequency.

P1.7/CEX4/
A17

WR#

Write. Write signal output to external memory.

P3.6

XTAL1

Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, its output is connected to this pin. XTAL1 is the
clock source for internal timing.

XTAL2

Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, leave XTAL2 unconnected.

NOTE:

The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin
PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower
address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

Table 7. Memory Signal Selections (RD1:0)

RD1:0

P1.7/CEX/

A17/WCLK

P3.7/RD#/A16

PSEN#

WR#

Features

0 0

A17

A16

Asserted for all
addresses

Asserted for writes to
all memory locations

256-Kbyte external
memory

0 1

P1.7/CEX4/
WCLK

A16

Asserted for all
addresses

Asserted for writes to
all memory locations

128-Kbyte external
memory

1 0

P1.7/CEX4/
WCLK

P3.7 only

Asserted for all
addresses

Asserted for writes to
all memory locations

64-Kbyte external
memory. One
additional port pin.

1 1

P1.7/CEX4/
WCLK

RD# asserted
for addresses

7F:FFFFH

Asserted for

80:0000H

Asserted only for
writes to MCS 51
microcontroller data
memory

locations.

64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.

Table 6. Signal Descriptions (Sheet 3 of 3)

Signal

Name

Type

Description

Alternate

Function

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

5.0

ADDRESS MAP

Table 8. 8xC251TA/TB/TP/TQ Address Map

Internal

Address)

Description

Notes

FF:FFFFH
FF:4000H

External Memory except the top eight bytes (FF:FFF8HFF:FFFFH) which are
reserved for the configuration array.

1, 3, 10

FF:3FFFH
FF:0000H

External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH,
16Kbytes FF:0000H - FF:3FFFH).

3, 4, 5

FE:FFFFH
FE:0000H

External Memory

FD:FFFFH

02:0000H

Reserved

01:FFFFH
01:0000H

External Memory

00:FFFFH
00:E000H

External memory or with configuration bit EMAP# = 0, addresses in this range
access on-chip code memory in region FF: (16 Kbyte devices only).

5, 7

00:DFFFH
00:0420H

External Memory

00:041FH
00:0080H

On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH)

00:007FH
00:0020H

On-chip RAM

00:001FH
00:0000H

Storage for R0R7 of Register File

2, 9

NOTES:

1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).

2. The special function registers (SFRs) and the register file have separate internal address spaces.

3. Data in this area is accessible by indirect addressing only.

4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information

See EA#.

5. The 16-Kbyte ROM devices allow internal locations FF:2000HFF:3FFFH to map into region 00:. In this case, if EA# = 1,

a data read to 00:E000H00:FFFFH is redirected to internal ROM (see bit 1 in UCONFIG0). This is not available for 8-
Kbyte ROM devices.

6. This reserved area returns indeterminate values.

7. Data is accessible by direct and indirect addressing.

8. Data is accessible by direct, indirect, and bit addressing.

9. Data is accessible by direct, indirect, and register addressing.

10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte

information.

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

6.0

ELECTRICAL CHARACTERISTICS

6.1

D.C. Characteristics

Parameter values apply to all devices unless otherwise indicated.

ABSOLUTE MAXIMUM RATINGS

Storage Temperature .................................. -65°C to +150°C
Voltage: EA# Pin with respect to V

............. 0 V to +13.0 V

Voltage: Any other Pin with respect to V

... -0.5 V to +6.5 V

per I/O Pin............................................................... 15 mA

Power Dissipation ......................................................... 1.5 W

OPERATING CONDITIONS

(Ambient Temperature Under Bias):

Commercial ................................................. 0°C to +70°C

Express........................................................... -40°C to +85°C
V

(Digital Supply Voltage) ............................ 4.5 V to 5.5 V

................................................................................... 0 V

NOTE:Maximum power dissipation is based on
package heat-transfer limitations, not device power
consumption.

NOTICE:This document contains information on
products being sampled or in the initial production
phase of development. Verify with your local Intel
sales office that you have the latest datasheet
before finalizing a design.

WARNING

: Stressing the device beyond the

"Absolute Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.

Table 9. DC Characteristics at V

= 4.5 5.5 V (Sheet 1 of 2)

Symbol

Parameter

Min

Typical

Max

Units

Test Conditions

Input Low Voltage
(except EA#)

-0.5

0.2 V

0.1

IL1

Input Low Voltage
(EA#)

0.2 V

0.3

Input High Voltage
(except XTAL1, RST)

0.2 V

+ 0.9

+ 0.5

IH1

Input High Voltage
(XTAL1, RST)

0.7 V

+ 0.5

Output Low Voltage
(Port 1, 2, 3)

0.3

0.45

1.0

= 100 µA

= 1.6 mA

= 3.5 mA

(Note 1, Note 2)

OL1

Output Low Voltage
(Port 0, ALE, PSEN#)

0.3

0.45

1.0

= 200 µA

= 3.2 mA

= 7.0 mA

(Note 1, Note 2)

Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)

0.3

0.7

1.5

= -10 µA

= -30 µA

= -60 µA

(Note 3)

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

OH1

Output High Voltage
(Port 0 in External
Address)

0.3

0.7

1.5

= -200 µA

= -3.2 mA

= -7.0 mA

OH2

Output High Voltage
(Port 2 in External
Address during Page
Mode)

0.3

0.7

1.5

= -200 µA

= -3.2 mA

= -7.0 mA

Logical 0 Input
Current (Port 1, 2, 3)

-50

µA

= 0.45 V

Input Leakage
Current (Port 0)

+/-10

µA

0.45 < V

< V

Logical 1-to-0
Transition Current
(Port 1, 2, 3)

-650

µA

= 2.0 V

RST

RST Pulldown
Resistor

225

Pin Capacitance

(Note 4)

OSC

= 24 MHz

= 25 °C

Powerdown

Current 10

(Note 4)

µA

Idle Mode Current

(Note 4)

OSC

= 24 MHz

Operating

Current 70

(Note 4)

OSC

= 24 MHz

NOTES:

1. Under steady-state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:10 mA

Maximum I

per 8-bit port:

port 0

26 mA

ports 13

15 mA

Maximum Total I

for

all output pins

71 mA

If I

exceeds the test conditions, V

may exceed the related specification. Pins are not guaranteed to sink current

greater than the listed test conditions.

2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and

ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins
change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may
exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.

3. Capacitive loading on ports 0 and 2 causes the V

on ALE and PSEN# to drop below the specification when the address

lines are stabilizing.

Typical values are obtained using V

= 5.0, T

= 25°C and are not guaranteed.

Table 9. DC Characteristics at V

= 4.5 5.5 V (Sheet 2 of 2)

Symbol

Parameter

Min

Typical

Max

Units

Test Conditions

ADVANCE INFORMATION

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

6.2

Definition of AC Symbols

6.3

A.C. Characteristics

Test Conditions: Capacitive load on all pins = 50 pF.

Table 11

lists AC timing parameters for the with no

wait states. External wait states can be added by
extending PSEN#/RD#/WR# and/or by extending
ALE. In the table, Notes 2 and 3 mark parameters
affected by an

ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.

Table 10. AC Timing Symbol Definitions

Signals

Conditions

Address

High

Data In

Low

ALE

Valid

Data Out

No Longer Valid

RD#/PSEN#

Floating

WR#

Figure 6

through

Figure 8

show the bus cycles with the timing parameters.

Table 11. AC Characteristics (Sheet 1 of 4)

Symbol

Parameter

@ Max F

OSC

(1)

OSC

Variable

Units

Min

Max

Min

Max

OSC

XTAL1 Frequency

N/A

MHz

OSC

1/F

OSC

@ 16MHz
@ 24MHz

N/A

62.5
41.7

LHLL

ALE Pulse Width
@ 16MHz
@ 24MHz

55.5
34.7

(0.5+M)

OSC

-7

ns (3)

AVLL

Address Valid to ALE Low
@ 16MHz
@ 24MHz

49.5
28.7

(0.5+M)

OSC

-13

ns (3)

LLAX

Address Hold after ALE Low
@ 16MHz
@ 24MHz

10
10

ns (4)

LLAXA

Address Hold after ALE Low
@ 16MHz
@ 24MHz

20
20

ns (5)

RLRH

RD# or PSEN# Pulse Width
@ 16MHz
@ 24MHz

115

73.4

(1+N)

OSC

-10

ns (3,4)

RLRHA

RD# or PSEN# Pulse Width
@ 16MHz
@ 24MHz

51.4

(1+N)

OSC

-32

ns (3,5)

WLWH

WR# Pulse Width
@ 16MHz
@ 24MHz

115

73.4

(1+N)

OSC

-10

ns (3,4)

WLWHA

WR# Pulse Width
@ 16MHz
@ 24MHz

51.4

(1+N)

OSC

-32

ns (3,5)

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

LLRL

ALE Low to RD# or PSEN#
Low
@ 16MHz
@ 24MHz

10
10

ns (4)

LLRLA

ALE Low to RD# or PSEN#
Low
@ 16MHz
@ 24MHz

20
20

ns (5)

LHAX

ALE High to Address Hold
@ 16MHz
@ 24MHz

56.4

(1+M)

OSC

-27

ns (3,4)

LHAXA

ALE High to Address Hold
@ 16MHz
@ 24MHz

77.5
56.7

(0.5+M)

OSC

+15

ns (3,5)

RLDV

RD# or PSEN# Low to Valid
Data/Instruction In
@ 16MHz
@ 24MHz

53.4

(1+N)

OSC

-30

ns (3,4)

RLDVA

RD# or PSEN# Low to Valid
Data/Instruction In
@ 16MHz
@ 24MHz

33.4

(1+N)

OSC

-50

ns (3,5)

RHDX

Data/Instruction Hold after
RD# or PSEN# High
@ 16MHz
@ 24MHz

0
0

RLAZ

RD#/PSEN# Low to
Address Float
@ 16MHz
@ 24MHz

10
10

RHDZ1

Instruction Float after
PSEN# or RD# high
@ 16MHz
@ 24MHz

10
10

ns (4)

RHDZ1A

Instruction Float after
PSEN# or RD# high
@ 16MHz
@ 24MHz

57.5
36.7

OSC

-5

ns (5)

RHDZ2

Data Float after PSEN# or
RD# high
@ 16MHz
@ 24MHz

135

93.4

OSC

+10

ns (4)

RHDZ2A

Data Float after PSEN# or
RD# high
@ 16MHz
@ 24MHz

182.5
120.1

OSC

-5

ns (5)

Table 11. AC Characteristics (Sheet 2 of 4)

Symbol

Parameter

@ Max F

OSC

(1)

OSC

Variable

Units

Min

Max

Min

Max

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

RHLH2

RD# or PSEN# High to ALE
High (data)
@ 16MHz
@ 24MHz

135

93.4

OSC

+10

ns (4)

RHLH2A

RD# or PSEN# High to ALE
High (data)
@ 16MHz
@ 24MHz

180.5
118.1

OSC

-7

ns (5)

RHLH1

RD# or PSEN# High to ALE
High (Instruction)
@ 16MHz
@ 24MHz

10
10

ns (4)

RHLH1A

RD# or PSEN# High to ALE
High (Instruction)
@ 16MHz
@ 24MHz

55.5
34.7

OSC

-7

ns (5)

WHLH

WR# High to ALE Low
@ 16MHz
@ 24MHz

135

93.4

OSC

+10

ns (4)

WHLHA

WR# High to ALE Low
@ 16MHz
@ 24MHz

180.5
118.1

OSC

-7

ns (5)

AVDV1

Address (mux'd) valid to
Valid Data/ Instruction In
@ 16MHz
@ 24MHz

190

106.8

(2+M+N)

OSC

-60

ns (3,4)

AVDV1A

Address (mux'd) valid to
Valid Data/ Instruction In
@ 16MHz
@ 24MHz

159.5

97.1

(1.5+M+N)

OSC

-28

ns (3,4)

AVDV2

Address (demux'd) valid to
Valid Data/Instruction In
@ 16MHz
@ 24MHz

212

128.8

(2+M+N)

OSC

-38

ns (3)

AVDV3

Address (P0)Valid to Valid
Instruction In
@ 16MHz
@ 24MHz

23.4

(1+N)

OSC

-60

ns (3)

AVRL

Address Valid to RD# or
PSEN# Low
@ 16MHz
@ 24MHz

43.4

(1+M)

OSC

-40

ns (3,4)

AVRLA

Address Valid to RD# or
PSEN# Low
@ 16MHz
@ 24MHz

72.5
51.7

(0.5+M)

OSC

+10

ns (3,5)

Table 11. AC Characteristics (Sheet 3 of 4)

Symbol

Parameter

@ Max F

OSC

(1)

OSC

Variable

Units

Min

Max

Min

Max

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

AVWL1

Address (mux'd) Valid to
WR# Low
@ 16MHz
@ 24MHz

43.4

(1+M)

OSC

-40

ns (3,4)

AVWL1A

Address (mux'd) Valid to
WR# Low
@ 16MHz
@ 24MHz

72.5
51.7

(0.5+M)

OSC

+10

ns (3,5)

AVWL2

Address (demux'd) Valid to
WR# Low
@ 16MHz
@ 24MHz

108

66.4

(1+M)

OSC

-17

ns (3,4)

AVWL2A

Address (demux'd) Valid to
WR# Low
@ 16MHz
@ 24MHz

135

93.4

(1+M)

OSC

+10

ns (3,5)

WHQX

Data Hold after WR# High
@ 16MHz
@ 24MHz

49.5
28.7

OSC

-13

QVWH

Data Valid to WR# High
@ 16MHz
@ 24MHz

110

68.4

(1+N)

OSC

-15

ns (3)

WHAX

WR# High to Address Hold
@ 16MHz
@ 24MHz

112

70.4

OSC

-13

NOTES:

1. 24 MHz XTAL Frequency.

2. Specifications for PSEN# are identical to those for RD#.

3. In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for

RD#/PSEN#/WR#.

4. Device configured with the default data float timing for fast memory interface (EDF# = 1).

5. Device configured with extended data float timing for slow memory interface (EDF# = 0).

Table 11. AC Characteristics (Sheet 4 of 4)

Symbol

Parameter

@ Max F

OSC

(1)

OSC

Variable

Units

Min

Max

Min

Max

8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

ADVANCE INFORMATION

Figure 14. External Bus Cycle: Data Write (Page Mode)

Table 13. Real-Time Wait AC Timing

Symbol

Parameter

Min

Max

Units

CLYV

Wait Clock Low to Wait Set-up

OSC

CLYX

Wait Hold after Wait Clock Low

(2W)T

OSC

+ 5

(1+2W)T

OSC

ns (1)

RLYV

PSEN#/RD# Low to Wait Set-up

OSC

RLYVA

PSEN#/RD# Low to Wait Set-up

OSC

ns (2)

RLYX

Wait Hold after PSEN#/RD# Low

(2W)T

OSC

+ 5

(1+2W)T

OSC

ns (1)

WLYV

WR# Low to Wait Set-up

OSC

WLYVA

WR# Low to Wait Set-up

OSC

ns (2)

WLYX

Wait Hold after WR# Low

(2W)T

OSC

+ 5

(1+2W)T

OSC

ns (1)

NOTES:

1. W = 0, 1, 2 -- is the number of real time wait states.

2. Device configured with the extended data float timing.

A15:8

WCLK

ALE

WR#

WLYV

WAIT#

A5003-02

State 1

State 2

State 3

State 4

CLYX

min

CLYV

D7:0

stretched

A7:0

stretched

WR# stretched

WLYX

max

WLYX

min

CLYX

max

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 8XC251TA