Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

December 1995

INTEL CORPORATION 1995

Order Number 272659-002

8XC51RA RB RC

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Commercial Express

87C51RA 83C51RA 80C51RA 87C51RB 83C51RB 87C51RC 83C51RC

See Table 1 for Proliferation Options

High Performance CHMOS EPROM
ROM CPU

24 MHz Operation

512 Bytes of On-Chip Data RAM

Dedicated Hardware Watchdog Timer
(One-Time Enabled with Reset-Out)

Three 16-Bit Timer Counters

Programmable Clock Out

Up Down Timer Counter

Three Level Program Lock System

8K 16K 32K On-Chip Program Memory

Improved Quick Pulse Programming
Algorithm

Boolean Processor

32 Programmable I O Lines

6 Interrupt Sources

Programmable Serial Channel with

Framing Error Detection
Automatic Address Recognition

TTL and CMOS Compatible Logic
Levels

64K External Program Memory Space

64K External Data Memory Space

MCS

51 Compatible Instruction Set

Power Saving Idle and Power Down
Modes

ONCE (On-Circuit Emulation) Mode

Four-Level Interrupt Priority

Extended Temperature Range
(

40 C to

85 C)

MEMORY ORGANIZATION

ROMless

ROM

EPROM

ROM EPROM

RAM

Device

Version

Bytes

80C51RA

83C51RA

87C51RA

512

80C51RA

83C51RB

87C51RB

16K

512

80C51RA

83C51RC

87C51RC

32K

512

These devices can address up to 64 Kbytes of external program data memory

The Intel 8XC51RA 8XC51RB 8XC51RC is a single-chip control-oriented microcontroller which is fabricated
on Intel's reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the
8XC51RA 8XC51RB 8XC51RC uses the same powerful instruction set has the same architecture and is pin-
for-pin compatible with the existing MCS 51 family of products The 8XC51RA 8XC51RB 8XC51RC is an
enhanced version of the 8XC52 8XC54 8XC58 The added features make it an even more powerful microcon-
troller for applications that require 512 bytes of on-chip data RAM and dedicated hardware WatchDog Timer
with reset-out features

Throughout this document 8XC51RX will refer to the 8XC51RA 8XC51RB and 8XC51RC unless information
applies to a specific device

For a detailed description of 8XC51RA RB RC refer to the 8XC51RA RB RC Hardware Description order
number 272668

8XC51RA RB RC

PIN DESCRIPTIONS

Supply voltage

Circuit ground

SS1

Secondary ground (not on DIP) Provided to

reduce ground bounce and improve power supply
by-passing

NOTE

This pin is not a substitute for the V

pin (pin 22)

(Connection not necessary for proper operation )

Port 0

Port 0 is an 8-bit open drain bidirectional

I O port As an output port each pin can sink several
LS TTL inputs Port 0 pins that have 1's written to
them float and in that state can be used as high-im-
pedance inputs

Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory In this application it uses strong inter-
nal pullups when emitting 1's and can source and
sink several LS TTL inputs

Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullup resistors are re-
quired during program verification

Port 1

Port 1 is an 8-bit bidirectional I O port with

internal pullups The Port 1 output buffers can drive
LS TTL inputs Port 1 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally pulled low will source current
(I

on the data sheet) because of the internal pull-

ups

In addition Port 1 serves the functions of the follow-
ing special features of the 8XC51RX

Port Pin

Alternate Function

P1 0

T2 (External Count Input to Timer
Counter 2) Clock-Out

P1 1

T2EX (Timer Counter 2 Capture
Reload Trigger and Direction Control)

Port 1 receives the low-order address bytes during
EPROM programming and verifying

Port 2

Port 2 is an 8-bit bidirectional I O port with

internal pullups The Port 2 output buffers can drive

LS TTL inputs Port 2 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally pulled low will source current
(I

on the data sheet) because of the internal pull-

ups

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX

DPTR) In this application it

uses strong internal pullups when emitting 1's Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX

Ri) Port 2 emits the contents of

the P2 Special Function Register

Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion

Port 3

Port 3 is an 8-bit bidirectional I O port with

internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1's written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally pulled low will source current
(I

on the data sheet) because of the pullups

Port 3 also serves the functions of various special
features of the 8051 Family as listed below

Port Pin

Alternate Function

P3 0

RXD (serial input port)

P3 1

TXD (serial output port)

P3 2

INT0 (external interrupt 0)

P3 3

INT1 (external interrupt 1)

P3 4

T0 (Timer 0 external input)

P3 5

T1 (Timer 1 external input)

P3 6

WR (external data memory write strobe)

P3 7

RD (external data memory read strobe)

RST

Reset I O A high on this pin for two machine

cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a minimum V

IHI

voltage is applied whether

the oscillator is running or not An internal pulldown
resistor permits a power-on reset with only a capaci-
tor connected to V

After a WatchDog Timer over-

flow this RST pin will drive an output high pulse at a
minimum V

OH2

for 96 x T

OSC

duration while the in-

ternal reset signal is active

ALE

Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-

8XC51RA RB RC

ternal memory This pin (ALE PROG) is also the
program pulse input during EPROM programming for
the 87C51RX

In normal operation ALE is emitted at a constant
rate of

the oscillator frequency and may be used

for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory

If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode

Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin

PSEN

Program Store Enable is the read strobe to

external Program Memory

When the 8XC51RX is executing code from external
Program Memory PSEN is activated twice each
machine cycle except that two PSEN activations
are skipped during each access to external Data
Memory

EA V

External Access enable

EA must be

strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH Note however that if any of the
Lock bits are programmed EA will be internally
latched on reset

EA should be strapped to V

for internal program

executions

This pin also receives the programming supply volt-
age (V

) during EPROM programming

XTAL1

Input to the inverting oscillator amplifier

XTAL2

Output from the inverting oscillator amplifi-

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output respec-
tively of a inverting amplifier which can be config-

ured for use as an on-chip oscillator as shown in
Figure 3 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ``Oscillators for Microcontrol-
lers'' Order No 230659

272659 � 5

C1 C2

30 pF

10 pF for Crystals

For Ceramic Resonators contact resonator manufac-
turer

Figure 3 Oscillator Connections

To drive the device from an external clock source
XTAL1 should be driven while XTAL2 floats as
shown in Figure 4 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed

An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the V

and V

specifications the capacitance will not ex-

ceed 20 pF

272659 � 6

Figure 4 External Clock Drive Configuration

IDLE MODE

The user's software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions

Idle

8XC51RA RB RC

Table 2 Status of the External Pins during Idle and Power Down

Mode

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

Power Down

External

Float

Data

Mode will be exited if the chip is reset or if an en-
abled interrupt occurs

POWER DOWN MODE

To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated

On the 8XC51RX either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down
Reset redefines all the SFRs but does not change
the on-chip RAM An external interrupt allows both
the SFRs and on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before V

restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)

With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down

DEDICATED HARDWARE WATCHDOG
TIMER (One-Time Enabled with
Reset-Out)

The 8XC51RX contains a dedicated WatchDog Tim-
er (WDT) to allow recovery from software or hard-

ware upset WDT is disabled upon power-up To en-
able the WDT user must write 1EH and E1H in se-
quence to WDTRST Special Function Register
Once the WDT is enabled the 14-bit counter will
increment every machine cycle While the oscillator
is running the WDT will be incrementing and cannot
be disabled The counter is reset by writing 1EH and
E1H in sequence to the WDTRST If the counter is
not reset before it reaches 3FFFH (16383D) the
chip will be forced into reset sequence and the WDT
will be disabled as upon power-up During this reset
the chip will drive an output Reset-High pulse for the
duration of 96 x T

OSC

at the RST pin The duration

of the Reset-High pulse works out to 6 00 ms
16 MHz

While in the Idle mode the WDT continues to count
If the user does not wish to exit the Idle mode with a
reset then the processor must periodically ``woken
up'' to service the WDT In Power Down mode the
WDT stops counting and holds its current value

DESIGN CONSIDERATION

The window on the D87C51RX must be covered
by an opaque label Otherwise the DC and AC
characteristics may not be met and the device
may be functionally impaired

When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory

NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No
270648) ``Designing with the 80C51BH ''

8XC51RA RB RC

ONCE MODE

The ONCE (``On-Circuit Emulation'') Mode facilitates
testing

and

debugging

systems

using

the

8XC51RX without the 8XC51RX having to be re-
moved from the circuit The ONCE Mode is invoked
by

1) Pull ALE low while the device is in reset and

PSEN is high

2) Hold ALE low as RST is deactivated

While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC51RX is in this mode an emulator
or test CPU can be used to drive the circuit Normal
operation is restored when a normal reset is applied

8XC51RX EXPRESS

The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers These EXPRESS products are
designed to meet the needs of those applications

whose operating requirements exceed commercial
standards

The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in

With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to a70 C With the ex-
tended temperature range option operational char-
acteristics are guaranteed over the range of b40 C
to a85 C

The optional burn-in is dynamic for a minimum time
of 168 hours at 125 C with V

6 9V

0 25V

following guidelines in MIL-STD-883 Method 1015

Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number The
prefixes are listed in Table 3

For the extended temperature range option this
data sheet specifies the parameters which deviate
from their commercial temperature range limits

Table 3 Prefix Identification

Prefix

Package

Temperature

Burn-In

Type

Range

Plastic

Commercial

PLCC

Commercial

QFP

Commercial

Plastic

Extended

PLCC

Extended

QFP

Extended

Plastic

Extended

Yes

PLCC

Extended

Yes

QFP

Extended

Yes

NOTE
Contact distributor or local sales office to match EXPRESS prefix with proper device

EXAMPLES
P80C51RA indicates 80C51RA in a plastic package and specified for commercial temperature range without burn-in
TS87C51RC indicates 87C51RC in a QFP package and specified for extended temperature range without burn-in

8XC51RA RB RC

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias b40 C to a85 C

Storage Temperature

65 C to a150 C

Voltage on EA V

Pin to V

0V to a13 0V

Voltage on Any Other Pin to V

0 5V to a6 5V

Per I O Pin

15 mA

Power Dissipation

1 5W

(based on PACKAGE heat transfer limitations not
device power consumption)

NOTICE This data sheet contains information on
products in the sampling and initial production phases
of development The specifications are subject to
change without notice Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Commercial

Express

Supply Voltage
All Others

4 0

6 0

8XC51RX-24

4 5

5 5

OSC

0scillator Frequency

8XC51RX

3 5

MHz

8XC51RX-1

3 5

MHz

8XC51RX-20

3 5

MHz

8XC51RX-24

3 5

MHz

DC CHARACTERISTICS

(Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

(Note 4)

Input Low Voltage

0 5

0 2 V

0 1

IL1

Input Low Voltage EA

0 2 V

0 3

Input High Voltage

0 2 V

0 9

0 5

(Except XTAL1 RST)

IH1

Input High Voltage

0 7 V

0 5

(XTAL1 RST)

Output Low Voltage (Note 5)

0 3

100 mA (Note 1)

(Ports 1 2 and 3)

0 45

1 6 mA (Note 1)

1 0

3 5 mA (Note 1)

OL1

Output Low Voltage (Note 5)

0 3

200 mA (Note 1)

(Port 0 ALE PSEN)

0 45

3 2 mA (Note 1)

1 0

7 0 mA (Note 1)

Output High Voltage

0 3

e b

10 mA

(Ports 1 2 and 3 ALE PSEN)

0 7

e b

30 mA

1 5

e b

60 mA

8XC51RA RB RC

DC CHARACTERISTICS

(Over Operating Conditions) (Continued)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

(Note 4)

OH1

Output High Voltage

0 3

e b

200 mA

(Port 0 in External Bus Mode)

0 7

e b

3 2 mA

1 5

e b

7 0 mA

OH2

Output High Voltage

0 5 V

e b

800 mA

(RST)

0 75 V

e b

300 mA

0 9 V

e b

80 mA

Logical 0 Input Current
(Ports 1 2 and 3)

0 45V

Input leakage Current (Port 0)

or V

Logical 1 to 0 Transition Current
(Ports 1 2 and 3)

Commercial

675

Express

775

RRST

RST Pulldown Resistor

225

CIO

Pin Capacitance

1 MHz 25 C

Power Supply Current

(Note 3)

Active Mode

at 12 MHz (Figure 5)

at 16 MHz

at 20 MHz

at 24 MHz

Idle Mode

at 12 MHz (Figure 5)

7 5

at 16 MHz

9 5

at 20 MHz

11 5

at 24 MHz

13 5

Power Down Mode

NOTES
1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V

s of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed
0 8V It may be desirable to qualify ALE or other signals with a Schmitt Triggers or CMOS-level input logic
2 Capacitive loading on Ports 0 and 2 cause the V

on ALE and PSEN to drop below the 0 9 V

specification when the

address lines are stabilizing
3 See Figures 6 � 9 for test conditions Minimum V

for Power Down is 2V

4 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature
and 5V
5 Under steady state (non-transient) conditions I

must be externally limited as follows

Maximum I

per port pin

10mA

Maximum I

per 8-bit port

Port 0

26 mA

Ports 1 2 and 3

15 mA

Maximum total I

for all output pins

71 mA

If I

exceeds the test condition V

may exceed the related specification Pins are not guaranteed to sink current greater

than the listed test conditions

8XC51RA RB RC

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters The first char-
acter is always a `T' (stands for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for

A Address

C Clock

D Input Data

H Logic level HIGH

I Instruction (program memory contents)

L Logic level LOW or ALE

P PSEN

Q Output Data

R RD signal

T Time

V Valid

W WR signal

X No longer a valid logic level

Z Float

For example

TAVLL e Time from Address Valid to ALE Low

TLLPL e Time from ALE Low to PSEN Low

AC CHARACTERISTICS

(Over Operating Conditions Load Capacitance for Port 0 ALE PROG and

PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated In this table 8XC51RX refers to
8XC51RX and 8XC51RX-1 8XC51RX-24 refers to 8XC51RX-20 and 8XC51RX-24

Symbol

Description

12 MHz

20 MHz

24 MHz

Variable

Units

Oscillator

Min

Max

Min

Max

Min

Max

Min

Max

1 TCLCL

Oscillator Frequency

8XC51RX

3 5

MHz

8XC51RX-1

3 5

MHz

8XC51RX-20

3 5

MHz

8XC51RX-24

3 5

MHz

TLHLL

ALE Pulse Width

127

2 TCLCL

TAVLL

Address Valid to

TCLCL

ALE Low

TLLAX

Address Hold After

TCLCL

ALE Low

TLLIV

ALE Low to Valid
Instruction In

8XC51RX

234

4 TCLCL

100

8XC51RX-24

125

4 TCLCL

TLLPL

ALE Low to PSEN

TCLCL

Low

TPLPH

PSEN Pulse Width

205

105

3 TCLCL

TPLIV

PSEN Low to Valid
Instruction In

8XC51RX

145

3 TCLCL

105

8XC51RX-24

3 TCLCL

TPXIX

Input Instruction

Hold After PSEN

8XC51RA RB RC

EXTERNAL MEMORY CHARACTERISTICS

(Continued)

All parameter values apply to all devices unless otherwise indicated

Symbol

Description

12 MHz

20 MHz

24 MHz

Variable

Units

Oscillator

Min

Max

Min

Max

Min

Max

Min

Max

TPXIZ

Input Instruction Float After
PSEN

8XC51RX

TCLCL

8XC51RX-24

TCLCL

TAVIV

Address to Valid Instruction

312

145

103

5 TCLCL

105

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

400

200

150

6 TCLCL

100

TWLWH

WR Pulse Width

400

200

150

6 TCLCL

100

TRLDV

RD Low to Valid Data In

8XC51RX

252

5 TCLCL

165

8XC51RX-24

155

113

5 TCLCL

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

107

2 TCLCL

TLLDV

ALE Low to Valid Data In

8XC51RX

517

8 TCLCL

150

8XC51RX-24

310

243

8 TCLCL

TAVDV

Address to Valid Data In

8XC51RX

585

9 TCLCL

165

8XC51RX-24

360

285

9 TCLCL

TLLWL

ALE Low to RD or WR Low

200

300

100

200

175

3 TCLCL

TAVWL

Address Valid to WR Low

8XC51RX

203

4 TCLCL

130

8XC51RX-24

110

4 TCLCL

TQVWX

Data Valid before WR

8XC51RX

TCLCL

8XC51RX-20

TCLCL

8XC51RX-24

TCLCL

TWHQX

Data Hold after WR

8XC51RX

TCLCL

8XC51RX-20

TCLCL

8XC51RX-24

TCLCL

TQVWH

Data Valid to WR High

8XC51RX

433

7 TCLCL

150

8XC51RX-24

280

222

7 TCLCL

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

8XC51RX

123

TCLCL

8XC51RX-24

TCLCL

8XC51RA RB RC

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Units

1 TCLCL

Oscillator Frequency
8XC51RX

3 5

MHz

8XC51RX-1

3 5

8XC51RX-20

3 5

8XC51RX-24

3 5

TCHCX

High Time

0 35 T

OSC

0 65 T

OSC

TCLCX

Low Time

0 35 T

OSC

0 65 T

OSC

TCLCH

Rise Time

8XC51RX

8XC51RX-24

TCHCL

Fall Time20

8XC51RX

8XC51RX-24

EXTERNAL CLOCK DRIVE WAVEFORM

272659 � 16

AC TESTING INPUT OUTPUT WAVEFORMS

272659 � 17

AC Inputs during testing are driven at V

0 5V for a Logic ``1''

and 0 45V for a Logic ``0'' Timing measurements are made at V

min for a Logic ``1'' and V

max for a Logic ``0''

FLOAT WAVEFORMS

272659 � 18

For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loaded V

level occurs

20 mA

8XC51RA RB RC

PROGRAMMING THE EPROM

The part must be running with a 4 MHz to 6 MHz
oscillator The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines Control and program signals must
be held at the levels indicated in Table 4 Normally
EA V

is held at logic high until just before ALE

PROG is to be pulsed The EA V

is raised to V

ALE PROG is pulsed low and then EA V

is re-

turned to a high (also refer to timing diagrams)

NOTES

Exceeding the V

maximum for any amount of

time could damage the device permanently The
V

source must be well regulated and free of

glitches

DEFINITION OF TERMS

ADDRESS LINES

P1 0 � P1 7 P2 0 � P2 5 respec-

tively for A0 � A13

DATA LINES

P0 0 � P0 7 for D0 � D7

CONTROL SIGNALS

RST PSEN P2 6 P2 7 P3 3

P3 6 P3 7

PROGRAM SIGNALS

ALE PROG EA V

Table 4 EPROM Programming Modes

Mode

RST

PSEN

ALE

P2 6

P2 7

P3 3

P3 6

P3 7

PROG

Program Code Data

12 75V

Verify Code Data

Program Encryption

12 75V

Array Address 0 � 3FH

Program Lock

Bit 1

12 75V

Bits

Bit 2

12 75V

Bit 3

12 75V

Read Signature Byte

8XC51RA RB RC

272659 � 19

See Table 4 for proper input on these pins

Figure 10 Programming the EPROM

PROGRAMMING ALGORITHM

Refer to Table 4 and Figures 10 and 11 for address
data and control signals set up To program the
87C51RX the following sequence must be exer-
cised

1 Input the valid address on the address lines

2 Input the appropriate data byte on the data

lines

3 Activate the correct combination of control sig-

nals

4 Raise EA V

from V

to 12 75V

0 25V

5 Pulse ALE PROG 5 times for the EPROM ar-

ray and 25 times for the encryption table and
the lock bits

Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached

PROGRAM VERIFY

Program verify may be done after each byte or block
of bytes is programmed In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C51RX

The lock bits cannot be directly verified Verification
of the lock bits is done by observing that their fea-
tures are enabled

272659 � 20

Figure 11 Programming Signal's Waveforms

8XC51RA RB RC

ROM and EPROM Lock System

The program lock system when programmed pro-
tects the onboard program against software piracy

The 83C51RX has a one-level program lock system
and a 64-byte encryption table See line 2 of Table
5 If program protection is desired the user submits
the encryption table with their code and both the
lock-bit and encryption array are programmed by the
factory The encryption array is not available without
the lock bit For the lock bit to be programmed the
user must submit an encryption table

The 87C51RX has a 3-level program lock system
and a 64-byte encryption array Since this is an
EPROM device all locations are user-programma-
ble See Table 5

Encryption Array

Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's) Every
time that a byte is addressed during a verify 6 ad-
dress lines are used to select a byte of the Encryp-
tion Array

This byte is then exclusive-NOR'ed

(XNOR) with the code byte creating an Encryption
Verify byte The algorithm with the array in the un-
programmed state (all 1's) will return the code in its
original unmodified form For programming the En-
cryption Array refer to Table 4 (Programming the
EPROM)

When using the encryption array one important fac-
tor needs to be considered If a code byte has the
value 0FFH verifying the byte will produce the en-
cryption byte value If a large block (

64 bytes) of

code is left unprogrammed a verification routine will
display the contents of the encryption array For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH and not
all of them the same value This will ensure maxi-
mum program protection

Program Lock Bits

The 87C51RX has 3 programmable lock bits that
when programmed according to Table 5 will provide
different levels of protection for the on-chip code
and data

If any program lock bits were programmed erasing
the EPROM will not erase the program lock bits and
programming of the EPROM is disabled

Reading the Signature Bytes

The 8XC51RX has 3 signature bytes in locations
30H 31H and 60H To read these bytes follow the
procedure for EPROM verify but activate the control
lines provided in Table 4 for Read Signature Byte

Location

Device

Contents

30H

All

89H

31H

All

58H

60H

87C51RC

C2H

87C51RB

C1H

87C51RA

C0H

83C51RC

42H C2H

83C51RB

41H C1H

83C51RA

40H C0H

Erasure Characteristics
(Windowed Packages Only)

Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4 000 Angstroms Since sunlight and
fluorescent lighting have wavelengths in this range
exposure to these light sources over an extended
time (about 1 week in sunlight or 3 years in room-
level fluorescent lighting) could cause inadvertent
erasure If an application subjects the device to this
type of exposure it is suggested that an opaque la-
bel be placed over the window

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-sec cm

Exposing the

EPROM to an ultraviolet lamp of 12 000 mW cm

rating for 30 minutes at a distance of about 1 inch
should be sufficient

Erasure leaves all the EPROM Cells in a 1's state

8XC51RA RB RC

Table 5 Program Lock Bits and the Features

Program Lock Bits

Protection Type

LB1

LB2

LB3

No Program Lock features enabled (Code verify will still be encrypted by the
Encryption Array if programmed )

MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory EA is sampled and latched on
Reset and further programming of the EPROM is disabled

Same as 2 also verify is disabled

Same as 3 also external execution is disabled

NOTE
Any other combination of the lock bits is not defined

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

21 C to 27 C V

20% V

0V)

Symbol

Parameter

Min

Max

Units

Programming Supply Voltage

12 5

13 0

Programming Supply Current

1 TCLCL

Oscillator Frequency

MHz

TAVGL

Address Setup to PROG Low

48TCLCL

TGHAX

Address Hold after PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold after PROG

48TCLCL

TEHSH

(Enable) High to V

48TCLCL

TSHGL

Setup to PROG Low

TGHSL

Hold after PROG

TGLGH

PROG Width

110

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float after ENABLE

48TCLCL

TGHGL

PROG High to PROG Low

8XC51RA RB RC

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

272659 � 21

5 pulses for the EPROM array 25 pulses for the encryption table and lock bits

Thermal Impedance

All thermal impedance data is approximate for static
air conditions at 1W of power dissipation Values will
change depending on operating conditions and ap-
plications See the Intel Packaging Handbook (Order
Number 240800) for a description of Intel's thermal
impedance test methodology

Package

Device

45 C W

16 C W

All

46 C W

16 C W

All

87 C W

18 C W

51RA

96 C W

24 C W

51RB

90 C W

22 C W

51RC

DATA SHEET REVISION HISTORY

Data sheets are changed as new device information
becomes available Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices

The following differences exist between this data-
sheet (272659-002) and the previous version
(272659-001)

1 ADVANCE INFORMATION datasheet replaces

PRODUCT PREVIEW datasheet

2 I

(Commercial) changed from b650 mA to

675 mA

3 I

(Express) changed from

750

A to

775 mA

4 8XC51RX-24 V

changed from 5V

20% to

10%

5 Remove all CERDIP package types (prefix D TD

LD)

INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080

INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000

INTEL JAPAN k k Ibaraki-ken Tel 029747-8511

Электронный компонент: 8XC51RC