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Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

INTEL CORPORATION 1995

Order Number 290500-003

A28F200BX-T B

2-MBIT (128K x 16 256K x 8) BOOT BLOCK

FLASH MEMORY FAMILY

Automotive

x8 x16 Input Output Architecture

A28F200BX-T A28F200BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs

Optimized High Density Blocked
Architecture

One 16 KB Protected Boot Block
Two 8 KB Parameter Blocks
One 96 KB Main Block
One 128 KB Main Block
Top or Bottom Boot Locations

Extended Cycling Capability

1 000 Block Erase Cycles

Automated Word Byte Write and
Block Erase

Command User Interface
Status Register
Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature

1 mA Typical I

Active Current in

Static Operation

Hardware Data Protection Feature

Erase Write Lockout during Power
Transitions

Very High-Performance Read

90 ns Maximum Access Time
45 ns Maximum Output Enable Time

Low Power Consumption

25 mA Typical Active Read Current

Deep Power-Down Reset Input

Acts as Reset for Boot Operations

Automotive Temperature Operation

40 C to

125 C

Write Protection for Boot Block

Industry Standard Surface Mount
Packaging

JEDEC ROM Compatible
44-Lead PSOP

12V Word Byte Write and Block Erase

12V

5% Standard

ETOX

III Flash Technology

5V Read

Independent Software Vendor Support

A28F200BX-T B

Intel's 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-
tive erasure automated write and erase operations and standard microprocessor interface The 2 Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input out-
put control very high speed low power an industry standard ROM compatible pinout The 2-Mbit flash family
allows for an easy upgrade to Intel's 4-Mbit Boot Block Flash Memory Family

The Intel A28F200BX-T B are 16-bit wide flash memory offerings optimized to meet the rigorous environmen-
tal requirements of Automotive Applications These high density flash memories provide user selectable bus
operation for either 8-bit or 16-bit applications The A28F200BX-T and A28F200BX-B are 2 097 152-bit non-
volatile memories organized as either 262 144 bytes or 131 072 words of information They are offered in 44-
Lead plastic SOP packages The x8 x16 pinout conforms to the industry standard ROM EPROM pinout Read
and Write Characteristics are guaranteed over the ambient temperature range of b40 C to a125 C

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word byte write and block erasure The A28F200BX-T provides block locations compatible with Intel's
MCS-186 family 80286 i386

i486

i860

and 80960CA microprocessors The A28F200BX-B provides

compatibility with Intel's 80960KX and 80960SX families as well as other embedded microprocessors

The boot block includes a data protection feature to protect the boot code in critical applications With a
maximum access time of 90 ns these 2 Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers

Manufactured on Intel's 0 8 micron ETOX

III process the 2-Mbit flash memory family provides world class

quality reliability and cost-effectiveness at the 2-Mbit density level

A28F200BX-T B

1 0

PRODUCT FAMILY OVERVIEW

Throughout this datasheet the A28F200BX refers to
both the A28F200BX-T and A28F200BX-B devices
Section 1 provides an overview of the 2-Mbit flash
memory family including applications pinouts and
pin descriptions Section 2 describes in detail the
specific memory organization Section 3 provides a
description of the family's principles of operation Fi-
nally the family's operating specifications are de-
scribed

1 1

Main Features

The A28F200BX boot block flash memory family is a
very high performance 2-Mbit (2 097 152 bit) memo-
ry family organized as either 128-KWords (131 072
words) of 16 bits each or 256-Kbytes (262 144
bytes) of 8 bits each

Five Separately Erasable Blocks

including a hard-

ware-lockable boot block

(16 384 Bytes) two pa-

rameter blocks

(8 192 Bytes each) and two main

blocks

(1 block of 98 304 Bytes and 1 block of

131 072 Bytes) are included on the 2-Mbit family An
erase operation erases one of the main blocks in
typically 3 seconds and the boot or parameter
blocks in typically 1 5 seconds Each block can be
independently erased and programmed 1 000 times

The Boot Block

is located at either the top

(A28F200BX-T) or the bottom (A28F200BX-B) of the
address map in order to accommodate different mi-
croprocessor protocols for boot code location The
hardware lockable boot block

provides the most

secure code storage The boot block is intended to
store the kernel code required for booting-up a sys-
tem When the RP

pin is between 11 4V and 12 6V

the boot block is unlocked and program and erase
operations can be performed When the RP

pin is

at or below 6 5V the boot block is locked and pro-
gram and erase operations to the boot block are
ignored

The A28F200BX products are available in the ROM
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package as
shown in Figure 3

The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the A28F200BX
flash memory

Program and Erase Automation

allows program

and erase operations to be executed using a two-
write command sequence to the CUI The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations including verifications there-
by unburdening the microprocessor or microcontrol-
ler Writing of memory data is performed in word or
byte increments for the A28F200BX family typically
within 9 ms which is a 100% improvement over pre-
vious flash memory products

The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation

Maximum Access Time of 90 ns (TACC) is achieved
over the automotive temperature range (b40 C to
125 C) 10% V

supply voltage range and 100 pF

output load

maximum Program current is 40 mA for x16

operation and 30 mA for x8 operation I

Erase

current is 30 mA maximum V

erase and pro-

gramming voltage is 11 4V to 12 6V (V

12V

5%) under all operating conditions Typical I

Active Current of 25 mA

is achieved

The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs Once the device is ac-
cessed to read array data APS mode will immedi-
ately put the memory in static mode of operation
where I

active current is typically 1 mA until the

next read is initiated

When the CE

and RP

pins are at V

and the

BYTE

pin is at either V

or GND the CMOS

Standby

mode is enabled where I

is typically

80 mA

A Deep Power-Down Mode is enabled when the
RP

pin is at ground minimizing power consumption

and providing write protection during power-up con-
ditions I

current

during deep power-down mode

is 50 mA typical An initial maximum access time or
Reset Time of 300 ns is required from RP

switch-

ing until outputs are valid Equivalently the device
has a maximum wake-up time of 210 ns until writes
to the Command User Interface are recognized

A28F200BX-T B

When RP

is at ground the WSM is reset the

Status Register is cleared and the entire device is
protected from being written to This feature pre-
vents data corruption and protects the code stored
in the device during system reset The system Reset
pin can be tied to RP

to reset the memory to nor-

mal read mode upon activation of the Reset pin
With on-chip program erase automation in the
2 Mbit family and the RP

functionality for data pro-

tection when the CPU is reset and even if a program
or erase command is issued the device will not rec-
ognize any operation until RP

returns to its normal

state

For the A28F200BX Byte-wide or Word-wide In-
put Output Control

is possible by controlling the

BYTE

pin When the BYTE

pin is at a logic low

the device is in the byte-wide mode (x8) and data is
read and written through DQ 0 7

During the byte-

wide mode DQ 8 14 are tri-stated and DQ15 Ab1
becomes the lowest order address pin When the
BYTE

pin is at a logic high the device is in the

word-wide mode (x16) and data is read and written
through DQ 0 15

1 2 Applications

The 2-Mbit boot block flash family combines high
density high performance cost-effective flash mem-
ories with blocking and hardware protection capabili-
ties Its flexibility and versatility will reduce costs
throughout the product life cycle Flash memory is
ideal for Just-In-Time production flow reducing sys-
tem inventory and costs and eliminating component
handling during the production phase During the
product life cycle when code updates or feature en-
hancements become necessary flash memory will
reduce the update costs by allowing either a user-
performed code change via floppy disk or a remote
code change via a serial link The 2-Mbit boot block
flash family provides full function blocked flash
memories suitable for a wide range of automotive
applications

A28F200BX-T B

1 4 Pin Descriptions for the x8 x16 A28F200BX

Symbol

Type

Name and Function

� A

ADDRESS INPUTS

for memory addresses Addresses are internally latched

during a write cycle

ADDRESS INPUT

When A

is at 12V the signature mode is accessed During this

mode A

decodes between the manufacturer and device ID's When BYTE

is at

a logic low only the lower byte of the signatures are read DQ

is a don't

care in the signature mode when BYTE

is low

� DQ

I O

DATA INPUTS OUTPUTS

Inputs array data on the second CE

and WE

cycle

during a program command Inputs commands to the Command User Interface
when CE

and WE

are active Data is internally latched during the write and

program cycles Outputs array intelligent identifier and Status Register data The
data pins float to tri-state when the chip is deselected or the outputs are disabled

� DQ

I O

DATA INPUTS OUTPUTS

Inputs array data on the second CE

and WE

cycle

during a program command Data is internally latched during the write and program
cycles Outputs array data The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE

``0'')

In the byte-wide mode DQ

becomes the lowest order address for data

output on DQ

� DQ

CHIP ENABLE

Activates the device's control logic input buffers decoders and

sense amplifiers CE

is active low CE

high deselects the memory device and

reduces power consumption to standby levels If CE

and RP

are high but not

at a CMOS high level the standby current will increase due to current flow through
the CE

and RP

input stages

RESET POWER-DOWN

Provides three-state control Puts the device in deep

power-down mode Locks the boot block from program erase

When RP

is at logic high level and equals 6 5V maximum the boot block is

locked and cannot be programmed or erased

When RP

11 4V minimum the boot block is unlocked and can be programmed

or erased

When RP

is at a logic low level the boot block is locked the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased therefore providing data protection during power
transitions When RP

transitions from logic low to logic high the flash memory

enters the read array mode

OUTPUT ENABLE

Gates the device's outputs through the data buffers during a

read cycle OE

is active low

WRITE ENABLE

Controls writes to the Command Register and array blocks

is active low Addresses and data are latched on the rising edge of the WE

pulse

BYTE

ENABLE

Controls whether the device operates in the byte-wide mode

(x8) or the word-wide mode (x16) BYTE

pin must be controlled at CMOS levels

to meet 130 mA CMOS current in the standby mode BYTE

``0'' enables the

byte-wide mode where data is read and programmed on DQ

� DQ

and

becomes the lowest order address that decodes between the upper

and lower byte DQ

� DQ

are tri-stated during the byte-wide mode

BYTE

``1'' enables the word-wide mode where data is read and programmed

on DQ

� DQ

PROGRAM ERASE POWER SUPPLY

For erasing memory array blocks or

programming data in each block
Note

PPLMAX

memory contents cannot be altered

DEVICE POWER SUPPLY (5V

10%)

GND

GROUND

For all internal circuitry

NO CONNECT

Pin may be driven or left floating

DON'T USE PIN

Pin should not be connected to anything

A28F200BX-T B

2 1 A28F200BX Memory Organization

2 1 1 BLOCKING

The A28F200BX uses a blocked array architecture
to provide independent erasure of memory blocks A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI The A28F200BX
is a random read write memory only erasure is per-
formed by block

2 1 1 1 Boot Block Operation and Data

Protection

The 16-Kbyte boot block provides a lock feature for
secure code storage The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP

is not at 12V The boot block can

be erased and written when RP

is held at 12V for

the duration of the erase or program operation This
allows customers to change the boot code when
necessary while providing security when needed
See the Block Memory Map section for address lo-
cations of the boot block for the A28F200BX-T and
A28F200BX-B

2 1 1 2 Parameter Block Operation

The A28F200BX has 2 parameter blocks (8-Kbytes
each) The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information The pa-
rameter blocks can also be used to store additional
boot or main code The parameter blocks however
do not have the hardware write protection feature
that the boot block has The parameter blocks pro-
vide for more efficient memory utilization when deal-
ing with parameter changes versus regularly blocked
devices See the Block Memory Map section for ad-
dress locations of the parameter blocks for the
A28F200BX-T and A28F200BX-B

2 1 1 3 Main Block Operation

Two

main

blocks

memory

exist

the

A28F200BX (1 x 128-Kbyte block and 1 x 96-Kbyte
block) See the following section on Block Memory
Map for the address location of these blocks for the
A28F200BX-T

and A28F200BX-B products

2 1 2 BLOCK MEMORY MAP

Two versions of the A28F200BX product exist to
support two different memory maps of the array
blocks in order to accommodate different microproc-
essor

protocols

for

boot

code

location

The

A28F200BX-T memory map is inverted from the
A28F200BX-B memory map

2 1 2 1 A28F200BX-B Memory Map

The A28F200BX-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H

In the

A28F200BX-B the first 8-Kbyte parameter block re-
sides in memory space from 02000H to 02FFFH
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH

The

96-Kbyte main block resides in memory space from
04000H to 0FFFFH The 128-Kbyte main block re-
sides in memory space from 10000H to 1FFFFH
(word locations) See Figure 4

(Word Addresses)

1FFFFH

128-Kbyte MAIN BLOCK

0FFFFH

10000H

96-Kbyte MAIN BLOCK

03FFFH

04000H

8-Kbyte PARAMETER BLOCK

02FFFH

03000H

8-Kbyte PARAMETER BLOCK

01FFFH

02000H

16-Kbyte BOOT BLOCK

00000H

Figure 4 A28F200BX-B Memory Map

A28F200BX-T B

2 1 2 2 A28F200BX-T Memory Map

The A28F200BX-T device has the 16-Kbyte boot
block located from 1E000H to 1FFFFH to accommo-
date those microprocessors that boot from the top
of the address map In the A28F200BX-T the first
8 Kbyte parameter block resides in memory space
from 1D000H to 1DFFFH The second 8-Kbyte pa-
rameter block resides in memory space from
1C000H to 1CFFFH The 96-Kbyte main block re-
sides in memory space from 10000H to 1BFFFH
The 128-Kbyte main block resides in memory space
from 00000H to 0FFFFH as shown in Figure 5

(Word Addresses)

1FFFFH

16-Kbyte BOOT BLOCK

1DFFFH

1E000H

8-Kbyte PARAMETER BLOCK

1CFFFH

1D000H

8-Kbyte PARAMETER BLOCK

1BFFFH

1C000H

96-Kbyte MAIN BLOCK

0FFFFH

10000H

128-Kbyte MAIN BLOCK

00000H

Figure 5 A28F200BX-T Memory Map

3 0

PRODUCT FAMILY PRINCIPLES
OF OPERATION

Flash memory augments EPROM functionality with
in-circuit electrical write and erase The 2-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations

The CUI allows for 100% TTL-level control inputs
fixed power supplies during erasure and program-
ming and maximum EPROM compatibility

In the absence of high voltage on the V

pin the

2-Mbit boot block flash family will only successfully
execute the following commands Read Array Read
Status Register Clear Status Register and Intelli-
gent Identifier mode The device provides standard
EPROM read standby and output disable opera-
tions Manufacturer Identification and Device Identi-
fication data can be accessed through the CUI or
through the standard EPROM A9 high voltage ac-
cess (V

) for PROM programming equipment

The same EPROM read standby and output disable
functions are available when high voltage is applied
to the V

pin In addition high voltage on V

al-

lows write and erase of the device All functions as-
sociated with altering memory contents write and
erase Intelligent Identifier read and Read Status are
accessed via the CUI

The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register The CUI will handle the
WE

interface to the data and address latches as

well as system software requests for status while the
WSM is in operation

3 1 Bus Operations

Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles

A28F200BX-T B

Table 1 Bus Operations for WORD-WIDE Mode (BYTE

)

Mode

Notes

0�15

Read

1 2 3

OUT

Output Disable

High Z

Standby

High Z

Deep Power-Down

High Z

Intelligent Identifier (Mfr)

0089H

Intelligent Identifier (Device)

4 5

2274H
2275H

Write

6 7 8

Table 2 Bus Operations for BYTE-WIDE Mode (BYTE

)

Mode

Notes

0�7

8�14

Read

1 2 3

OUT

High Z

Output Disable

High Z

Standby

High Z

Deep Power-Down

High Z

Intelligent Identifier (Mfr)

89H

High Z

Intelligent Identifier

4 5

74H

High Z

(Device)

75H

Write

6 7 8

High Z

NOTES
1 Refer to DC Characteristics
2 X can be V

or V

for control pins and addresses V

PPL

or V

PPH

for V

3 See DC characteristics for V

PPL

PPH

voltages

4 Manufacturer and Device codes may also be accessed via a CUI write sequence A

� A

5 Device ID

2274H for A28F200BX-T and 2275H for A28F200BX-B

6 Refer to Table 3 for valid D

during a write operation

7 Command writes for Block Erase or Word Byte Write are only executed when V

PPH

8 To write or erase the boot block hold RP

at V

9 RP

must be at GND

0 2V to meet the 80 mA maximum deep power-down current

3 2 Read Operations

The 2-Mbit boot block flash family has three user
read modes Array Intelligent Identifier and Status
Register Status Register read mode will be dis-
cussed in detail in the ``Write Operations'' section

During power-up conditions (V

supply ramping) it

takes a maximum of 300 ns from when V

is at

4 5V minimum to valid data on the outputs

3 2 1 READ ARRAY

If the memory is not in the Read Array mode it is
necessary to write the appropriate read mode com-
mand to the CUI The 2-Mbit boot block flash family
has three control functions all of which must be logi-
cally active to obtain data at the outputs Chip-En-
able CE

is the device selection control Reset

Power-Down RP

is the device power control Out-

put-Enable OE

is the DATA INPUT OUTPUT

(DQ 0 15 or DQ 0 7 ) direction control and when
active is used to drive data from the selected memo-
ry on to the I O bus

A28F200BX-T B

3 2 1 1 Output Control

With OE

at logic-high level (V

) the output from

the device is disabled and data input output pins
(DQ 0 15 or DQ 0 7 ) are tri-stated Data input is
then controlled by WE

3 2 1 2 Input Control

With WE

at logic-high level (V

) input to the de-

vice is disabled Data Input Output pins (DQ- 0 15
or DQ 0 7 ) are controlled by OE

3 2 2 INTELLIGENT IDENTlFlERS

The manufacturer and device codes are read via the
CUI or by taking the A

pin to 12V Writing 90

the CUI places the device into Intelligent Identifier
read mode A read of location 00000

outputs the

manufacturer's identification code 0089H and loca-
tion 00001

outputs the device code 2274H for

A28F200BX-T

2275H for A28F200BX-B

When

BYTE

is at a logic low only the lower byte of the

above signatures is read and DQ

is a ``don't

care'' during Intelligent Identifier mode A read array
command must be written to the CUI to return to the
read array mode

3 3 Write Operations

Commands are written to the CUI using standard mi-
croprocessor write timings The CUl serves as the
interface between the microprocessor and the inter-
nal chip operation The CUI can decipher Read Ar-
ray Read Intelligent Identifier Read Status Register
Clear Status Register Erase and Program com-
mands In the event of a read command the CUI
simply points the read path at either the array the
Intelligent Identifier or the status register depending
on the specific read command given For a program
or erase cycle the CUI informs the write state ma-
chine that a write or erase has been requested Dur-
ing a program cycle the Write State Machine will
control the program sequences and the CUI will only
respond to status reads During an erase cycle the
CUI will respond to status reads and erase suspend
After the Write State Machine has completed its
task it will allow the CUI to respond to its full com-
mand set The CUI will stay in the current command
state until the microprocessor issues another com-
mand

The CUI will successfully initiate an erase or write
operation only when V

is within its voltage range

Depending upon the application the system design-
er may choose to make the V

power supply

switchable available only when memory updates
are desired The system designer can also choose
to ``hard-wire'' V

to 12V The 2-Mbit boot block

flash family is designed to accommodate either de-
sign practice It is strongly recommended that RP
be tied to logical Reset for data protection during
unstable CPU reset function as described in the
``Product Family Overview'' section

3 3 1 BOOT BLOCK WRITE OPERATIONS

In the case of Boot Block modifications (write and
erase) RP

is set to V

12V typically in addi-

tion to V

at high voltage However if RP

is not at

when a program or erase operation of the boot

block is attempted the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase refer to
Table 4 for Status Register Definitions) is set to indi-
cate the failure to complete the operation

3 3 2 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) serves as the
interface to the microprocessor The CUI points the
read write path to the appropriate circuit block as
described in the previous section After the WSM
has completed its task it will set the WSM Status bit
to a ``1'' which will also allow the CUI to respond to
its full command set Note that after the WSM has
returned control to the CUI the CUI will remain in its
current state

3 3 2 1 Command Set

Command

Device Mode

Codes

Invalid Reserved

Alternate Program Setup

Erase Setup

Program Setup

Clear Status Register

Read Status Register

Intelligent Identifier

Erase Suspend

Erase Resume Erase Confirm

Read Array

3 3 2 2 Command Function Descriptions

Device operations are selected by writing specific
commands into the CUI Table 3 defines the 2-Mbit
boot block flash family commands

A28F200BX-T B

Table 3 Command Definitions

Command

Bus

Notes

First Bus Cycle

Second Bus Cycle

Cycles

Req'd

Operation Address Data Operation Address Data

Read Array Reset

Write

FFH

Intelligent Identifier

2 4

Write

90H

Read

IID

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Erase Setup Erase Confirm

Write

20H

Write

D0H

Word Byte Write Setup Write

6 7

Write

40H

Write

Erase Suspend Erase Resume

Write

B0H

Write

D0H

Alternate Word Byte Write Setup Write

6 7

Write

10H

Write

NOTES
1 Bus operations are defined in Tables 1 2
2 IA

Identifier Address 00H for manufacturer code 01H for device code

3 SRD

Data read from Status Register

4 IID

Intelligent Identifier Data

Following the Intelligent Identifier Command two read operations access manufacturer and device codes
5 BA

Address within the block being erased

6 PA

Address to be programmed

Data to be programmed at location PA

7 Either 40H or 10H command is valid
8 When writing commands to the device the upper data bus DQ8 � DQ15

X which is either V

or V

to avoid burning

additional current

Invalid Reserved

These are unassigned commands It is not recom-
mended that the customer use any command other
than the valid commands specified above Intel re-
serves the right to redefine these codes for future
functions

Read Array (FFH)

This single write command points the read path at
the array If the host CPU performs a CE

controlled read immediately following a two-write se-
quence that started the WSM then the device will
output status register contents If the Read Array
command is given after Erase Setup the device is
reset to read the array A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup

Intelligent Identifier (90H)

After this command is executed the CUI points the
output path to the Intelligent Identifier circuits Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode all
other address inputs are ignored)

Read Status Register (70H)

This is one of the two commands that is executable
while the state machine is operating After this com-
mand is written a read of the device will output the
contents of the status register regardless of the ad-
dress presented to the device

The device automatically enters this mode after pro-
gram or erase has completed

Clear Status Register (50H)

The WSM can only set the Program Status and
Erase Status bits in the status register it can not
clear them Two reasons exist for operating the
status register in this fashion The first is a synchro-
nization The WSM does not know when the host
CPU has read the status register therefore it would
not know when to clear the status bits Secondly if
the CPU is programming a string of bytes it may be
more efficient to query the status register after pro-
gramming the string Thus if any errors exist while
programming the string the status register will return
the accumulated error status

A28F200BX-T B

Program Setup (40H or 10H)

This command simply sets the CUI into a state such
that the next write will load the address and data
registers Either 40H or 10H can be used for Pro-
gram Setup Both commands are included to ac-
commodate efforts to achieve an industry standard
command code set

Program

The second write after the program setup command
will latch addresses and data Also the CUI initiates
the WSM to begin execution of the program algo-
rithm While the WSM finishes the algorithm the de-
vice will output Status Register contents Note that
the WSM cannot be suspended during program-
ming

Erase Setup (20H)

Prepares the CUI for the Erase Confirm command
No other action is taken lf the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a ``1'' place the device into the
Read Status Register state and wait for another
command

Erase Confirm (D0H)

If the previous command was an Erase Setup com-
mand then the CUI will enable the WSM to erase at
the same time closing the address and data latches
and respond only to the Read Status Register and
Erase Suspend commands While the WSM is exe-
cuting the device will output Status Register data
when OE

is toggled low Status Register data can

only be updated by toggling either OE

or CE

low

Erase Suspend (B0H)

This command only has meaning while the WSM is
executing an Erase operation and therefore will only
be responded to during an erase operation After
this command has been executed the CUl will set
an output that directs the WSM to suspend Erase
operations and then return to responding to only
Read Status Register or to the Erase Resume com-
mands Once the WSM has reached the Suspend
state it will set an output into the CUI which allows
the CUI to respond to the Read Array Read Status
Register and Erase Resume commands In this
mode the CUI will not respond to any other com-
mands The WSM will also set the WSM Status bit to
a ``1'' The WSM will continue to run idling in the
SUSPEND state regardless of the state of all input

control pins with the exclusion of RP

will

immediately shut down the WSM and the remainder
of the chip During a suspend operation the data
and address latches will remain closed but the ad-
dress pads are able to drive the address into the
read path

Erase Resume (D0H)

This command will cause the CUI to clear the Sus-
pend state and set the WSM Status bit to a ``0'' but
only if an Erase Suspend command was previously
issued Erase Resume will not have any effect in all
other conditions

3 3 3 STATUS REGISTER

The 2-Mbit boot block flash family contains a status
register which may be read to determine when a pro-
gram or erase operation is complete and whether
that operation completed successfully The status
register may be read at any time by writing the Read
Status command to the CUI After writing this com-
mand all subsequent Read operations output data
from the status register until another command is
written to the CUI A Read Array command must be
written to the CUI to return to the Read Array mode

The status register bits are output on DQ 0 7
whether the device is in the byte-wide (x8) or word-
wide (x16) mode In the word-wide mode the upper
byte DQ 8 15 is set to 00H during a Read Status
command In the byte-wide mode DQ 8 14 are tri-
stated and DQ15 Ab1 retains the low order ad-
dress function

It should be noted that the contents of the status
register are latched on the falling edge of OE

whichever occurs last in the read cycle This

prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register CE

or OE

must be toggled

with each subsequent status read or the completion
of a program or erase operation will not be evident

The Status Register is the interface between the mi-
croprocessor and the Write State Machine (WSM)
When the WSM is active this register will indicate
the status of the WSM and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation The WSM sets
status bits ``Three'' through ``Seven'' and clears bits
``Six'' and ``Seven'' but cannot clear status bits
``Three'' through ``Five'' These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command

A28F200BX-T B

3 3 3 1 Status Register Bit Definition

Table 4 Status Register Definitions

WSMS

ESS

VPPS

NOTES

SR 7

WRITE STATE MACHINE STATUS

Ready

Busy

Write State Machine Status bit must first be checked to
determine byte word program or block erase completion
before the Program or Erase Status bits are checked for
success

SR 6

ERASE SUSPEND STATUS

Erase Suspended

Erase in Progress Completed

When Erase Suspend is issued WSM halts execution
and sets both WSMS and ESS bits to ``1'' ESS bit re-
mains set to ``1'' until an Erase Resume command is is-
sued

SR 5

ERASE STATUS

Error in Block Erasure

Successful Block Erase

When this bit is set to ``1'' WSM has applied the maxi-
mum number of erase pulses to the block and is still un-
able to successfully perform an erase verify

SR 4

PROGRAM STATUS

Error in Byte Word Program

Successful Byte Word Program

When this bit is set to ``1'' WSM has attempted but failed
to Program a byte or word

SR 3

STATUS

Low Detect Operation Abort

The V

Status bit unlike an A D converter does not

provide continuous indication of V

level The WSM in-

terrogates the V

level only after the byte write or block

erase command sequences have been entered and in-
forms the system if V

has not been switched on The

Status bit is not guaranteed to report accurate feed-

back between V

PPL

and V

PPH

SR 2 � SR 0

RESERVED FOR FUTURE ENHANCE-

MENTS

These bits are reserved for future use and should be
masked out when polling the Status Register

3 3 3 2 Clearing the Status Register

Certain bits in the status register are set by the write
state machine and can only be reset by the system
software These bits can indicate various failure con-
ditions By allowing the system software to control
the resetting of these bits several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in se-
quence) The status register may then be read to
determine if an error occurred during that program-
ming or erasure series This adds flexibility to the
way the device may be programmed or erased To
clear the status register the Clear Status Register
command is written to the CUI Then any other
command may be issued to the CUI Note again that
before a read cycle can be initiated a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array
status register or Intelligent Identifier

3 3 4 PROGRAM MODE

Program is executed by a two-write sequence The
Program Setup command is written to the CUI fol-
lowed by a second write which specifies the address
and data to be programmed The write state ma-
chine will execute a sequence of internally timed
events to
1 Program the desired bits of the addressed memo-

ry word (byte) and

2 Verify that the desired bits are sufficiently pro-

grammed

Programming of the memory results in specific bits
within a byte or word being changed to a ``0''

If the user attempts to program ``1''s there will be no
change of the memory cell content and no error oc-
curs

Similar to erasure

the status register indicates

whether programming is complete While the pro-
gram sequence is executing bit 7 of the status regis-
ter is a ``0'' The status register can be polled by

A28F200BX-T B

toggling either CE

or OE

to determine when the

program sequence is complete

Only the Read

Status Register command is valid while program-
ming is active

When programming is complete the status bits
which indicate whether the program operation was
successful should be checked If the programming
operation was unsuccessful Bit 4 of the status regis-
ter is set to a ``1'' to indicate a Program Failure lf Bit
3 is set then V

was not within acceptable limits

and the WSM will not execute the programming se-
quence

The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after programming is completed however it
must be recognized that reads from the memory
status register or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read

Figure 6 shows a system software flowchart for de-
vice byte programming operation Figure 7 shows a
similar flowchart for device word programming oper-
ation (A28F200BX-only)

3 3 5 ERASE MODE

Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI along with the addresses A 12 16

identifying

the block to be erased These addresses are latched
internally when the Erase Confirm command is is-
sued Block erasure results in all bits within the block
being set to ``1''

The WSM will execute a sequence of internally
timed events to
1 Program all bits within the block
2 Verify that all bits within the block are sufficiently

programmed

3 Erase all bits within the block and
4 Verify that all bits within the block are sufficiently

erased

While the erase sequence is executing Bit 7 of the
status register is a ``0''

When the status register indicates that erasure is
complete the status bits which indicate whether the
erase operation was successful should be checked
If the erasure operation was unsuccessful Bit 5 of
the status register is set to a ``1'' to indicate an
Erase Failure If V

was not within acceptable limits

after the Erase Confirm command is issued the
WSM will not execute an erase sequence instead
Bit 5 of the status register is set to a ``1'' to indicate

an Erase Failure and Bit 3 is set to a ``1'' to identify
that V

supply voltage was not within acceptable

limits

The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after erasure is completed however it must
be recognized that reads from the memory array
status register or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read

Figure 8 shows a system software flowchart for
Block Erase operation

3 3 5 1 Suspending and Resuming Erase

Since an erase operation typically requires 1 5 to 3
seconds to complete an Erase Suspend command
is provided This allows erase-sequence interruption
in order to read data from another block of the mem-
ory Once the erase sequence is started writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se-
quence at a predetermined point in the erase algo-
rithm The status register must be read to determine
when the erase operation has been suspended

At this point a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended The only other
valid command at this time is the Erase Resume
command or Read Status Register operation

Figure 9 shows a system software flowchart detail-
ing the operation

During Erase Suspend mode the chip can go into a
pseudo-standby mode by taking CE

to V

and the

active current is now a maximum of 10 mA If the
chip is enabled while in this mode by taking CE

the Erase Resume command can be issued to

resume the erase operation

Upon completion of reads from any block other than
the block being erased the Erase Resume com-
mand must be issued When the Erase Resume
command is given the WSM will continue with the
erase sequence and complete erasing the block As
with the end of erase the status register must be
read cleared and the next instruction issued in or-
der to continue

3 4 6 EXTENDED CYCLING

Intel has designed extended cycling capability into
its ETOX III flash memory technology The 2-Mbit
boot block flash family is designed for 1 000 pro-
gram erase cycles on each of the five blocks The
combination of low electric fields clean oxide pro-
cessing and minimized oxide area per memory cell
subjected to the tunneling electric field results in
very high cycling capability

A28F200BX-T B

290500 � 5

Bus

Command

Comments

Operation

Write

Setup

Data

40H

Program

Address

Byte to be

programmed

Write

Program

Data to be programmed
Address

Byte to be

programmed

Read

Status Register Data
Toggle OE

or CE

to update

Status Register

Standby

Check SR 7
1

Ready 0

Busy

Repeat for subsequent bytes

Full status check can be done after each byte or after a
sequence of bytes

Write FFH after the last byte programming operation to
reset the device to Read Array Mode

Full Status Check Procedure

290500 � 6

Bus

Command

Comments

Operation

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4
1

Byte Program Error

SR 3 MUST be cleared if set during a program attempt
before further attempts are allowed by the Write State
Machine

SR 4 is only cleared by the Clear Status Register
Command in cases where multiple bytes are programmed
before full status is checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 6 Automated Byte Programming Flowchart

A28F200BX-T B

290500 � 7

Bus

Command

Comments

Operation

Write

Setup

Data

40H

Program

Address

Word to be

programmed

Write

Program

Data to be programmed
Address

Word to be

programmed

Read

Status Register Data
Toggle OE

or CE

to update

Status Register

Standby

Check SR 7
1

Ready 0

Busy

Repeat for subsequent words

Full status check can be done after each word or after a
sequence of words

Write FFH after the last word programming operation to
reset the device to Read Array Mode

Full Status Check Procedure

290500 � 8

Bus

Command

Comments

Operation

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4
1

Word Program Error

SR 3 MUST be cleared if set during a program attempt
before further attempts are allowed by the Write State
Machine

SR 4 is only cleared by the Clear Status Register
Command in cases where multiple words are programmed
before full status is checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 7 Automated Word Programming Flowchart

A28F200BX-T B

290500 � 9

Bus

Command

Comments

Operation

Write

Setup

Data

20H

Erase

Address

Within block to be

erased

Write

Erase

Data

D0H

Address

Within block to be

erased

Read

Status Register Data
Toggle OE

or CE

to update

Status Register

Standby

Check SR 7
1

Ready 0

Busy

Repeat for subsequent blocks

Full status check can be done after each block or after a
sequence of blocks

Write FFH after the last block erase operation to reset the
device to Read Array Mode

Full Status Check Procedure

290500 � 10

Bus

Command

Comments

Operation

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4 5
Both 1

Command Sequence

Error

Standby

Check SR 5
1

Block Erase Error

SR 3 MUST be cleared if set during an erase attempt
before further attempts are allowed by the Write State
Machine

SR 5 is only cleared by the Clear Status Register
Command in cases where multiple blocks are erased
before full status is checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 8 Automated Block Erase Flowchart

A28F200BX-T B

290500 � 11

Bus

Command

Comments

Operation

Write

Erase

Data

B0H

Suspend

Read

Status Register Data
Toggle OE

or CE

update Status Register

Standby

Check SR 7
1

Ready

Standby

Check SR 6
1

Suspended

Write

Read Array

Data

FFH

Read

Read array data from block
other than that being
erased

Write

Erase Resume

Data

D0H

Figure 9 Erase Suspend Resume Flowchart

3 4 Power Consumption

3 4 1 ACTIVE POWER

With CE

at a logic-low level and RP

at a logic-

high level the device is placed in the active mode
The device I

current is a maximum of 65 mA at

10 MHz with TTL input signals

3 4 2 AUTOMATIC POWER SAVINGS

Automatic Power Savings (APS) is a low power fea-
ture during active mode of operation The 2-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed After data is read from the
memory array PRC logic controls the device's pow-
er consumption by entering the APS mode where

maximum I

current is 3 mA and typical I

current

is 1 mA The device stays in this static state with
outputs valid until a new location is read

3 4 3 STANDBY POWER

With CE

at a logic-high level (V

) and the CUI in

read mode the memory is placed in standby mode
where the maximum I

standby current is 100 mA

with CMOS input signals The standby operation dis-
ables much of the device's circuitry and substantially
reduces device power consumption The outputs
(DQ 0 15 or DQ 0 7 ) are placed in a high-imped-
ance state independent of the status of the OE
signal When the 2-Mbit boot block flash family is
deselected during erase or program functions the
devices will continue to perform the erase or pro-
gram function and consume program or erase active
power until program or erase is completed

A28F200BX-T B

3 4 4 RESET DEEP POWER-DOWN

The 2-Mbit boot block flash family has a RP

which places the device in the deep power-down
mode When RP

is at a logic-low (GND

0 2V) all

circuits are turned off and the device typically draws
a maximum 80 mA of V

current

During read modes the RP

pin going low dese-

lects the memory and places the output drivers in a
high impedance state Recovery from the deep pow-
er-down state requires a minimum of 300 ns to ac-
cess valid data (t

PHQV

)

During erase or program modes RP

low will abort

either erase or program operation The contents of
the memory are no longer valid as the data has been
corrupted by the RP

function As in the read mode

above all internal circuitry is turned off to achieve
the low current level

transitions to V

or turning power off to the

device will clear the status register

This use of RP

during system reset is important

with automated write erase devices When the sys-
tem comes out of reset it expects to read from the
flash memory Automated flash memories provide
status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel's
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
input In this application RP

is controlled by the

same RESET

signal that resets the system CPU

3 5 Power-Up Operation

The 2-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions Upon power-
up the 2-Mbit boot block flash family is indifferent as
to which power supply V

or V

powers-up first

Power suppy sequencing is not required

The 2-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up

In addition on power-up the user must either drop
CE

low or present a new address to ensure valid

data at the outputs

A system designer must guard against spurious
writes for V

voltages above V

LKO

when V

active Since both WE

and CE

must be low for a

command write driving either signal to V

will inhibit

writes to the device The CUI architecture provides
an added level of protection since alteration of mem-

ory contents can only occur after successful com-
pletion of the two-step command sequences Final-
ly the device is disabled until RP

is brought to V

regardless of the state of its control inputs This fea-
ture provides yet another level of memory protec-
tion

3 6 Power Supply Decoupling

Flash memory's power switching characteristics re-
quire careful device decoupling methods System
designers are interested in 3 supply current issues

Standby current levels (I

CCS

)

Active current levels (I

CCR

)

Transient peaks produced by falling and rising
edges of CE

Transient current magnitudes depend on the device
outputs' capacitive and inductive loading Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks Each
flash device should have a 0 1 mF ceramic capacitor
connected between each V

and GND and be-

tween its V

and GND These high frequency low-

inherent inductance capacitors should be placed as
close as possible to the package leads

3 6 1 V

TRACE ON PRINTED CIRCUIT

BOARDS

Writing to flash memories while they reside in the
target system requires special consideration of the
V

power supply trace by the printed circuit board

designer The V

pin supplies the flash memory

cell's current for programming and erasing One
should use similar trace widths and layout consider-
ations given to the V

power supply trace Ade-

quate V

supply traces and decoupling will de-

crease spikes and overshoots

3 6 2 V

AND RP

TRANSITIONS

The CUI latches commands as issued by system
software and is not altered by V

or CE

tran-

sitions or WSM actions Its state upon power-up af-
ter exit from deep power-down mode or after V

transitions below V

LKO

(Lockout voltage) is Read

Array mode

After any word byte write or block erase operation is
complete and even after V

transitions down to

PPL

the CUI must be reset to Read Array mode via

the Read Array command when accesses to the
flash memory are desired

A28F200BX-T B

ABSOLUTE MAXIMUM RATINGS

Automatic Operating Temperature

During Read

40 C to a125 C

During Block Erase
and Word Byte Write

40 C to a125 C

Temperature Under Bias

40 C to a125 C

Storage Temperature

65 C to a150 C

Voltage on Any Pin

(except V

and RP )

with Respect to GND

2 0V to a7 0V

(2)

Voltage on Pin RP

or Pin A

with Respect to GND

2 0V to a13 5V

(2 3)

Program Voltage with Respect

to GND during Block Erase
and Word Byte Write

2 0V to a14 0V

(2 3)

Supply Voltage

with Respect to GND

2 0V to a7 0V

(2)

Output Short Circuit Current

100 mA

(4)

NOTICE This data sheet contains information on
products in the sampling and initial production phases
of development The specifications are subject to
change without notice Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

NOTES
1 Operating temperature is for automotive product defined by this specification
2 Minimum DC voltage is

0 5V on input output pins During transitions this level may undershoot to

2 0V for periods

20 ns Maximum DC voltage on input output pins is V

0 5V which during transitions may overshoot to V

2 0V

for periods

20 ns

3 Maximum DC voltage on V

may overshoot to

14 0V for periods

20 ns Maximum DC voltage on RP

or A

may

overshoot to 13 5V for periods

20 ns

4 Output shorted for no more than one second No more than one output shorted at a time

OPERATING CONDITIONS

Symbol

Parameter

Notes

Min

Max

Units

Operating Temperature

125

Supply Voltage (10%)

4 50

5 50

DC CHARACTERISTICS

Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

Input Load Current

1 0

Max

or GND

Output Leakage Current

Max

OUT

or GND

CCS

Standby Current

1 3

1 5

Max

130

Max

0 2V

A28F200BX
BYTE

0 2V or GND

A28F200BX-T B

DC CHARACTERISTICS

(Continued)

Symbol

Parameter

Notes Min Typ

Max

Unit

Test Condition

CCD

Deep Power-Down Current

A RP

GND

0 2V

CCR

Read Current for

1 5

mA V

Max CE

GND

A28F200BX Byte-Wide and

f e 10 MHz I

OUT

0 mA

Word-Wide Mode

CMOS Inputs

mA V

Max CE

f e 10 MHz I

OUT

0 mA

TTL Inputs

CCW

Write Current

1 4

mA Word Write in Progress

CCE

Block Erase Current

1 4

mA Block Erase in Progress

CCES

Erase Suspend Current

1 2

mA Block Erase Suspended

PPS

Standby Current

A V

PPD

Deep Power-Down Current

5 0

A RP

GND

0 2V

PPR

Read Current

200

A V

PPW

Word Write Current

1 4

mA V

PPH

Word Write in Progress

PPW

Byte Write Current

1 4

mA V

PPH

Byte Write in Progress

PPE

Block Erase Current

1 4

mA V

PPH

Block Erase in Progress

PPES

Erase Suspend Current

200

A V

PPH

Block Erase Suspended

Current

1 4

500

A RP

Intelligent Identifier Current

1 4

500

A A

Intelligent Identifier Voltage

11 5

13 0

Input Low Voltage

0 5

0 8

Input High Voltage

2 0

0 5 V

Output Low Voltage

0 45

V V

Min

5 8 mA

Output High Voltage

2 4

V V

Min

e b

2 5 mA

PPL

during Normal Operations

0 0

6 5

PPH

during Erase Write Operations

11 4 12 0

12 6

LKO

Erase Write Lock Voltage

2 0

Unlock Voltage

11 5

13 0

V Boot Block Write Erase

A28F200BX-T B

CAPACITANCE

(4)

25 C f e 1 MHz

Symbol

Parameter

Typ

Max

Unit

Condition

Input Capacitance

OUT

Output Capacitance

OUT

NOTES
1 All currents are in RMS unless otherwise noted Typical values at V

5 0V V

12 0V T

25 C These currents

are valid for all product versions (packages and speeds)
2 I

CCES

is specified with the device deselected If the device is read while in Erase Suspend Mode current draw is the sum

of I

CCES

and I

CCR

3 Block Erases and Word Byte Writes are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and

PPL

4 Sampled not 100% tested
5 Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical in static operation

6 CMOS Inputs are either V

0 2V or GND

0 2V TTL Inputs are either V

or V

7 V

12 0V

5% for applications requiring 1 000 block erase cycles

STANDARD TEST CONFIGURATION

STANDARD AC INPUT OUTPUT
REFERENCE WAVEFORM

290500 � 12

AC test inputs are driven at V

(2 4 V

TTL

) for a Logic ``1'' and V

(0 45 V

TTL

) for a logic ``0'' Input timing begins at V

(2 0 V

TTL

) and V

(0 8 V

TTL

) Output timing ends at V

and V

Input rise and fall times (10%

to 90%)

10 ns

STANDARD AC TESTING
LOAD CIRCUIT

290500 � 13

100 pF

Includes Jig Capacitance

3 3 KX

A28F200BX-T B

AC CHARACTERISTICS

Read Only Operations

(1)

Versions

A28F200BX-90

(4)

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Read Cycle Time

AVQV

ACC

Address to

Output Delay

ELQV

to Output Delay

PHQV

PWH

High to

300

Output Delay

GLQV

to Output Delay

ELQX

to Output Low Z

EHQZ

High to Output

High Z

GLQX

OLZ

to Output Low Z

GHQZ

High to Output

High Z

Output Hold from

Addresses
CE

or OE

Change

Whichever is First

ELFL

to BYTE

ELFH

Switching
Low or High

FHQV

BYTE

Switching

3 5

High to
Valid Output Delay

FLQZ

BYTE

Switching

Low to
Output High Z

NOTES
1 See AC Input Output Reference Waveform for timing measurements
2 OE

may be delayed up to t

� t

after the falling edge of CE

without impact on t

3 Sampled not 100% tested
4 See Standard Test Configuration
5 t

FLQV

BYTE

switching low to valid output delay will be equal to t

AVQV

measured from the time DQ

A-

becomes

valid

A28F200BX-T B

AC CHARACTERISTICS

For WE -Controlled Write Operations

(1)

Versions

(4)

A28F200BX-90

(9)

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Write Cycle Time

PHWL

High Recovery to

210

Going Low

ELWL

Setup to WE

Going Low

PHHWH

PHS

Setup to WE

Going High

6 8

100

VPWH

VPS

Setup to WE

Going High

5 8

100

AVWH

Address Setup to WE

Going High

DVWH

Data Setup to WE

Going High

WLWH

Pulse Width

WHDX

Data Hold from WE

High

WHAX

Address Hold from WE

High

WHEH

Hold from WE

High

WHWL

WPH

Pulse Width High

WHQV1

Duration of Word Byte

2 5

Write Operation

WHQV2

Duration of Erase Operation (Boot)

2 5 6

0 4

WHQV3

Duration of Erase

2 5

0 4

Operation (Parameter)

WHQV4

Duration of Erase Operation (Main)

2 5 6

0 7

QWL

VPH

Hold from Valid SRD

5 8

QVPH

PHH

Hold from Valid SRD

6 8

PHBR

Boot-Block Relock Delay

7 8

100

NOTES
1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
Characteristics during Read Mode
2 The on-chip WSM completely automates program erase operations program erase algorithms are now controlled inter-
nally which includes verify and margining operations
3 Refer to command definition table for valid A

4 Refer to command definition table for valid D

5 Program Erase durations are measured to valid SRD data (successful operation SR 7

6 For Boot Block Program Erase RP

should be held at V

until operation completes successfully

7 Time t

PHBR

is required for successful relocking of the Boot Block

8 Sampled but not 100% tested
9 See Standard Test Configuration

A28F200BX-T B

AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS

(1 9)

Versions

A28F200BX-90

(10)

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Write Cycle Time

PHEL

High Recovery

210

to CE

Going Low

WLEL

Setup to CE

Going Low

PHHEH

PHS

Setup to

6 8

100

Going High

VPEH

VPS

Setup to CE

5 8

100

Going High

AVEH

Address Setup to

Going High

DVEH

Data Setup to CE

Going High

ELEH

Pulse Width

EHDX

Data Hold from

High

EHAX

Address Hold

from CE

High

EHWH

Hold from CE

High

EHEL

CPH

Pulse

Width High

EHQV1

Duration of Word Byte

2 5

Programming
Operation

EHQV2

Duration of Erase

2 5 6

0 4

Operation (Boot)

EHQV3

Duration of Erase

2 5

0 4

Operation (Parameter)

EHQV4

Duration of Erase

2 5

0 7

Operation (Main)

QWL

VPH

Hold from

5 8

Valid SRD

QVPH

PHH

Hold

6 8

from Valid SRD

PHBR

Boot-Block Relock Delay

100

NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE

and WE

in systems where

defines the write pulse-width (within a longer WE

timing waveform) all set-up hold and inactive WE

time should be

measured relative to the CE

waveform

2 3 4 5 6 7 8 Refer to AC Characteristics for WE -Controlled Write Operations
9 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
Characteristics during Read Mode
10 See Standard Test Configuration

Электронный компонент: A28F200BX-B