Электронный компонент: CD2231

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CD2231

Intelligent Two-Channel LAN and WAN Communications Controller

Datasheet

The CD2231 is a two-channel multi-protocol synchronous/asynchronous communications
controller specifically designed to reduce host-system processing overhead and increase
efficiency in a wide variety of communications applications. The CD2231 is packaged in a 100-
pin MQFP, and offers eight clock/modem pins per channel. The device has two fully
independent serial channels that support asynchronous, asynchronous-HDLC (PPP),
synchronous HDLC/SDLC, SLIP, and MNP

4 protocols at serial data rates up to 256 kbps,

(230.4 kbps in async modes) when clocked by a 35-MHz source.

The device is based on a proprietary on-chip RISC processor that performs all time-critical, low-
level tasks that are otherwise performed by the host system.

The CD2231 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored
interrupts, and intelligent protocol processing. The on-chip DMA controller provides `fire-and-
forget' transmit support -- the host need only inform the CCD2231 of the location of the packet
to be sent. Similarly, on receive, the CD2231 automatically receives a complete packet with no
host intervention or assistance required. The DMA controller also has an `Append mode' for use
in asynchronous applications.

The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer
schemes. Each channel and direction has two active buffers.

The CD2231 can be programmed to interrupt the host at the completion of a frame or buffer. In
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames
to be divided into multiple buffers.

For applications where a DMA interface is not desired, the device can be operated as an
interrupt-driven or polled device. This choice is available individually for each channel and each
direction. For example, a channel can be programmed for DMA transmit and interrupt-driven
receive.

In either case, 16-byte FIFOs on each channel and in each direction reduce latency time
requirements, making both software and hardware designs less time-critical. Threshold levels on
FIFOs are user-programmable.

Efficient vectored interrupts are another way the CD2231 helps system efficiency. Separate
interrupts are generated for transmit, receive, and modem-signal change with unique user-
defined vectors for each type and channel. This allows very flexible interfacing and fast,
efficient interrupt coding.

As of May 2001, this document replaces the Basis
Communications Corp. document

May 2001

CL-CD2231 -- Intelligent Two-Channel LAN and WAN Communications Controller.

Datasheet

Information in this document is provided in connection with Intel

�

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The CD2231 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright � Intel Corporation, 2001

*Third-party brands and names are the property of their respective owners.

Datasheet

3

Intelligent Two-Channel LAN and WAN Communications Controller -- CD2231

Contents

1.0

Features

......................................................................................................................... 9

1.1

Benefits ............................................................................................................... 11

2.0

Conventions

............................................................................................................... 13

3.0

Pin Information

.......................................................................................................... 15

3.1

Pin Diagram......................................................................................................... 15

3.2

Pin Functions....................................................................................................... 16

3.3

Pin Descriptions .................................................................................................. 16

4.0

Register Table

............................................................................................................20

4.1

Memory Map ....................................................................................................... 20
4.1.1

Global Registers..................................................................................... 20

4.1.2

Option Registers..................................................................................... 20

4.1.3

Bit Rate and Clock Option Registers...................................................... 21

4.1.4

Channel Command and Status Registers .............................................. 22

4.1.5

Receive Interrupt Registers.................................................................... 22

4.1.6

Transmit Interrupt Registers................................................................... 22

4.1.7

DMA Registers ....................................................................................... 23

4.1.8

Timer Registers ...................................................................................... 24

4.2

Register Definitions ............................................................................................. 24
4.2.1

Global Registers..................................................................................... 24

4.2.2

Option Registers..................................................................................... 25

4.2.3

Bit Rate and Clock Option Registers...................................................... 27

4.2.4

Channel Command and Status Registers .............................................. 28

4.2.5

Interrupt Registers..................................................................................29

4.2.6

DMA Registers ....................................................................................... 31

4.2.7

Timer Registers ...................................................................................... 33

5.0

Functional Description

........................................................................................... 34

5.1

Host Interface ......................................................................................................34
5.1.1

Host Read and Write Cycles .................................................................. 34

5.1.2

Byte and Word Transfers ....................................................................... 36

5.2

Interrupts ............................................................................................................. 36
5.2.1

Contexts and Channels .......................................................................... 37

5.2.2

Interrupt Registers..................................................................................37

5.2.3

Groups and Types..................................................................................38

5.2.4

Hardware Signals and IACK Cycles ....................................................... 39

5.2.5

Multi CD2231 Systems ........................................................................... 40

5.3

FIFO and Timer Operations ................................................................................ 41
5.3.1

Receive FIFO Operation ........................................................................ 41

5.3.2

Transmit FIFO Operation ....................................................................... 41

5.3.3

Timers .................................................................................................... 41

5.3.4

Timers in Synchronous Protocols........................................................... 42

5.3.5

Timers in Asynchronous Protocols......................................................... 42

5.3.6

Transmit Timer ....................................................................................... 42

5.4

DMA Operation.................................................................................................... 42

CD2231 -- Intelligent Two-Channel LAN and WAN Communications Controller

4

Datasheet

5.4.1

Bus Acquisition Cycle............................................................................. 43

5.4.2

DMA Data Transfer ................................................................................ 43

5.4.3

Bus Error Handling ................................................................................. 44

5.4.4

A and B Buffers and Chaining ................................................................ 45

5.4.5

Transmit DMA Transfer .......................................................................... 46

5.4.6

Synchronous Transmitter Examples ...................................................... 47

5.4.7

Receive DMA Transfer ........................................................................... 49

5.4.8

Transmit DMA Transfer .......................................................................... 52

5.4.9

Receive Buffer Interrupts ....................................................................... 55

5.5

Bit Rate Generation and Data Encoding ............................................................. 57
5.5.1

BRG and DPLL Operation...................................................................... 57

5.6

Hardware Configurations .................................................................................... 64
5.6.1

Interface to a 32-Bit Data Bus ................................................................ 65

5.6.2

DMA Connections for the CD2231 ......................................................... 65

5.6.3

CD2231 as a DTE and DCE Interface.................................................... 65

6.0

Protocol Processing

............................................................................................... 67

6.1

HDLC Processing................................................................................................ 67
6.1.1

Frame Check Sequence ........................................................................ 67

6.1.2

HDLC Transmit Mode............................................................................. 67

6.1.3

HDLC Receive Mode ............................................................................. 68

6.2

PPP (Point-to-Point Protocol) Mode.................................................................... 69
6.2.1

Character Format ................................................................................... 69

6.2.2

Frame Format ........................................................................................ 69

6.2.3

Frame Check Sequence ........................................................................ 69

6.2.4

Transparency ......................................................................................... 70

6.2.5

Definition of a Valid Frame ..................................................................... 71

6.2.6

Transmitter ............................................................................................. 71

6.2.7

Receiver ................................................................................................. 72

6.3

SLIP Processing.................................................................................................. 72
6.3.1

Framing .................................................................................................. 73

6.3.2

Debugging Aids ...................................................................................... 73

6.4

MNP,4/ARAP Protocol Processing...................................................................... 73
6.4.1

Framing .................................................................................................. 74

6.4.2

MNP,4/ARAP FCS (Frame Check Sequence) Calculation..................... 74

6.5

Async Processing................................................................................................ 75
6.5.1

Transmitter In-Band Flow Control .......................................................... 75

6.5.2

Out-of-Band Flow Control ...................................................................... 77

6.5.3

Line Break Detection and Generation .................................................... 78

6.5.4

Special Character Transmission ............................................................ 78

6.5.5

Special Character Recognition and Special Character Range............... 79

6.5.6

Special Character Range ....................................................................... 79

6.5.7

UNIX, Support Features ......................................................................... 80

6.6

Non-8-Bit Data Transfers .................................................................................... 80

7.0

Programming Examples

........................................................................................ 84

7.1

Global Initialization .............................................................................................. 85

7.2

Async Interrupt Setup Example........................................................................... 85

7.3

HDLC DMA Channel Setup Example.................................................................. 86

7.4

Receive DMA Interrupt Service Routine ............................................................. 86

Datasheet

5

Intelligent Two-Channel LAN and WAN Communications Controller -- CD2231

7.5

Transmit Interrupt Service Routine...................................................................... 87

8.0

Detailed Register Descriptions

........................................................................... 88

8.1

Global Registers.................................................................................................. 88
8.1.1

Global Firmware Revision Code Register (GFRCR) .............................. 88

8.1.2

Channel Access Register (CAR) ............................................................ 88

8.2

Option Registers.................................................................................................. 89
8.2.1

Channel Mode Register (CMR) .............................................................. 89

8.2.2

Channel Option Register 1 (COR1)........................................................ 90

8.2.3

Channel Option Register 2 (COR2)........................................................ 92

8.2.4

Channel Option Register 3 (COR3) -- Async-HDLC/PPP Mode ...........94

8.2.5

Channel Option Register 4 (COR4)........................................................ 98

8.2.6

Channel Option Register 5 (COR5)........................................................ 99

8.2.7

Channel Option Register 6 (COR6) -- Async Mode Only .................... 100

8.2.8

Channel Option Register 7 (COR7) -- Async Mode Only .................... 101

8.2.9

Special Character Registers -- Async Modes Only .............................102

8.2.10 Special Character Range -- Async Mode Only ...................................104
8.2.11 LNext Character (LNXT) -- Async Mode Only..................................... 104
8.2.12 Receive Frame Address Registers -- HDLC Sync Mode Only ............ 105
8.2.13 CRC Polynomial Select Register (CPSR) ............................................ 106
8.2.14 Transmit Special Mapped Characters -- PPP Mode only.................... 106
8.2.15 Transmit Async Control Character Maps -- PPP Mode Only .............. 107
8.2.16 Receive Async Control Character Maps -- PPP Mode Only ............... 108

8.3

Bit Rate and Clock Option Registers................................................................. 110
8.3.1

Receive Baud Rate Generator Registers ............................................. 110

8.3.2

Transmit Baud Rate Generator Registers ............................................ 111

8.4

Channel Command and Status Registers ......................................................... 112
8.4.1

Channel Command Register (CCR) ..................................................... 112

8.4.2

Special Transmit Command Register (STCR) ..................................... 115

8.4.3

Channel Status Register (CSR) ........................................................... 117

8.4.4

Modem Signal Value Registers (MSVR) .............................................. 121

8.5

Interrupt Registers.............................................................................................122
8.5.1

General Interrupt Registers .................................................................. 122

8.5.2

Receive Interrupt Registers.................................................................. 125

8.5.3

Transmit Interrupt Registers................................................................. 133

8.5.4

Modem Interrupt Registers ...................................................................137

8.6

DMA Registers .................................................................................................. 139
8.6.1

DMA Mode Register (DMR) ................................................................. 139

8.6.2

Bus Error Retry Count (BERCNT)........................................................ 140

8.6.3

DMA Buffer Status (DMABSTS) ........................................................... 140

8.6.4

DMA Receive Registers ....................................................................... 141

8.6.5

DMA Transmit Registers ...................................................................... 145

8.7

Timer Registers ................................................................................................. 152
8.7.1

Timer Period Register (TPR)................................................................ 152

8.7.2

Receive Timeout Period Register (RTPR) -- Async Mode Only.......... 153

8.7.3

General Timer 1 (GT1) Sync Modes Only............................................ 154

8.7.4

General Timer 2 (GT2) Sync Modes Only............................................ 154

8.7.5

Transmit Timer Register (TTR) Async Modes Only .............................155

Document Outline

• 1.0 Features
  • Figure 1. Functional Block Diagram
  • 1.1 Benefits
• 2.0 Conventions
• 3.0 Pin Information
  • 3.1 Pin Diagram
  • 3.2 Pin Functions
  • 3.3 Pin Descriptions
    • Table 1. Pin Descriptions (Sheet 1 of 3)
• 4.0 Register Table
  • 4.1 Memory Map
    • 4.1.1 Global Registers
    • 4.1.2 Option Registers
    • 4.1.3 Bit Rate and Clock Option Registers
    • 4.1.4 Channel Command and Status Registers
      • 4.1.4.1 Interrupt Registers
    • 4.1.5 Receive Interrupt Registers
    • 4.1.6 Transmit Interrupt Registers
      • 4.1.6.1 Modem Interrupt Registers
    • 4.1.7 DMA Registers
      • 4.1.7.1 DMA Receive Registers
      • 4.1.7.2 DMA Transmit Registers
    • 4.1.8 Timer Registers
  • 4.2 Register Definitions
    • 4.2.1 Global Registers
    • 4.2.2 Option Registers
    • 4.2.3 Bit Rate and Clock Option Registers
    • 4.2.4 Channel Command and Status Registers
    • 4.2.5 Interrupt Registers
      • 4.2.5.1 Receive Interrupt Registers
      • 4.2.5.2 Transmit Interrupt Registers
      • 4.2.5.3 Modem/Timer Interrupt Registers
    • 4.2.6 DMA Registers
      • 4.2.6.1 DMA Receive Registers
      • 4.2.6.2 DMA Transmit Registers
    • 4.2.7 Timer Registers
• 5.0 Functional Description
  • 5.1 Host Interface
    • 5.1.1 Host Read and Write Cycles
      • Figure 2. Host Read Cycle
      • Figure 3. Host Write Cycle
    • 5.1.2 Byte and Word Transfers
  • 5.2 Interrupts
    • 5.2.1 Contexts and Channels
    • 5.2.2 Interrupt Registers
      • Figure 4. Interrupt Acknowledge Cycle
    • 5.2.3 Groups and Types
      • Table 2. Transmit and Receive Interrupt Service Requests
    • 5.2.4 Hardware Signals and IACK Cycles
      • 5.2.4.1 Programming the PILR Registers
      • 5.2.4.2 Systems with Interrupt Controllers
    • 5.2.5 Multi CD2231 Systems
      • 5.2.5.1 Keep-and-Pass Logic
      • 5.2.5.2 Fair Share Scheme
  • 5.3 FIFO and Timer Operations
    • 5.3.1 Receive FIFO Operation
    • 5.3.2 Transmit FIFO Operation
    • 5.3.3 Timers
    • 5.3.4 Timers in Synchronous Protocols
    • 5.3.5 Timers in Asynchronous Protocols
    • 5.3.6 Transmit Timer
  • 5.4 DMA Operation
    • 5.4.1 Bus Acquisition Cycle
    • 5.4.2 DMA Data Transfer
      • Figure 5. Bus Acquisition Cycle
      • Figure 6. Data Transfer Timing
    • 5.4.3 Bus Error Handling
    • 5.4.4 A and B Buffers and Chaining
      • Table 3. A and B Buffers Chaining (Sheet 1 of 2)
    • 5.4.5 Transmit DMA Transfer
      • Figure 7. Transmitter A and B Buffers
    • 5.4.6 Synchronous Transmitter Examples
    • 5.4.7 Receive DMA Transfer
      • Figure 8. Receiver A and B Buffers
    • 5.4.8 Transmit DMA Transfer
      • 5.4.8.1 Interrupts for Transmit DMA Buffers
      • 5.4.8.2 Chained Buffers
      • Figure 9. DMA Transmit Buffer Selection
      • 5.4.8.3 Append Mode
      • 5.4.8.4 Transmit Bus Errors
    • 5.4.9 Receive Buffer Interrupts
      • 5.4.9.1 Receive Timeout in Asynchronous DMA Mode
      • 5.4.9.2 Receive Bus Errors
  • 5.5 Bit Rate Generation and Data Encoding
    • 5.5.1 BRG and DPLL Operation
      • Figure 10. Bit Rate Generator/DPLL
      • Table 4. Clock Source Select (Sheet 1 of 2)
      • Table 5. Bit Rate Constants, CLK = 20 MHz
      • Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet 1 of 2)
      • Table 7. Bit Rate Constants, CLK = 30 MHz
      • Table 8. Bit Rate Constants, CLK = 35 MHz (Sheet 1 of 2)
      • Figure 11. Data Encoding
      • Figure 12. Transmit Data With External Clock In
      • Figure 13. Transmit Data With External Clock Out
      • Table 9. Data Clock Selection Using External Clock
  • 5.6 Hardware Configurations
    • 5.6.1 Interface to a 32-Bit Data Bus
    • 5.6.2 DMA Connections for the CD2231
      • Figure 14. DMA Connections for the CD2231
    • 5.6.3 CD2231 as a DTE and DCE Interface
      • Table 10. DTE Connections
      • Table 11. DCE Connections
• 6.0 Protocol Processing
  • 6.1 HDLC Processing
    • 6.1.1 Frame Check Sequence
    • 6.1.2 HDLC Transmit Mode
    • 6.1.3 HDLC Receive Mode
  • 6.2 PPP (Point-to-Point Protocol) Mode
    • 6.2.1 Character Format
      • Figure 15. Character Format
    • 6.2.2 Frame Format
      • Figure 16. Point-to-Point Protocol Frame
    • 6.2.3 Frame Check Sequence
    • 6.2.4 Transparency
      • 6.2.4.1 Mapped Characters from 00�1F
      • 6.2.4.2 Mapped Characters from 20 and Above
      • 6.2.4.3 Characters 7D and 7E as Transmitted Data
      • 6.2.4.4 Mapped Characters in the FCS Field
    • 6.2.5 Definition of a Valid Frame
    • 6.2.6 Transmitter
      • 6.2.6.1 Fixed Transmitter Operations
      • 6.2.6.2 Transmitter Options
      • 6.2.6.3 Transmission of Abort
      • 6.2.6.4 Transmit Framing Error
    • 6.2.7 Receiver
      • 6.2.7.1 Fixed Receiver Operations
      • 6.2.7.2 Receiver Options
  • 6.3 SLIP Processing
    • 6.3.1 Framing
    • 6.3.2 Debugging Aids
  • 6.4 MNP�4/ARAP Protocol Processing
    • 6.4.1 Framing
      • Table 12. Special Character Definition
    • 6.4.2 MNP�4/ARAP FCS (Frame Check Sequence) Calculation
      • Figure 17. ARAP 1.0 Frame
      • Figure 18. ARAP 2.0 Frame
  • 6.5 Async Processing
    • 6.5.1 Transmitter In-Band Flow Control
      • 6.5.1.1 Receiver In-Band Flow Control
      • 6.5.1.2 Automatic Receive In-Band Flow Control
    • 6.5.2 Out-of-Band Flow Control
      • Table 13. Signal Hookup for Flow Control
    • 6.5.3 Line Break Detection and Generation
      • Table 14. Datastream Transmission Breaks
    • 6.5.4 Special Character Transmission
      • Table 15. SSPC[x] Settings
    • 6.5.5 Special Character Recognition and Special Character Range
    • 6.5.6 Special Character Range
      • Table 16. SCdet Settings
    • 6.5.7 UNIX� Support Features
  • 6.6 Non-8-Bit Data Transfers
    • Figure 19. CD2231 Receive Character Processing
• 7.0 Programming Examples
  • Figure 20. Initialization Sequence for the CD2231
  • 7.1 Global Initialization
  • 7.2 Async Interrupt Setup Example
  • 7.3 HDLC DMA Channel Setup Example
  • 7.4 Receive DMA Interrupt Service Routine
  • 7.5 Transmit Interrupt Service Routine
• 8.0 Detailed Register Descriptions
  • 8.1 Global Registers
    • 8.1.1 Global Firmware Revision Code Register (GFRCR)
    • 8.1.2 Channel Access Register (CAR)
  • 8.2 Option Registers
    • 8.2.1 Channel Mode Register (CMR)
    • 8.2.2 Channel Option Register 1 (COR1)
      • 8.2.2.1 COR1 � HDLC Mode
      • 8.2.2.2 COR1 � Asynchronous Mode
    • 8.2.3 Channel Option Register 2 (COR2)
      • 8.2.3.1 COR2 � HDLC Mode
      • 8.2.3.2 Asynchronous/Async-HDLC/PPP Mode
      • 8.2.3.3 COR2 � MNP4/SLIP Mode
    • 8.2.4 Channel Option Register 3 (COR3) � Async-HDLC/PPP Mode
      • 8.2.4.1 MNP�4 Mode
      • 8.2.4.2 HDLC Mode
      • 8.2.4.3 SLIP Mode
      • 8.2.4.4 Asynchronous Mode
    • 8.2.5 Channel Option Register 4 (COR4)
    • 8.2.6 Channel Option Register 5 (COR5)
    • 8.2.7 Channel Option Register 6 (COR6) � Async Mode Only
    • 8.2.8 Channel Option Register 7 (COR7) � Async Mode Only
    • 8.2.9 Special Character Registers � Async Modes Only
      • 8.2.9.1 Special Character Register 1 (SCHR1)
      • 8.2.9.2 Special Character Register 2 (SCHR2)
      • 8.2.9.3 Special Character Register 3 (SCHR3)
      • 8.2.9.4 Special Character Register 4 (SCHR4)
    • 8.2.10 Special Character Range � Async Mode Only
      • 8.2.10.1 Special Character Range low (SCRl)
      • 8.2.10.2 Special Character Range high (SCRh)
    • 8.2.11 LNext Character (LNXT) � Async Mode Only
    • 8.2.12 Receive Frame Address Registers � HDLC Sync Mode Only
      • 8.2.12.1 Receive Frame Address Register 1 (RFAR1)
      • 8.2.12.2 Receive Frame Address Register 2 (RFAR2)
      • 8.2.12.3 Receive Frame Address Register 3 (RFAR3)
      • 8.2.12.4 Receive Frame Address Register 4 (RFAR4)
    • 8.2.13 CRC Polynomial Select Register (CPSR)
    • 8.2.14 Transmit Special Mapped Characters � PPP Mode only
      • 8.2.14.1 Transmit Special Mapped Character 1 (TSPMAP1)
      • 8.2.14.2 Transmit Special Mapped Character 2 (TSPMAP2)
      • 8.2.14.3 Transmit Special Mapped Character 3 (TSPMAP3)
    • 8.2.15 Transmit Async Control Character Maps � PPP Mode Only
      • 8.2.15.1 Transmit Async Control Character Map 0 (TXACCM0)
      • 8.2.15.2 Transmit Async Control Character Map 1 (TXACCM1)
      • 8.2.15.3 Transmit Async Control Character Map 2 (TXACCM2)
      • 8.2.15.4 Transmit Async Control Character Map 3 (TXACCM3)
    • 8.2.16 Receive Async Control Character Maps � PPP Mode Only
      • 8.2.16.1 Receive Async Control Character Map 0 (RXACCM0)
      • 8.2.16.2 Receive Async Control Character Map 1 (RXACCM1)
      • 8.2.16.3 Receive Async Control Character Map 2 (RXACCM2)
      • 8.2.16.4 Receive Async Control Character Map 3 (RXACCM3)
  • 8.3 Bit Rate and Clock Option Registers
    • 8.3.1 Receive Baud Rate Generator Registers
      • 8.3.1.1 Receive Baud Rate Period Register (RBPR)
      • 8.3.1.2 Receive Clock Option Register (RCOR)
    • 8.3.2 Transmit Baud Rate Generator Registers
      • 8.3.2.1 Transmit Baud Rate Period Register (TBPR)
      • 8.3.2.2 Transmit Clock Option Register (TCOR)
  • 8.4 Channel Command and Status Registers
    • 8.4.1 Channel Command Register (CCR)
      • 8.4.1.1 CCR � Mode 1
      • 8.4.1.2 CCR Mode 2
    • 8.4.2 Special Transmit Command Register (STCR)
      • 8.4.2.1 Async-HDLC/PPP Mode
      • 8.4.2.2 SLIP/MNP�4 Mode
      • 8.4.2.3 Async and HDLC Modes
    • 8.4.3 Channel Status Register (CSR)
      • 8.4.3.1 CSR � HDLC Mode
      • 8.4.3.2 CSR � Async Mode
      • 8.4.3.3 Async-HDLC/PPP Mode
      • 8.4.3.4 SLIP/MNP�4 Mode
    • 8.4.4 Modem Signal Value Registers (MSVR)
      • 8.4.4.1 Modem Signal Value Register (MSVR-RTS)
      • 8.4.4.2 Modem Signal Value Register (MSVR-DTR)
  • 8.5 Interrupt Registers
    • 8.5.1 General Interrupt Registers
      • 8.5.1.1 Local Interrupt Vector Register (LIVR)
      • 8.5.1.2 Interrupt Enable Register (IER), Non-PPP Modes
      • 8.5.1.3 Interrupt Enable Register (IER), PPP Mode
      • 8.5.1.4 Local Interrupting Channel Register (LICR)
      • 8.5.1.5 Interrupt Stack Register (STK)
    • 8.5.2 Receive Interrupt Registers
      • 8.5.2.1 Receive Priority Interrupt Level Register (RPILR)
      • 8.5.2.2 Receive Interrupt Register (RIR)
      • 8.5.2.3 Receive Interrupt Status Register (RISR
      • 8.5.2.4 Receive Interrupt Status Register high (RISRh)
      • 8.5.2.5 Receive FIFO Output Count (RFOC)
      • 8.5.2.6 Receive Data Register (RDR)
      • 8.5.2.7 Receive End of Interrupt Register (REOIR)
    • 8.5.3 Transmit Interrupt Registers
      • 8.5.3.1 Transmit Priority Interrupt Level Register (TPILR)
      • 8.5.3.2 Transmit Interrupt Register (TIR)
      • 8.5.3.3 Transmit Interrupt Status Register (TISR)
      • 8.5.3.4 Transmit FIFO Transfer Count (TFTC)
      • 8.5.3.5 Transmit Data Register (TDR)
      • 8.5.3.6 Transmit End of Interrupt Register (TEOIR)
    • 8.5.4 Modem Interrupt Registers
      • 8.5.4.1 Modem Priority Interrupt Level Register (MPILR)
      • 8.5.4.2 Modem Interrupt Register (MIR)
      • 8.5.4.3 Modem (/Timer) Interrupt Status Register (MISR)
      • 8.5.4.4 Modem End of Interrupt Register (MEOIR)
  • 8.6 DMA Registers
    • 8.6.1 DMA Mode Register (DMR)
    • 8.6.2 Bus Error Retry Count (BERCNT)
    • 8.6.3 DMA Buffer Status (DMABSTS)
    • 8.6.4 DMA Receive Registers
      • 8.6.4.1 A Receive Buffer Address Register � Lower (ARBADRL)
      • 8.6.4.2 A Receive Buffer Address Register � Upper (ARBADRU)
      • 8.6.4.3 B Receive Buffer Address Register � Lower (BRBADRL)
      • 8.6.4.4 B Receive Buffer Address Register � Upper (BRBADRU)
      • 8.6.4.5 A Buffer Receive Byte Count (ARBCNT)
      • 8.6.4.6 B Buffer Receive Byte Count (BRBCNT)
      • 8.6.4.7 A Receive Buffer Status (ARBSTS)
      • 8.6.4.8 B Receive Buffer Status (BRBSTS)
      • 8.6.4.9 Receive Current Buffer Address Register � Lower (RCBADRL)
      • 8.6.4.10 Receive Current Buffer Address Register � Upper (RCBADRU)
    • 8.6.5 DMA Transmit Registers
      • 8.6.5.1 A Transmit Buffer Address Register � Lower (ATBADRL)
      • 8.6.5.2 A Transmit Buffer Address Register � Upper (ATBADRU)
      • 8.6.5.3 B Transmit Buffer Address Register � Lower (BTBADRL)
      • 8.6.5.4 B Transmit Buffer Address Register � Upper (BTBADRU)
      • 8.6.5.5 A Buffer Transmit Byte Count (ATBCNT)
      • 8.6.5.6 B Buffer Transmit Byte Count (BTBCNT)
      • 8.6.5.7 A Transmit Buffer Status (ATBSTS) � Async-HDLC/PPP Mode
      • 8.6.5.8 A Transmit Buffer Status (ATBSTS) � SLIP/MNP�4 Mode
      • 8.6.5.9 B Transmit Buffer Status (BTBSTS) � SLIP/MNP�4 Mode
      • 8.6.5.10 A Transmit Buffer Status (ATBSTS) � HDLC Mode
      • 8.6.5.11 B Transmit Buffer Status (BTBSTS) � HDLC Mode
      • 8.6.5.12 A Transmit Buffer Status (ATBSTS) � Async Mode
      • 8.6.5.13 B Transmit Buffer Status (BTBSTS) � Async Mode
      • 8.6.5.14 Transmit Current Buffer Address Register � Lower (TCBADRL)
      • 8.6.5.15 Transmit Current Buffer Address Register � Upper (TCBADRU)
  • 8.7 Timer Registers
    • 8.7.1 Timer Period Register (TPR)
    • 8.7.2 Receive Timeout Period Register (RTPR) � Async Mode Only
      • 8.7.2.1 Receive Timeout Period Register low (RTPRl) � Async Mode Only
      • 8.7.2.2 Receive Timeout Period Register high (RTPRh) � Async Mode Only
    • 8.7.3 General Timer 1 (GT1) Sync Modes Only
      • 8.7.3.1 General Timer 1 low (GT1l) Sync Modes Only
      • 8.7.3.2 General Timer 1 high (GT1h) Sync Modes Only
    • 8.7.4 General Timer 2 (GT2) Sync Modes Only
    • 8.7.5 Transmit Timer Register (TTR) Async Modes Only
• 9.0 Electrical Specifications
  • 9.1 Absolute Maximum Ratings
  • 9.2 DC Electrical Characteristics
  • 9.3 AC Electrical Characteristics
    • Figure 21. CLK / BUSCLK / RESET* TIming Relationship
    • Figure 22. Slave Read Cycle Timing
    • Figure 23. Slave Write Cycle Timing
    • Figure 24. Interrupt Acknowledge Cycle Timing
    • Figure 25. Bus Arbitration Cycle Timing
    • Figure 26. Bus Release Timing
    • Figure 27. DMA Read Cycle Timing
    • Figure 28. DMA Write Cycle Timing
• 10.0 Package Specifications
• 11.0 Ordering Information Example
• Index
  • Numerics
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• Bit Index
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