PRODUCT PREVIEW

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995

September 1995

Order Number: 290539-002

Intel SmartVoltage Technology

5V or 12V Program/Erase

2.7V, 3.3V or 5V Read Operation

Program Time Reduced 60% at

12V V

Very High Performance Read

5V: 70/120 ns Max. Access Time,

30/40 ns Max. Output Enable Time

3V: 120/150 ns Max Access

65 ns Max. Output Enable Time

2.7V: 120 ns Max Access

65 ns Max. Output Enable Time

Low Power Consumption

Max 60 mA Read Current at 5V

Max 30 mA Read Current at 2.73.6V

x8/x16-Selectable Input/Output Bus

28F800 for High Performance 16- or

32-bit CPUs

x8-Only Input/Output Architecture

28F008B for Space-Constrained

8-bit Applications

Optimized Array Blocking Architecture

One 16-KB Protected Boot Block

Two 8-KB Parameter Blocks

One 96-KB Main Block

Seven 128-KB Main Blocks

Top or Bottom Boot Locations

Absolute Hardware-Protection for Boot

Block
Software EEPROM Emulation with

Parameter Blocks

Extended Temperature Operation

40°C to +85°C

Extended Cycling Capability

100,000 Block Erase Cycles

(Commercial Temperature)

10,000 Block Erase Cycles

(Extended Temperature)

Automated Word/Byte Write and Block

Erase

Industry-Standard Command User

Interface

Status Registers

Erase Suspend Capability

SRAM-Compatible Write Interface
Automatic Power Savings Feature

1 mA Typical I

Active Current in

Static Operation

Reset/Deep Power-Down Input

0.2 µA I

Typical

Provides Reset for Boot Operations

Hardware Data Protection Feature

Erase/Write Lockout during Power

Transitions

Industry-Standard Surface Mount

Packaging

40-Lead TSOP

44-Lead PSOP: JEDEC ROM

Compatible

48-Lead TSOP

Footprint Upgradeable from 2-Mbit and

4-Mbit Boot Block Flash Memories
ETOXTM IV Flash Technology

8-MBIT (512K X 16, 1024K X 8)

SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B

28F800CE-T/B, 28F008BE-T/B

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PRODUCT PREVIEW

CONTENTS

PAGE

1.0 PRODUCT FAMILY OVERVIEW . 3

1.1 New Features in the

SmartVoltage Products.....................3

1.2 Main Features................................... 4
1.3 Applications ..................................... 7
1.4 Pinouts..............................................8
1.5 Pin Descriptions.............................10

2.0 PRODUCT DESCRIPTION ........... 13

2.1 Memory Organization....................13

2.1.1 Blocking................................... 13

3.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION............................. 12

3.1 Bus Operations...............................16
3.2 Read Operations.............................16

3.2.1 Read Array...............................16
3.2.2 Intelligent Identifiers................14

3.3 Write Operations............................19

3.3.1 Command User Interface..........19
3.3.2 Status Register..........................17
3.3.3 Program Mode..........................18
3.3.4 Erase Mode ..............................27

3.4 Boot Block Locking.......................19

3.4.1 V

= V

for Complete

Protection.................................. 28

3.4.2 WP# = V

for Boot Block

Locking..................................... 28

3.4.3 RP# = V

or WP# = V

for

Boot Block Unlocking..............29

3.5 Power Consumption....................... 33

3.5.1 Active Power............................33
3.5.2 Automatic Power Savings........ 33
3.5.3 Standby Power......................... 33
3.5.4 Deep Power-Down Mode......... 33

3.6 Power-Up/Down Operation............ 34

3.6.1 RP# Connected to System Reset34
3.6.2 V

, V

and RP# Transtions... 34

3.7 Power Supply Decoupling.............. 34

3.7.1 V

Trace on Printed Circuit

Boards ...................................... 35

4.0 ABSOLUTE MAXIMUM RATINGS 36
5.0 COMMERCIAL OPERATING

CONDITIONS ................................. 37

5.1 Applying V

Voltages .................. 37

5.2 DC Characteristics.......................... 38
5.3 AC Characteristics.......................... 32

6.0 EXTENDED OPERATING

CONDITIONS ................................. 57

6.1 Applying V

Voltages .................. 57

6.2 DC Characteristics.......................... 58
6.3 AC Characteristics.......................... 67

7.0 ADDITIONAL INFORMATION ... 75

7.1 Ordering Information..................... 75
7.2 References...................................... 77
7.3 Revision History............................77

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PRODUCT PREVIEW

1.0

PRODUCT FAMILY

OVERVIEW

This datasheet contains the specifications
for the two branches of products in the
SmartVoltage 8-Mbit boot block flash
memory family: the -BE/CE suffix
products feature a low V

operating range

of 2.73.6V; the -BV/CV suffix products
offer
3.03.6V operation. Both BE/CE and
BV/CV products also operate at 5V for
high-speed access times. Throughout this
datasheet, the 28F800 refers to all x8/x16
8-Mbit products, while 28F008B refers to
all x8 8-Mbit boot block products (but not
to the 28F008SA FlashFileTM Memory).
Also, the term "2.7V" generally means the
full voltage range 2.73.6V. Section 1
provides an overview of the flash memory
family including applications, pinouts and
pin descriptions. Sections 2 and 3 describe
the memory organization and operation for
these products. Finally, Sections 4, 5 and 6
contain the family's operating
specifications.

1.1

New Features in the

SmartVoltage Products

The new 8-Mbit SmartVoltage boot block
flash memory family provides a
convenient density upgrade path from the
2-Mbit and 4-Mbit boot block products.
The 8-Mbit boot block functions similarly
to lower density boot block products in
both command sets and operation,
providing similar pinouts to ease density
upgrades.

To upgrade from lower density -BX/BL-
suffix 12V program products, please note
the following differences and guidelines:

WP# pin has replaced DU (Don't Use)
pin #12 in the 40-lead TSOP package.
In the 44-lead PSOP, DU pin #2 is
replaced with A

(see Figure 1 and

Section 3.4 for details). Connect the
WP# pin to control signal or to V

GND (in this case, a logic-level signal
can be placed on DU pin #12 for 40-
lead TSOP). See Tables 2 and 9 to see
how the WP# pin works.

5V program/erase operation has been
added. If switching V

for write

protection, switch to GND (not 5V) for
complete write protection. To take
advantage of 5V write-capability, allow
for connecting 5V to V

and

disconnecting 12V from V

line.

Enhanced circuits optimize low V

performance, allowing operation down
to V

= 2.7V (using the BE/CE

products).

To upgrade from lower density
SmartVoltage boot block products, the
similar pinouts in the 40-lead and 48-lead
TSOP packages provide easy upgrades by
adding extra address lines (see Figures 1
and 3). In the 44-lead TSOP, the WP# pin
on the 2-Mbit and 4-Mbit BV parts
becomes A

, removing the capability to

unlock the boot block with a logic-level
signal in this package only. The boot block
can still be unlocked with 12V on RP# (see
Figure 2 and Section 3.4 for details).

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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1.2

Main Features

Intel's SmartVoltage technology is the most
flexible voltage solution in the flash
industry, providing two discrete voltage
supply pins: V

for read operation, and V

for program and erase operation. Discrete
supply pins allow system designers to use
the optimal voltage levels for their design.
All products (28F800BV/CV, 28F008BV,
28F800CE and 28F008BE) provide
program/erase capability at 5V or 12V. The
28F800BV/CV and 28F008BV allows reads
with V

at 3.3

0.3V or 5V, while the

28F800CE and 28F008BE allows reads
with V

at 2.73.6V or 5V. Since many

designs read from the flash memory a large
percentage of the time, 2.7V V

operation

can provide great power savings. If read
performance is an issue, however, 5V V

provides faster read access times. For
program and erase operations, 5V V

operation eliminates the need for in system
voltage converters, while 12V V

operation

provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is in-
system. For design simplicity, however, just
hook up V

and V

to the same 5V ± 10%

source.
The 28F800/28F008B boot block flash
memory family is a high-performance,
8-Mbit (8,388,608 bit) flash memory family
organized as either
512 Kwords of 16 bits each (28F800 only)
or
1024 Kbytes of 8 bits each (28F800 and
28F008B).
Separately erasable blocks, including a
hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes
each) and main blocks (one block of 98,304
bytes and seven blocks of 131,072 bytes)
define the boot block flash family

architecture. See Figures 4 and 5 for
memory maps. Each block can be
independently erased and programmed
100,000 times at commercial temperature or
10,000 times at extended temperature.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to
accommodate different microprocessor
protocols for boot code location. The
hardware-lockable boot block provides
complete code security for the kernel code
required for system initialization. Locking
and unlocking of the boot block is
controlled by WP# and/or RP# (see Section
3.4 for details).

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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The Command User Interface (CUI) serves
as the interface between the microprocessor
or microcontroller and the internal
operation of the boot block flash memory
products. The internal Write State Machine
(WSM) automatically executes the
algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the
status of the WSM and whether it
successfully completed the desired program
or erase operation.
Program and erase automation allows
program and erase operations to be
executed using an industry-standard two-
write command sequence to the CUI. Data
writes are performed in word (28F800
family) or byte (28F800 or 28F008B
families) increments. Each byte or word in
the flash memory can be programmed
independently of other memory locations,
unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash
memory family is also designed with an
Automatic Power Savings (APS) feature
which minimizes system battery current
drain, allowing for very low power designs.
To provide even greater power savings, the
boot block family includes a deep power-
down mode which minimizes power
consumption by turning most of the flash
memory's circuitry off. This mode is
controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides
protection against unwanted command
writes due to invalid system bus conditions
that may occur during system reset and
power-up/down sequences. For example,

when the flash memory powers-up, it
automatically defaults to the read array
mode, but during a warm system reset,
where power continues uninterrupted to the
system components, the flash memory
could remain in a non-read mode, such as
erase. Consequently, the system Reset
signal should be tied to RP# to reset the
memory to normal read mode upon
activation of the Reset signal (see Section
3.6).

The 28F800 provides both byte-wide or
word-wide input/output, which is
controlled by the BYTE# pin. Please see
Table 2 and Figure 13 for a detailed
description of BYTE# operations,
especially the usage of the

pin.

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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The 28F800 products are available in the
44-lead PSOP (Plastic Small Outline)
package (a ROM/EPROM-compatible
pinout) and the 48-lead TSOP (Thin Small
Outline, 1.2 mm thick) package as shown in
Figures 2, and 3, respectively. The 28F800
is not available in 56-lead TSOP. The
28F008B products are available in the 40-
lead TSOP package as shown in Figure 1.

Refer to the DC Characteristics Table,
Section 5.2 (commercial temperature)
and Section 6.2 (extended temperature),
for complete current and voltage
specifications. Refer to the AC
Characteristics Table, Section 5.3
(commercial temperature) and Section
6.3 (extended temperature), for read,
write and erase performance
specifications.

1.3

Applications

The 8-Mbit boot block flash memory family
combines high-density, low-power, high-
performance, cost-effective flash memories
with blocking and hardware protection
capabilities. Their flexibility and versatility
reduce costs throughout the product life
cycle. Flash memory is ideal for just-in-
time production flow, reducing system
inventory and costs, and eliminating
component handling during the production
phase.
When your product is in the end-user's
hands, and updates or feature enhancements
become necessary, flash memory reduces
the update costs by allowing user-
performed code changes instead of costly
product returns or technician calls.

The 8-Mbit boot block flash memory family
provides full-function, blocked flash
memories suitable for a wide range of
applications. These applications include
ROM-able applications storage, digital
cellular phone program and data storage,
telecommunication boot/firmware, printer
firmware/font storage and various other
embedded applications where program and
data storage are required.
The 8-Mbit flash memory products are also
excellent design solutions for digital
cellular phone and telecommunication
switching applications requiring very low
power consumption, high-performance,
high-density storage capability, modular
software designs, and a small form factor
package. The 8-Mbit's blocking scheme
allows for easy segmentation of the
embedded code with
16 Kbytes of hardware-protected boot code,
eight main blocks of program code and two
parameter blocks of 8 Kbytes each for
frequently updated data storage and
diagnostic messages (e.g., phone numbers,
authorization codes).
Intel's boot block architecture provides a
flexible solution for the different design
needs of various applications. The
asymmetrically-blocked memory map
allows the integration of several memory
components into a single flash device. The
boot block provides a secure boot PROM;
the parameter blocks can emulate EEPROM
functionality for parameter store with
proper software techniques; and the main
blocks provide code and data storage with
access times fast enough to execute code in
place, decreasing RAM requirements.

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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1.4

Pinouts

Intel's SmartVoltage Boot Block
architecture provides pinout upgrade paths
to the 8-Mbit density. 8-Mbit pinouts are
given on the chip illustration in the center,
with 2-Mbit and 4-Mbit pinouts going
outward from the center for reference.

The 28F008B 40-lead TSOP pinout for
space-constrained designs is shown in
Figure 1. For designs that require x16
operation but have space concerns, refer to
the 48-lead pinout in Figure 3. The 28F800
44-lead PSOP pinout follows the industry-
standard ROM/EPROM pinout, as shown in
Figure 2.

28F008B

40-LEAD TSOP

Boot Block

10 mm x 20 mm

TOP VIEW

32
31
30
29
28

27
26

25
24

23
22
21

17
18

1
2
3
4
5

6
7

8
9

10
11
12
13

RP#

WE#

W P#

28F004B

RP#

WE#

WP#

CE#

OE#
GND

GND

CE#

OE#
GND

GND

28F002B

RP#

WE#

A16

A15

A14

A13

A11

A12

WP#

A18

DQ7

CE#

OE#
GND

DQ6

DQ5

DQ4

DQ2

DQ1

DQ0

VCC

DQ3

A17

GND

A10

VCC

A19

0539_01

NOTE:
1. Pin 12 is DU for -BX/BL 12V V

Versions.

2. The 28F008B pinout is for the 8-Mbit boot block and not for the 28F008SA FlashFileTM Memory.

Figure 1. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained

Applications

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PRODUCT PREVIEW

CE#

GND

OE#

CE#

WP#

GND

OE#

PA28F800

Boot Block

44-LEAD PSOP

0.525" x 1.110"

TOP VIEW

GND

WE#

RP#

BYTE#

32
31
30
29
28
27
26
25
24
23

17
18

1
2
3
4
5
6
7
8
9

10
11
12
13
14

CE#

WP#

GND

OE#

GND

WE#

RP#

BYTE#

28F200

-1

28F400

GND

WE#

RP#

BYTE#

28F400

-1

0539_02

NOTE:
Pin 2 is DU for BX/BL 12V V

Versions, but for the 8-Mbit device, pin 2 has been changed to A

(WP# on 2/4 Mbit). Designs

planning on upgrading to the 8-Mbit density from the 2/4-Mbit density in this package should design pin 2 to control WP# functionality

at the 2/4-Mbit level and allow for pin 2 to control A

after upgrading to the 8-Mbit density.

Figure 2. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM

Standards

28F800C

Boot Block

48-LEAD TSOP

12 mm x 20 mm

TOP VIEW

17
18

1
2
3
4
5
6
7
8
9

10
11
12
13
14

RP#

WE#

WP#

CE#

OE#

GND

BYTE#

15/A

-1

DQ14

DQ8

RP#

WE#

WP#

CE#

OE#

GND

BYTE#

15 /A

-1

DQ14

DQ5

DQ12

DQ4
DQ11
DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

DQ3

CE#

OE#

GND

VCC

GND

BYTE#

A16

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4
DQ11
DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

DQ3

28F200

28F400

28F200

28F400

A18

RP#

WE#

A15

A14

A13

A11

A12

VPP

A10

WP#

A17

0539_03

Figure 3. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PRODUCT PREVIEW

1.5

Pin Descriptions

Table 2. 28F800/008B Pin Descriptions

Symbol

Type

Name and Function

INPUT

ADDRESS INPUTS for memory addresses. Addresses are
internally latched during a write cycle. The 28F800 only has
A

pins, while

the 28F008B has A

INPUT

ADDRESS INPUT: When A

is at V

the signature mode is

accessed. During this mode, A

decodes between the

manufacturer and device IDs. When BYTE# is at a logic low,
only the lower byte of the signatures are read. DQ

is a

don't care in the signature mode when BYTE# is low.

INPUT/OUT

PUT

DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Inputs
commands to the Command User Interface when CE# and
WE# are active. Data is internally latched during the Write
cycle. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-
selected or the outputs are disabled.

INPUT/OUT

PUT

DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Data is
internally latched during the Write cycle. Outputs array data.
The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# =
"0"). In the byte-wide mode DQ

becomes the lowest

order address for data output on DQ

. The 28F008B

does not include these DQ

DQ

pins.

CE#

INPUT

CHIP ENABLE: Activates the device's control logic, input
buffers, decoders and sense amplifiers. CE# is active low.
CE# high de-selects the memory device and reduces power
consumption to standby levels. If CE# and RP# are high, but
not at a CMOS high level, the standby current will increase
due to current flow through the CE# and RP# input stages.

OE#

INPUT

OUTPUT ENABLE: Enables the device's outputs through
the data buffers during a read cycle. OE# is active low.

WE#

INPUT

WRITE ENABLE: Controls writes to the Command Register
and array blocks. WE# is active low. Addresses and data are
latched on the rising edge of the WE# pulse.

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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RP#

INPUT

RESET/DEEP POWER-DOWN: Uses three voltage levels
(V

, V

, and V

) to control two different functions:

reset/deep power-down mode and boot block unlocking. It is
backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep
power-down mode, which puts the outputs at High-Z, resets
the Write State Machine, and draws minimum current.

When RP# is at logic high, the device is in standard
operation. When RP# transitions from logic-low to logic-
high, the device defaults to the read array mode.

When RP# is at V

, the boot block is unlocked and can be

programmed or erased. This overrides any control from the
WP# input.

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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Table 2. 28F800/008B Pin Descriptions (Continued)

Symbol

Type

Name and Function

WP#

INPUT

WRITE PROTECT: Provides a method for unlocking the
boot block in a system without a 12V supply.

When WP# is at logic low, the boot block is locked ,
preventing program and erase operations to the boot block. If
a program or erase operation is attempted on the boot block
when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to
indicate the operation failed.

When WP# is at logic high, the boot block is unlocked and
can be programmed or erased.

NOTE: This feature is overridden and the boot block
unlocked when RP# is at V

. This pin is not available on the

44-lead PSOP package. See Section 3.4 for details on write
protection.

BYTE#

INPUT

BYTE# ENABLE: Not available on 28F008B. Controls
whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# pin must be controlled at
CMOS levels to meet the CMOS current specification in the
standby mode.

When BYTE# is at logic low, the byte-wide mode is
enabled, where data is read and programmed on DQ

and DQ

becomes the lowest order address that decodes

between the upper and lower byte. DQ

are tri-stated

during the byte-wide mode.

When BYTE# is at logic high, the word-wide mode is
enabled, where data is read and programmed on DQ

DEVICE POWER SUPPLY: 5.0V

10%, 3.3V

0.3V,

2.7V3.6V

PROGRAM/ERASE POWER SUPPLY: For erasing
memory array blocks or programming data in each block, a
voltage either of 5V

10% or 12V

5% must be applied to

this pin. When V

< V

PPLK

all blocks are locked and

protected against Program and Erase commands.

GND

GROUND: For all internal circuitry.

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NO CONNECT: Pin may be driven or left floating.

2.0

PRODUCT DESCRIPTION

2.1

Memory Organization

2.1.1

BLOCKING

This product family features an
asymmetrically- blocked architecture
providing system memory integration. Each
erase block can be erased independently of
the others up to 100,000 times for
commercial temperature or up to 10,000
times for extended temperature. The block
sizes have been chosen to optimize their
functionality for common applications of
nonvolatile storage. The combination of
block sizes in the boot block architecture
allow the integration of several memories
into a single chip. For the address locations
of the blocks, see the memory maps in
Figures 4 and 5.

2.1.1.1

Boot Block - 1 x 16 KB

The boot block is intended to replace a
dedicated boot PROM in a microprocessor
or microcontroller-based system. The 16-
Kbyte (16,384 bytes) boot block is located
at either the top (denoted by -T suffix) or
the bottom (-B suffix) of the address map to
accommodate different microprocessor
protocols for boot code location. This boot
block features hardware controllable write-
protection to protect the crucial
microprocessor boot code from accidental
modification. The protection of the boot
block is controlled using a combination of
the V

, RP#, and WP# pins, as is detailed

in Section 3.4.

2.1.1.2

Parameter Blocks - 2 x 8 KB

The boot block architecture includes
parameter blocks to facilitate storage of
frequently updated small parameters that
would normally require an EEPROM. By
using software techniques, the byte-rewrite
functionality of EEPROMs can be
emulated. These techniques are detailed in
Intel's AP-604,

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"Using Intel's Boot Block Flash Memory
Parameter Blocks to Replace EEPROM."
Each boot block component contains two
parameter blocks of
8 Kbytes (8,192 bytes) each. The parameter
blocks are not write-protectable.

2.1.1.3

Main Blocks - 1 x 96 KB + 7 x

128 KB

After the allocation of address space to the
boot and parameter blocks, the remainder is
divided into main blocks for data or code
storage. Each 8-Mbit device contains one
96-Kbyte (98,304 byte) block and seven
128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more
information.

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

7FFFFH

70000H

6FFFFH

60000H

5FFFFH

50000H

4FFFFH

40000H

3FFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

28F800-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

00000H

0FFFFH

10000H

1FFFFH

20000H

2FFFFH

30000H

3FFFFH

40000H

4FFFFH

50000H

5FFFFH

60000H

6FFFFH

70000H

7BFFFH

7C000H

7CFFFH

7D000H

7DFFFH

7E000H

7FFFFH

28F800-T

0539_04

NOTE:
In x8 operation, the least significant system address should be connected to A

. Memory maps are shown for x16 operation.

Figure 4. Word-Wide x16-Mode Memory Maps

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28F800-T

28F800-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

00000H

1FFFFH

20000H

3FFFFH

40000H

5FFFFH

60000H

7FFFFH

80000H

9FFFFH

A0000H

BFFFFH

C0000H

DFFFFH

E0000H

F7FFFH

F8000H

F9FFFH

FA000H

FBFFFH

FC000H

FFFFFH

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

FFFFFH

E0000H

DFFFFH

C0000H

BFFFFH

A0000H

9FFFFH

80000H

7FFFFH

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

0539_05

NOTE:
These memory maps apply to the 28F008B or the 28F800 (in x8 mode).

Figure 5. Byte-Wide x8-Mode Memory Maps

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3.0

PRODUCT FAMILY

PRINCIPLES OF OPERATION

Flash memory combines EPROM
functionality with in-circuit electrical write
and erase. The boot block flash family
utilizes a Command User Interface (CUI)
and automated algorithms to simplify write
and erase operations. The CUI allows for
100% TTL-level control inputs, fixed power
supplies during erasure and programming,
and maximum EPROM compatibility.
When V

< V

PPLK

, the device will only

successfully execute the following
commands: Read Array, Read Status
Register, Clear Status Register and
intelligent identifier mode. The device
provides standard EPROM read, standby
and output disable operations. Manufacturer
identification and device identification data
can be accessed through the CUI or through
the standard EPROM A

high voltage

access (V

) for PROM programming

equipment.
The same EPROM read, standby and output
disable functions are available when 5V or
12V is applied to the V

pin. In addition,

5V or 12V on V

allows write and erase of

the device. All functions associated with
altering memory contents: Program and
Erase, Intelligent Identifier Read, and Read
Status are accessed via the CUI.
The internal Write State Machine (WSM)
completely automates program and erase,
beginning operation signaled by the CUI
and reporting status through the Status
Register. The CUI handles the WE#
interface to the data and address latches, as
well as system status requests during WSM
operation.

3.1

Bus Operations

Flash memory reads, erases and writes in-
system via the local CPU. All bus cycles to
or from the flash memory conform to
standard microprocessor bus cycles. These
bus operations are summarized in Tables 3
and 4.

3.2

Read Operations

3.2.1

READ ARRAY

When RP# transitions from V

(reset) to

, the device will be in the read array

mode and will respond to the read control
inputs (CE#, address inputs, and OE#)
without any commands being written to the
CUI.
When the device is in the read array mode,
five control signals must be controlled to
obtain data at the outputs.

WE# must be logic high (V

)

CE# must be logic low (V

)

OE must be logic low (V

)

RP# must be logic high (V

)

BYTE# must be logic high or logic low.

In addition, the address of the desired
location must be applied to the address
pins. Refer to Figures 12 and 13 for the
exact sequence and timing of these signals.
If the device is not in read array mode, as
would be the case after a program or erase
operation, the Read Mode command (FFH)
must be written to the CUI before reads can
take place.

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Table 3. Bus Operations for Word-Wide Mode (BYTE# = V

)

Mode

Note

RP#

CE# OE# WE#

015

Read

1,2,3

OUT

Output Disable

High Z

Standby

High Z

Deep Power-
Down

High Z

Intelligent
Identifier (Mfr.)

0089 H

Intelligent
Identifier
(Device)

4,5

See

Table 5

Write

6,7,8

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Table 4. Bus Operations for Byte-Wide Mode (BYTE# = V

)

Mode

Note

RP# CE# OE

07

Read

1,2,3

OUT

High

Output
Disable

High

Standby

High

Deep
Power-
Down

High

Intelligent
Identifier
(Mfr.)

89H

High

Intelligent
Identifier
(Device)

4,5

See

Table

High

Write

6,7,8

High

NOTES:
1.

Refer to DC Characteristics.

X can be V

, V

for control pins and addresses, V

PPLK

or V

PPH

for V

See DC Characteristics for V

PPLK

, V

PPH

1, V

PPH

2, V

, V

voltages

Manufacturer and device codes may also be accessed via a CUI write sequence, A

= X, A

= X.

See Table 5 for device IDs.

Refer to Table 7 for valid D

during a write operation.

Command writes for Block Erase or Word/Byte Write are only executed when V

= V

PPH

1 or V

PPH

To write or erase the boot block, hold RP# at V

or WP# at V

. See Section 3.4.

RP# must be at GND

0.2V to meet the maximum deep power-down current specified.

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3.2.2

INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes,
the device must be in intelligent identifier
read mode, which can be reached using two
methods: by writing the intelligent identifier
command (90H) or by taking the A

pin to

. Once in intelligent identifier read

mode, A

= 0 outputs the manufacturer's

identification code and A

= 1 outputs the

device code. In byte-wide mode, only the
lower byte of the above signatures is read
(DQ

is a "don't care" in this mode).

See Table 5 for product signatures. To
return to read array mode, write a Read
Array command (FFH).

Table 5. Intelligent Identifier Table

Produc

Mfr.

Device ID

-T

(Top

Boot)

-B

(Bottom

Boot)

28F800

0089

889C H

889D H

28F008

89 H

9C H

9D H

3.3

Write Operations

3.3.1

COMMAND USER

INTERFACE (CUI)

The Command User Interface (CUI) is the
interface between the microprocessor and
the internal chip controller. Commands are
written to the CUI using standard
microprocessor write timings. The available
commands are Read Array, Read Intelligent
Identifier, Read Status Register, Clear
Status Register, Erase and Program
(summarized in Tables 6 and 7). The three
read modes are read array, intelligent
identifier read, and Status Register read. For
Program or Erase commands, the CUI
informs the Write State Machine (WSM)
that a write or erase has been requested.
During the execution of a Program
command, the WSM will control the
programming sequences and the CUI will
only respond to status reads. During an
erase cycle, the CUI will respond to status
reads and erase suspend. After the WSM
has completed its task, it will set the WSM
Status bit to a "1" (ready), which indicates
that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will
stay in the current command state until it
receives another command.

3.3.1.1

Command Function

Description

Device operations are selected by writing
specific commands into the CUI. Tables 6
and 7 define the available commands.

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Table 6. Command Codes and Descriptions

Code Device Mode

Description

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the
right to redefine these codes for future functions.

Read Array/

Program or

Erase Abort

Places the device in read array mode, so that array data will be
output on the data pins. This command can also be used to cancel
erase and program sequences after their set-up commands have been
issued. To cancel after issuing an Erase Set-Up command, issue this
command, which will reset to read array mode. To cancel a program
operation after issuing a Program Set-Up command, issue two Read
Array commands in sequence to reset to read array mode. If a
program or erase operation has already been initiated to the WSM
this command can not cancel that operation in progress.

Program

Set-Up

Sets the CUI into a state such that the next write will load the
Address and Data registers. After this command is executed, the
outputs default to the Status Register. A two Read Array command
sequence (FFH) is required to reset to Read Array after the Program
Set-Up command.

The second write after the Program Set-Up command will latch
addresses and data, initiating the WSM to begin execution of the
program algorithm. The device outputs Status Register data when
OE# is enabled. A Read Array command is required after
programming, to read array data. See Section 3.3.3.

Alternate

Program Set-

(See 40H/Program Set-Up)

Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will set
both the Program Status and Erase Status bits of the Status Register
to a "1," place the device into the read Status Register state, and
wait for another command. See Section 3.3.4.

Erase

Resume/

Erase

Confirm

If the previous command was an Erase Set-Up command, then the
CUI will close the address and data latches, and begin erasing the
block indicated on the address pins. During erase, the device will
respond only to the Read Status Register and Erase Suspend
commands and will output Status Register data when OE# is
toggled low. Status Register data can be updated by toggling either

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Table 6. Command Codes and Descriptions

Code Device Mode

Description

OE# or CE# low.

Erase

Suspend

Valid only while an erase operation is in progress and will be
ignored in any other circumstance. Issuing this command will begin
to suspend erase operation. The Status Register will indicate when
the device reaches erase suspend mode. In this mode, the CUI will
respond only to the Read Array, Read Status Register, and Erase
Resume commands and the WSM will also set the WSM Status bit
to a "1" (ready). The WSM will continue to idle in the SUSPEND
state, regardless of the state of all input control pins except RP#,
which will immediately shut down the WSM and the remainder of
the chip, if it is made active. During a suspend operation, the data
and address latches will remain closed, but the address pads are able
to drive the address into the read path. See Section 3.3.4.1.

Read Status

Puts the device into the read Status Register mode, so that reading
the device will output the contents of the Status Register, regardless
of the address presented to the device. The device automatically
enters this mode after program or erase has completed. This is one
of the two commands that is executable while the WSM is
operating. See Section 3.3.2.

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Table 6. Command Codes and Descriptions (Continued)

Code Device Mode

Description

Clear Status

The WSM can only set the Program Status and Erase Status bits in
the Status Register to "1," it cannot clear them to "0."

The Status Register operates in this fashion for two reasons. The
first is to give the host CPU the flexibility to read the status bits at
any time. Second, when programming a string of bytes, a single
Status Register query after programming the string may be more
efficient, since it will return the accumulated error status of the
entire string. See Section 3.3.2.1.

Intelligent

Identifier

Puts the device into the intelligent identifier read mode, so that
reading the device will output the manufacturer and device codes.
(A

= 0 for manufacturer,

= 1 for device, all other address inputs are ignored). See Section

3.2.2.

Table 7. Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Note

Oper

Addr

Data

Oper

Addr

Data

Read Array

Write

FFH

Intelligent Identifier

Write

90H

Read

IID

Read Status Register

2,4

Write

70H

Read

SRD

Clear Status Register

Write

50H

Word/Byte Write

Write

40H

Write

Alternate Word/Byte
Write

6,7

Write

10H

Write

Block Erase/Confirm

6,7

Write

20H

Write

D0H

Erase Suspend/Resume

Write

B0H

Write

D0H

ADDRESS

DATA

BA= Block Address

SRD= Status Register Data

IA= Identifier Address

IID= Identifier Data

WA= Write Address

WD= Write Data

X= Don't Care

NOTES:

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Bus operations are defined in Tables 3 and 4.

IA = Identifier Address: A

= 0 for manufacturer code, A

= 1 for device code.

SRD - Data read from Status Register.

IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device

codes.

BA = Address within the block being erased.

WA = Address to be written. WD = Data to be written at location WD.

Either 40H or 10H commands is valid.

When writing commands to the device, the upper data bus [DQ

] = X (28F800 only) which is either V

or V

, to minimize

current draw.

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Table 8. Status Register Bit Definition

WSMS

ESS

DWS

VPPS

NOTES:

SR.7 WRITE STATE MACHINE
STATUS

1 = Ready

(WSMS)

0 = Busy

Check Write State Machine bit first to
determine Word/Byte program or Block
Erase completion, before checking
Program or Erase Status bits.

SR.6 = ERASE-SUSPEND STATUS
(ESS)

1 = Erase Suspended
0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM
halts execution and sets both WSMS and
ESS bits to "1." ESS bit remains set to "1"
until an Erase Resume command is issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure
0 = Successful Block Erase

When this bit is set to "1," WSM has
applied the max number of erase pulses to
the block and is still unable to verify
successful block erasure.

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program
0 = Successful Byte/Word Program

When this bit is set to "1," WSM has
attempted but failed to program a byte or
word.

SR.3 = V

STATUS (VPPS)

1 = V

Low Detect, Operation

Abort

0 = V

The V

Status bit does not provide

continuous indication of V

level. The

WSM interrogates V

level only after the

Byte Write or Erase command sequences
have been entered, and informs the system
if V

has not been switched on. The V

Status bit is not guaranteed to report
accurate feedback between V

PPLK

and

PPH

SR.2-SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and
should be masked out when polling the
Status Register.

3.3.2

STATUS REGISTER

The device Status Register indicates when a
program or erase operation is complete, and
the success or failure of that operation. To
read the Status Register write the Read

Status (70H) command to the CUI. This
causes all subsequent read operations to
output data from the Status Register until
another command is written to the CUI. To
return to reading from the array, issue a
Read Array (FFH) command.

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The Status Register bits are output on DQ

, in both byte-wide (x8) or word-wide

(x16) mode. In the word-wide mode the
upper byte, DQ

, outputs 00H during

a Read Status command. In the byte-wide
mode, DQ

are tri-stated and DQ

retains the low order address function.

Important: The contents of the Status
Register are latched on the falling edge of
OE# or CE#, whichever occurs last in the
read cycle. This prevents possible bus
errors which might occur if Status Register
contents change while being read. CE# or
OE# must be toggled with each subsequent
status read, or the Status Register will not
indicate completion of a program or erase
operation.
When the WSM is active, the SR.7 register
will indicate the status of the WSM, and
will also hold the bits indicating whether or
not the WSM was successful in performing
the desired operation.

3.3.2.1

Clearing the Status Register

The WSM sets status bits 3 through 7 to
"1," and clears bits 6 and 7 to "0," but
cannot clear status bits 3 through 5 to "0."
Bits 3 through 5 can only be

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cleared by the controlling CPU through the
use of the Clear Status Register (50H)
command, because these bits indicate
various error conditions. By allowing the
system software to control the resetting of
these bits, several operations may be
performed (such as cumulatively
programming several bytes or erasing
multiple blocks in sequence) before reading
the Status Register to determine if an error
occurred during that series. Clear the Status
Register before beginning another
command or sequence. Note, again, that a
Read Array command must be issued
before data can be read from the memory or
intelligent identifier.

3.3.3

PROGRAM MODE

Programming is executed using a two-write
sequence. The Program Setup command is
written to the CUI followed by a second
write which specifies the address and data
to be programmed. The WSM will execute
a sequence of internally timed events to:

1. Program the desired bits of the

addressed memory word or byte.

2. Verify that the desired bits are

sufficiently programmed.

Programming of the memory results in
specific bits within a byte or word being
changed to a "0."
If the user attempts to program "1"s, there
will be no change of the memory cell
content and no error occurs.
The Status Register indicates programming
status: while the program sequence is
executing, bit 7 of the Status Register is a
"0." The Status Register can be polled by
toggling either CE# or OE#. While
programming, the only valid command is
Read Status Register.

When programming is complete, the
Program Status bits should be checked. If
the programming operation was
unsuccessful, bit 4 of the Status Register is
set to a "1" to indicate a Program Failure. If
bit 3 is set to a "1," then V

was not within

acceptable limits, and the WSM did not
execute the programming sequence.

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The Status Register should be cleared
before attempting the next operation. Any
CUI instruction can follow after
programming is completed; however, reads
from the Memory Array or Intelligent
Identifier cannot be accomplished until the
CUI is given the appropriate command.

3.3.4

ERASE MODE

To erase a block, write the Erase Set-Up
and Erase Confirm commands to the CUI,
along with the addresses identifying the
block to be erased. These addresses are
latched internally when the Erase Confirm
command is issued. Block erasure results in
all bits within the block being set to "1."
Only one block can be erased at a time.
The WSM will execute a sequence of
internally timed events to:

1. Program all bits within the block to "0."
2. Verify that all bits within the block are

sufficiently programmed to "0."

3. Erase all bits within the block to "1."
4. Verify that all bits within the block are

sufficiently erased.

While the erase sequence is executing, bit 7
of the Status Register is a "0."
When the Status Register indicates that
erasure is complete, check the Erase Status
bit to verify that the erase operation was
successful. If the Erase operation was
unsuccessful, bit 5 of the Status Register
will be set to a "1," indicating an Erase
Failure. If V

was not within acceptable

limits after the Erase Confirm command is
issued, the WSM will not execute an erase
sequence; instead, bit 5 of the Status
Register is set to a "1" to indicate an Erase
Failure, and bit 3 is set to a "1" to identify
that V

supply voltage was not within

acceptable limits.

Clear the Status Register before attempting
the next operation. Any CUI instruction can
follow after erasure is completed; however,
reads from the Memory Array, Status
Register, or Intelligent Identifier cannot be
accomplished until the CUI is given the
Read Array command.

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3.3.4.1

Suspending and Resuming
Erase

Since an erase operation requires on the
order of seconds to complete, an Erase
Suspend command is provided to allow
erase-sequence interruption in order to read
data from another block of the memory.
Once the erase sequence is started, writing
the Erase Suspend command to the CUI
requests that the WSM pause the erase
sequence at a predetermined point in the
erase algorithm. The Status Register will
indicate if/when the erase operation has
been suspended.
At this point, a Read Array command can
be written to the CUI in order to read data
from blocks other than that which is being
suspended. The only other valid command
at this time is the Erase Resume command
or Read Status Register command.
During erase suspend mode, the chip can go
into a pseudo-standby mode by taking CE#
to V

, which reduces active current draw.

To resume the erase operation, enable the
chip by taking CE# to V

, then issuing the

Erase Resume command, which continues
the erase sequence to completion. As with
the end of a standard erase operation, the
Status Register must be read, cleared, and
the next instruction issued in order to
continue.

3.4

Boot Block Locking

The boot block family architecture features
a hardware-lockable boot block so that the
kernel code for the system can be kept
secure while the parameter and main blocks
are programmed and erased independently
as necessary. Only the boot block can be
locked independently from the other blocks.

3.4.1

= V

FOR COMPLETE

PROTECTION

For complete write protection of all blocks
in the flash device, the V

programming

voltage can be held low. When V

is below

PPLK

, any program or erase operation will

result in a error in the Status Register.

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3.4.2

WP# = V

FOR BOOT BLOCK

LOCKING

When WP# = V

, the boot block is locked

and any program or erase operation to the
boot block will result in an error in the
Status Register. All other blocks remain
unlocked in this condition and can be
programmed or erased normally. Note that
this feature is overridden and the boot block
unlocked when RP# = V

. Since the WP#

pin is not available on the 44-lead PSOP
package, the boot block's default status is
locked when RP# is at V

or V

. For the

44-lead PSOP, the boot block cannot be
unlocked with a logic-level signal; instead,
RP# must be taken to V

as discussed in

Section 3.4.3 below.

3.4.3

RP# = V

OR WP# = V

FOR

BOOT BLOCK UNLOCKING

Two methods can be used to unlock the
boot block:
1. WP# = V

2. RP# = V

If both or either of these two conditions are
met, the boot block will be unlocked and
can be programmed or erased. Since the

WP# pin is not available on the 44-lead
PSOP package, the boot block cannot be
unlocked with a logic-level signal on that
package. Instead, RP# must be taken to
V

The truth table, Table 9, clearly defines the
write protection methods.

Table 9. Write Protection Truth Table for

SmartVoltage Boot Block Family

Write Protection

Provided

All Blocks Locked

PPLK

All Blocks Locked
(Reset)

PPLK

All Blocks
Unlocked

PPLK

Boot Block
Locked

PPLK

All Blocks
Unlocked

NOTE:
WP# pin not available on 44-lead PSOP. In this package, treat as

if the WP# pin is internally tied low, effectively eliminating the

last row of the above table.

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SR.7 = 1

YES

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read

Status Register

V Range Error

Bus

Operation

Standby

Check SR.3

1 = V Low Detect

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are programmed before full
status is checked.

If error is detected, clear the Status Register before attempting
retry or other error recovery.

Bus

Operation

Command

Comments

W rite

Setup

Program

Data = Data to Program
Addr = Location to Program

Read

Data = 40H
Addr = Word/Byte to Program

Check SR.7

1 = WSM Ready
0 = WSM Busy

Repeat for subsequent Word/Byte Writes.
SR Full Status Check can be done after each Word/Byte
Write, or after a sequence of Word/Byte Writes.

Write FFH after the last write operation to reset device to
read array mode.

Standby

SR.3=

SR.4 =

Word/Byte Program

Error

Word/Byte Program

Successful

Check SR.4

1 = V Byte Program Error

Program

Status Register Data

Toggle CE# or OE#

to Update SRD.

Command

Comments

0539_06

Figure 6. Automated Word/Byte Programming Flowchart

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SR.7 =

Start

Write 20H,

Block Address

Write D0H and

Block Address

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read Status

V Range Error

Suspend

Erase

Suspend Erase

Loop

YES

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Block Erase

Error

Bus

Operation

Command

Comments

Standby

Check SR.4,5
Both 1 = Command
Sequence Error

Standby

Check SR.3

1 = V Low Detect

SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Register before attempting
retry or other error recovery.

Check SR.5
1 = Block Erase Error

Standby

Bus

Operation

Command

Comments

W rite

Erase Setup

Read

Data = 20H
Addr = Within Block to be Erased

Check SR.7

1 = WSM Ready
0 = WSM Busy

Repeat for subsequent block erasures.
Full Status Check can be done after each block erase,

or after a sequence of block erasures.
Write FFH after the last operation to reset device to read
array mode.

Status Register Data

Toggle CE# or OE#

to Update Status Register

Standby

Erase

Confirm

Data = D0H

Addr = Within Block to be Erased

Block Erase

Successful

0539_07

Figure 7. Automated Block Erase Flowchart

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SR.7 =

Start

Write B0H

Read

Status Register

Write D0H

Erase Resumed

Bus

Operation

Command

Comments

W rite

Erase

Suspend

Read

Data = B0H
Addr = X

Check SR.7

1 = WSM Ready
0 = WSM Busy

Status Register Data

Toggle CE# or OE#

to update SRD.

Addr = X

Standby

CSR.6 =

Write FFH

Read Array Data

Done

Reading

Erase Completed

Write FFH

Read Array Data

YES

Check SR.6

1 = Erase Suspended
0 = Erase Completed

Standby

Data = FFH
Addr = X

W rite

Read array data from block other

than the one being erased.

Read

Data = D0H
Addr = X

W rite

Read Array

Erase Resume

0539_08

Figure 8. Erase Suspend/Resume Flowchart

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3.5

Power Consumption

3.5.1

ACTIVE POWER

With CE# at a logic-low level and RP# at a
logic-high level, the device is placed in the
active mode. Refer to the DC
Characteristics table for I

current values.

3.5.2

AUTOMATIC POWER

SAVINGS (APS)

Automatic Power Savings (APS) provides
low-power operation during active mode.
Power Reduction Control (PRC) circuitry
allows the device to put itself into a low
current state when not being accessed. After
data is read from the memory array, PRC
logic controls the device's power
consumption by entering the APS mode
where typical I

current is less than 1 mA.

The device stays in this static state with
outputs valid until a new location is read.

3.5.3

STANDBY POWER

With CE# at a logic-high level (V

), and

the CUI in read mode, the memory is placed
in standby mode, which disables much of
the device's circuitry and substantially
reduces power consumption. Outputs (DQ

or DQ

) are placed in a high-

impedance state independent of the status of
the OE# signal. When CE# is at logic-high
level during erase or program operations,
the device will continue to perform the
operation and consume corresponding
active power until the operation is
completed.

3.5.4

DEEP POWER-DOWN MODE

The SmartVoltage boot block family
supports a low typical I

in deep power-

down mode, which turns off all circuits to
save power. This mode is activated by the
RP# pin when it is at a logic-low

(GND

0.2V). Note: BYTE# pin must be

at CMOS levels to meet the I

CCD

specification.
During read modes, the RP# pin going low
de-selects the memory and places the output
drivers in a high impedance state. Recovery
from the deep power-down state, requires a
minimum access time of t

PHQV

(see AC

Characteristics table).
During erase or program modes, RP# low
will abort either erase or program
operations, but the memory

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contents are no longer valid as the data has
been corrupted by the RP# function. As in
the read mode above, all internal circuitry is
turned off to achieve the power savings.
RP# transitions to V

, or turning power off

to the device will clear the Status Register.

3.6

Power-Up/Down Operation

The device is protected against accidental
block erasure or programming during power
transitions. Power supply sequencing is not
required, since the device is indifferent as
to which power supply, V

or V

, powers-

up first. The CUI is reset to the read mode
after power-up, but the system must drop
CE# low or present a new address to ensure
valid data at the outputs.
A system designer must guard against
spurious writes when V

voltages are

above V

LKO

and V

is active. Since both

WE# and CE# must be low for a command
write, driving either signal to V

will

inhibit writes to the device. The CUI
architecture provides additional protection
since alteration of memory contents can
only occur after successful completion of
the two-step command sequences. The
device is also disabled until RP# is brought
to V

, regardless of the state of its control

inputs. By holding the device in reset (RP#
connected to system PowerGood) during
power-up/down, invalid bus conditions
during power-up can be masked, providing
yet another level of memory protection.

3.6.1

RP# CONNECTED TO

SYSTEM RESET

The use of RP# during system reset is
important with automated write/erase
devices because the system expects to read
from the flash memory when it comes out
of reset. If a CPU reset occurs without a
flash memory reset, proper CPU

initialization would not occur because the
flash memory may be providing status
information instead of array data. Intel's
Flash memories allow proper CPU
initialization following a system reset by
connecting the RP# pin to the same
RESET# signal that resets the system CPU.

3.6.2

, V

AND RP#

TRANSITIONS

The CUI latches commands as issued by
system software and is not altered by V

CE# transitions or WSM actions. Its default
state upon power-up, after exit from deep
power-down mode, or after V

transitions

above V

LKO

(Lockout voltage), is read array

mode.
After any word/byte write or block erase
operation is complete and even after V

transitions down to V

PPLK

, the CUI must be

reset to read array mode via the Read Array
command if accesses to the flash memory
are desired.
Please refer to AP-617, "Additional Flash
Data Protection Using V

, RP#, and WP#"

for a circuit-level description of how to
implement the protection discussed in
Section 3.6.

3.7

Power Supply Decoupling

Flash memory's power switching
characteristics require careful device
decoupling methods. System designers
should consider three supply current issues:
1. Standby current levels (I

CCS

)

2. Active current levels (I

CCR

)

3. Transient peaks produced by falling and

rising edges of CE#.

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Transient current magnitudes depend on the
device outputs' capacitive and inductive
loading. Two-line control and proper
decoupling capacitor selection will suppress
these transient voltage peaks. Each flash
device should have a 0.1 µF ceramic
capacitor connected between each V

and

GND, and between its V

and GND. These

high- frequency, inherently low-inductance
capacitors should be placed as close as
possible to the package leads.

3.7.1

TRACE ON PRINTED

CIRCUIT BOARDS

Designing for in-system writes to the flash
memory requires special consideration of
the V

power supply trace by the printed

circuit board designer. The V

pin supplies

the flash memory cells current for
programming and erasing. One should use
similar trace widths and layout
considerations given to the V

power

supply trace. Adequate V

supply traces,

and decoupling capacitors placed adjacent
to the component, will decrease spikes and
overshoots.

NOTE:

Table headings in Sections 5 and 6 (i.e., BV-70, BV-120, TBV-90, TBE-120) refer to
the specific products listed below. See Section 7.1 for more information on product
naming and line items.

Abbreviatio

Applicable Product Names

BV-70

E28F008BV-T70, E28F008BV-B70, E28F800CV-T70, E28F800CV-
B70, PA28F800BV-T70, PA28F800BV-B70

BV-120

E28F008BV-T120, E28F008BV-B120, PA28F800BV-T120,
PA28F800BV-B120

TBV-90

TE28F008BV-T90, TE28F008BV-B90, TE28F800CV-T90,
TE28F800CV-B90, TB28F800BV-T90, TB28F800BV-B90

TBE-120

TE28F008BE-T120, TE28F008BE-B120, TE28F800CE-T120,
TE28F800CE-B120, TB28F800BE-T120, TB28F800BE-B120

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4.0

ABSOLUTE MAXIMUM

RATINGS*

Commercial Operating Temperature

During Read.....................0°C to +70°C
During Block Erase
and Word/Byte Write.......0°C to +70°C
Temperature Bias .........10°C to +80°C

Extended Operating Temperature

During Read.................40°C to +85°C
During Block Erase
and Word/Byte Write...40°C to +85°C
Temperature Under Bias40°C to +85°C

Storage Temperature........65°C to +125°C
Voltage on Any Pin

(except V

, V

, A

and RP#)

with Respect to GND.2.0V to +7.0V

(2)

Voltage on Pin RP# or Pin A

with Respect to GND2.0V to
+13.5V

(2,3)

Program Voltage with Respect

to GND during Block Erase
and Word/Byte Write2.0V to
+14.0V

(2,3)

Supply Voltage

with Respect to GND.2.0V to +7.0V

(2)

Output Short Circuit Current......100 mA

(4)

NOTICE: This datasheet contains information on products in the
sampling and initial production phases of development. The
specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest datasheet
before finalizing a design.

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These are
stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.

NOTES:

Operating temperature is for commercial product defined

by this specification.

Minimum DC voltage is 0.5V on input/output pins.

During transitions, this level may undershoot to 2.0V for

periods < 20 ns. Maximum DC voltage on input/output pins

is V

+ 0.5V which, during transitions, may overshoot to

+ 2.0V for periods

< 20 ns.

Maximum DC voltage on V

may overshoot to +14.0V for

periods < 20 ns. Maximum DC voltage on RP# or A

may

overshoot to 13.5V for periods < 20 ns.

Output shorted for no more than one second. No more than

one output shorted at a time.

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5.0

COMMERCIAL OPERATING CONDITIONS

Table 10. Commercial Temperature and V

Operating Conditions

Symbol

Parameter

Notes

Min

Max

Units

Operating Temperature

+70

°C

3.3V V

Supply Voltage (±

0.3V)

3.0

3.6

Volts

5V V

Supply Voltage (10%)

4.50

5.50

Volts

5V V

Supply Voltage (5%)

4.75

5.25

Volts

NOTES:
1. 10% V

specifications apply to the 80 ns and 120 ns product versions in their standard test configuration.

2. 5% V

specifications apply to the 80 ns versions in their high-speed test configuration.

5.1

Applying V

Voltages

When applying V

voltage to the device, a delay may be required before initiating device

operation, depending on the V

ramp rate. If V

ramps slower than 1V/100 µs (0.01 V/µs)

then no delay is required. If V

ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2

µs is required before initiating device opeation. RP# = GND is recommended during power-
up to protect against spurious write signals when V

is between V

LKO

and V

CCMIN

Ramp

Rate

Required Timing

1V/100

No delay required.

> 1V/100

A delay time of 2

s is required before any device operation is initiated,

including read operations, command writes, program operations, and erase
operations. This delay

is measured beginning from the time V

reaches

CCMIN

(3.0V for 3.3

0.3V operation; and 4.5V for 5V operation).

NOTES:
1.

These requirements must be strictly followed to guarantee all other read and write specifications.

To switch between 3.3V and 5V operation, the system should first transition V

from the existing voltage range to GND, and then

to the new voltage. Any time the V

supply drops below V

CCMIN

, the chip may be reset, aborting any operations pending or in

progress.

These guidelines must be followed for any V

transition from GND.

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5.2

DC Characteristics

Table 11. DC Characteristics (Commercial)

Prod

BV-70

BV-120

Sym

Parameter

3.3 ± 0.3V

5V ± 10% Unit

Test Conditions

Note

Typ Max Typ Max

Input Load Current

1.0

µA V

= V

Max

= V

or GND

Output Leakage
Current

± 10

µA V

= V

Max

= V

or GND

CCS

Standby

Current

1,3

0.4

1.5

0.8

2.0

mA V

= V

Max

CE# = RP# = BYTE#
=
WP# = V

110

130

µA V

= V

Max

CE# = RP# = V

0.2V

CCD

Deep

Power-Down
Current

0.2

µA V

= V

Max

= V

or GND

RP# = GND ± 0.2V

CCR

Read Current

for Word or Byte

1,5,6

mA CMOS INPUTS

= V

Max

CE# = GND, OE# =
V

f = 10 MHz (5V),
5 MHz (3.3V)
I

OUT

= 0 mA

Inputs = GND ±
0.2V or
V

± 0.2V

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Table 11. DC Characteristics (Commercial)

mA TTL INPUTS

= V

Max

CE# = V

, OE# =

f = 10 MHz (5V),
5 MHz (3.3V)
I

OUT

= 0 mA

Inputs = V

or V

CCW

Write Current

for Word or Byte

1,4

mA V

= V

PPH

1 (at 5V)

Word Write in
Progress

mA V

= V

PPH

2 (at 12V)

Word Write in
Progress

CCE

Erase Current

1,4

mA V

= V

PPH

1 (at 5V)

Block Erase in
Progress

mA V

= V

PPH

2 (at

12V)
Block Erase in
Progress

CCES

Erase Suspend

Current

1,2

8.0

mA CE# = V

Block Erase Suspend

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PRODUCT PREVIEW

Table 11. DC Characteristics (Commercial) (Continued)

Prod

BV-70

BV-120

Sym

Parameter

3.3 ± 0.3V

5V ± 10% Unit

Test Conditions

Note

Typ Max Typ Max

PPS

Standby

Current

0.5

± 15

0.5

± 10

µA V

< V

PPH

PPD

Deep Power-

Down
Current

0.2

5.0

µA RP# = GND ± 0.2V

PPR

Read Current

200

µA V

PPH

PPW

Word/Byte

Current

1,4

mA V

= V

PPH

1 (at 5V)

Word Write in
Progress

= V

PPH

2 (at 12V)

Word Write in
Progress

PPE

Erase Current

1,4

mA V

= V

PPH

1 (at 5V)

Block Erase in
Progress

= V

PPH

2 (at 12V)

Block Erase in
Progress

PPES

Erase

Suspend Current

200

µA V

= V

PPH

Block

Erase
Suspend in Progress

RP#

RP# Boot Block
Unlock Current

1,4

500

µA RP# = V

Intelligent

Identifier Current

1,4

500

µA A

= V

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PRODUCT PREVIEW

Table 11. DC Characteristics (Commercial) Continued

Prod

BV-70

BV-120

Sym

Parameter

3.3 ± 0.3V

5V ± 10% Unit

Test

Conditions

Notes Min Max Min Max

Intelligent Identifier

Voltage

11.4 12.6 11.4 12.6

Input Low Voltage

0.5

0.8

0.5

0.8

Input High Voltage

2.0

0.5V

2.0

0.5V

Output Low Voltage

0.45

= V

Min
I

= 5.8 mA

1 Output High Voltage

(TTL)

2.4

= V

Min
I

= 2.5

2 Output High Voltage

(CMOS)

0.85

= V

Min
I

= 2.5

0.4V

= V

Min
I

= 100

PPL

Lock-Out Voltage

0.0

1.5

0.0

1.5

Complete
Write
Protection

PPH

(Prog/Erase

Operations)

4.5

5.5

4.5

5.5

at 5V

PPH

(Prog/Erase

Operations)

11.4 12.6 11.4 12.6

at 12V

LKO

Erase/Write Lock

Voltage

2.0

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PRODUCT PREVIEW

Table 11. DC Characteristics (Commercial) Continued

RP# Unlock Voltage

11.4 12.6 11.4 12.6

Boot Block
Write/Erase

Table 12. Capacitance (T

= 25 °C, f = 1 MHz)

Symbol

Parameter

Notes

Typ

Max

Units

Conditions

Input
Capacitance

= 0V

OUT

Output
Capacitance

4, 7

OUT

= 0V

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V

= 5.0V, T = +25°C. These currents are valid for all product

versions (packages and speeds).

2. I

CCES

is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of I

CCES

and

CCR

3. Block erases and word/byte writes are inhibited when V

= V

PPLK

, and not guaranteed in the range between V

PPH

1 and V

PPLK

4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

± 0.2V or GND ± 0.2V. TTL Inputs are either V

or V

7. For the 28F008B, address pin A

follows the C

OUT

capacitance numbers.

8. For all BV/CV parts, V

LKO

= 2.0V for both 3.3V and 5V operations.

TEST POINTS

INPUT

OUTPUT

1.5

3.0

0.0

1.5

0539_09

NOTE:
AC test inputs are driven at 3.0V for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise

and fall times (10%90%) <10 ns.

Figure 9. 3.3V Inputs and Measurement Points

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TEST POINTS

INPUT

OUTPUT

2.0

0.8

2.0

2.4

0.45

0539_10

NOTE:
AC test inputs are driven at V

(2.4 V

TTL

) for a logic "1" and V

(0.45 V

TTL

) for a logic "0." Input timing begins at V

(2.0 V

TTL

)

and V

(0.8 V

TTL

) . Output timing ends at V

and V

. Input rise and fall times (10%90%) <10 ns.

Figure 10. 5V Inputs and Measurement Points

Out

Device

under

Test

0539-11

NOTE:
See table for component values.

Figure 11. Test Configuration

Test Configuration Component Values

Test Configuration

(pF)

(

)

(

)

3.3V Standard Test

990

770

5V Standard Test

100

580

390

5V High-Speed Test

580

390

NOTE:
C

includes jig capacitance.

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PRODUCT PREVIEW

5.3

AC Characteristics

Table 13. AC Characteristics: Read Only Operations (Commercial)

Prod

BV-70

3.3±0.3V

(

5V±5%

(6)

5V±10%

(

Symbo

Parameter

Loa

50 pF

30 pF

100 pF

Unit

Note

Min

Max

Min

Max

Min

Max

AVAV

Read Cycle Time

120

AVQV

Address to Output Delay

120

ELQV

CE# to Output Delay

120

PHQV

RP# to Output Delay

1.5

0.4

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# to Output in High Z

Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First

ELFL

ELFH

CE# Low to BYTE# High
or Low

AVFL

Address to BYTE# High or
Low

FLQV

FHQV

BYTE# to Output Delay

3,4

120

FLQZ

BYTE# Low to Output in
High Z

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PRODUCT PREVIEW

Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued)

Prod

BV-120

Sym

Parameter

3.3±0.3V

(5)

5V±10%

(7)

Units

Load

50 pF

100 pF

Notes

Min Max Min Max

AVAV

Read Cycle Time

150

120

AVQV

Address to Output Delay

150

120

ELQV

CE# to Output Delay

150

120

PHQV

RP# to Output Delay

1.5

0.45

µs

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# to Output in High Z

Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First

ELFL

ELFH

CE# Low to BYTE# High or Low

AVFL

Address to BYTE# High or Low

FLQV

FHQV

BYTE# to Output Delay

3,4

150

120

FLQZ

BYTE# Low to Output in High Z

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to t

after the falling edge of CE# without impact on t

3. Sampled, but not 100% tested.
4. t

FLQV

, BYTE# switching low to valid output delay will be equal to t

AVQV

, measured from the time DQ

becomes valid.

5. See Test Configurations (Figure 11), 3.3V Standard Test component values.
6. See Test Configurations (Figure 11), 5V High-Speed Test component values.
7. See Test Configurations (Figure 11), 5V Standard Test component values.

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Address Stable

Device and

Address Selection

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP#(P)

PHQV

High Z

Valid Output

Data

Valid

Standby

AVAV

EHQZ

GHQZ

GLQV

GLQX

ELQV

ELQX

AVQV

High Z

0539_14

Figure 12. AC Waveforms for Read Operations

Address Stable

Device

Address Selection

ADDRESSES (A)

CE# (E)

OE# (G)

BYTE# (F)

DATA (D/Q)

(DQ0-DQ7)

High Z

Data Output

on DQ0-DQ7

Data

Valid

Standby

AVAV

EHQZ

GHQZ

AVQV

High Z

GLQV

ELQV

AVQV

Data Output

on DQ0-DQ7

DATA (D/Q)

(DQ8-DQ14)

High Z

Data Output

on DQ8-DQ14

High Z

(DQ15/A-1)

High Z

Data Output

on DQ15

Address Input

FLQZ

ELQX

ELFL

AVFL

GLQX

0539_15

Figure 13. BYTE# Timing Diagram for Read Operations

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PRODUCT PREVIEW

Table 14. AC Characteristics: WE#Controlled Write Operations

(1)

(Commercial)

Symbo

Parameter

3.3±0.3V

(

5V±5%

(10

)

5V±10%

(

11)

Unit

Loa

50 pF

30 pF

100 pF

Note

AVAV

Write Cycle Time

120

PHWL

RP# Setup to WE# Going
Low

1.5

0.4

ELWL

CE# Setup to WE# Going
Low

PHHWH

Boot Block Lock Setup to
WE# Going High

6,8

200

100

VPWH

Setup to WE# Going

High

5,8

200

100

AVWH

Address Setup to WE#
Going High

DVWH

Data Setup to WE# Going
High

WLWH

WE# Pulse Width

WHDX

Data Hold Time from WE#
High

WHAX

Address Hold Time from
WE# High

WHEH

CE# Hold Time from WE#
High

WHWL

WE# Pulse Width High

WHQV1

Duration of Word/Byte
Programming Operation

2,5

µs

WHQV2

Duration of Erase
Operation (Boot)

2,5,6 0.3

0.3

WHQV3

Duration of Erase
Operation (Parameter)

2,5

0.3

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PRODUCT PREVIEW

Table 14. AC Characteristics: WE#Controlled Write Operations

(1)

(Commercial)

(Continued)

Prod

BV-120

Sym

Parameter

3.3±0.3V

(9)

5V±10%

(11)

Unit

Load

50 pF

100 pF

Note

Min Max Min Max

AVAV

Write Cycle Time

180

120

PHWL

RP# Setup to WE# Going Low

1.5

0.45

µs

ELWL

CE# Setup to WE# Going Low

PHHWH

Boot Block Lock Setup to WE#
Going High

6,8

200

100

VPWH

Setup to WE#

Going High

5,8

200

100

AVWH

Address Setup to WE# Going
High

150

DVWH

Data Setup to WE# Going High

150

WLWH

WE# Pulse Width

150

WHDX

Data Hold Time from WE# High

WHAX

Address Hold Time from WE#
High

WHEH

CE# Hold Time from WE# High

WHWL

WE# Pulse Width High

WHQV1

Duration of Word/Byte
Programming Operation

2,5

µs

WHQV2

Duration of Erase Operation
(Boot)

2,5,6

0.3

WHQV3

Duration of Erase Operation
(Parameter)

2,5

0.3

WHQV4

Duration of Erase Operation
(Main)

2,5

0.6

QWL

Hold from Valid SRD

5,8

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PRODUCT PREVIEW

QVPH

RP# V

Hold from Valid SRD

6,8

PHBR

Boot-Block Lock Delay

7,8

200

100

NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which

includes verify and margining operations.

3. Refer to command definition table for valid A

. (Table 7)

4. Refer to command definition table for valid D

. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7=1).
6. For boot block program/erase, RP# should be held at V

or WP# should be held at V

until operation completes successfully.

7. Time t

PHBR

is required for successful locking of the boot block.

8. Sampled, but not 100% tested.
9. See Test Configurations (Figure 11), 3.3V Standard Test component values.)
10. See Test Configurations (Figure 11), 5V High-Speed Test component values.
11. See Test Configurations (Figure 11), 5V Standard Test component values.

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

6.5V

WHEH

WHWL

Valid
SRD

WHQV1,2,3,4

PHHWH

PHWL

High Z

WHDX

V (V)

PPH

PPLK

PPH

WP#

AVAV

AVWH

WHAX

DVWH

WLWH

QVPH

QVVL

VPWH

ELWL

0539_16

Figure 14. AC Waveforms for Write and Erase Operations (WE#Controlled Writes)

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PRODUCT PREVIEW

Table 15. AC Characteristics: CE#Controlled Write Operations

(1,12)

(Commercial)

Prod

BV-70

3.3±0.3V

(

5V±5%

(10

)

5V±10%

(

11)

Symbo

Parameter

Loa

50 pF

30 pF

100 pF

Unit

Note

Min

Max

Min

Max

Min

Max

AVAV

Write Cycle Time

120

PHEL

RP# High Recovery to CE#
Going Low

1.5

0.4

µs

WLEL

WE# Setup to CE# Going
Low

PHHEH

Boot Block Lock Setup to
CE# Going High

6,8

200

100

VPEH

Setup to CE# Going

High

5,8

200

100

AVEH

Address Setup to CE#
Going High

DVEH

Data Setup to CE# Going
High

ELEH

CE# Pulse Width

EHDX

Data Hold Time from CE#
High

EHAX

Address Hold Time from
CE# High

EHWH

WE # Hold Time from CE#
High

EHEL

CE# Pulse Width High

EHQV1

Duration of Word/Byte
Programming Operation

2,5

µs

EHQV2

Duration of Erase
Operation (Boot)

2,5,6 0.3

0.3

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PRODUCT PREVIEW

Table 15. AC Characteristics: CE#Controlled Write Operations

(1,12)

(Commercial)

EHQV3

Duration of Erase
Operation (Parameter)

2,5

0.3

EHQV4

Duration of Erase
Operation (Main)

2,5

0.6

QWL

Hold from Valid SRD

5,8

QVPH

RP# V

Hold from Valid

SRD

6,8

PHBR

Boot-Block Lock Delay

7,8

200

100

Table 15. AC Characteristics: CE#Controlled Write Operations

(1,12)

(Commercial)

(Continued)

Prod

BV-120

Sym

Parameter

3.3±0.3V

(9)

5V±10%

(11)

Unit

Load

50 pF

100 pF

Note

Min Max Min Max

AVAV

Write Cycle Time

180

120

PHEL

RP# High Recovery to CE# Going
Low

1.5

0.45

WLEL

WE# Setup to CE# Going Low

PHHEH

Boot Block Lock Setup to CE#
Going High

6,8

200

100

VPEH

Setup to CE# Going High

5,8

200

100

AVEH

Address Setup to CE# Going High

150

DVEH

Data Setup to CE# Going High

150

ELEH

CE# Pulse Width

150

EHDX

Data Hold Time from CE# High

EHAX

Address Hold Time from CE#
High

EHWH

WE # Hold Time from CE# High

EHEL

CE# Pulse Width High

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PRODUCT PREVIEW

EHQV1

Duration of Word/Byte
Programming Operation

2,5

µs

EHQV2

Duration of Erase Operation
(Boot)

2,5,6

0.3

EHQV3

Duration of Erase Operation
(Parameter)

2,5

0.3

EHQV4

Duration of Erase Operation
(Main)

2,5

0.6

QWL

Hold from Valid SRD

5,8

QVPH

RP# V

Hold from Valid SRD

6,8

PHBR

Boot-Block Lock Delay

7,8

200

100

NOTES:
See WE# Controlled Write Operations for notes 1 through 11.
12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where

CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should

be measured relative to the CE# waveform.

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PRODUCT PREVIEW

ADDRESSES (A)

WE# (W)

OE# (G)

CE# (E)

DATA (D/Q)

RP# (P)

6.5V

AVAV

Valid
SRD

QVPH

PHHEH

High Z

EHDX

V (V)

EHAX

EHQV1,2,3,4

EHEL

EHWH

ELEH

DVEH

VPEH

QVVL

PHEL

WLEL

AVEH

PPLK

PPH

WP#

0539_17

NOTES:
1. V

Power-Up and Standby.

2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.

Figure 15. Alternate AC Waveforms for Write and Erase Operations (CE#Controlled

Writes)

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PRODUCT PREVIEW

Table 16. Erase and Program Timings (Commercial T

= 0°C to +70°C)

5V ± 10%

12V ± 5%

Parameter

3.3 ± 0.3V

5V ± 10%

3.3 ± 0.3V

5V ± 10% Un

Typ Max Typ Max Typ Max Typ Max

Boot/Parameter Block Erase
Time

0.84

0.8

0.44

0.34

Main Block Erase Time

2.4

1.9

1.3

1.1

Main Block Write Time (Byte
Mode)

1.7

1.8

1.6

1.2

Main Block Write Time (Word
Mode)

1.1

0.9

0.8

0.6

Byte Write Time

µs

Word Write Time

µs

NOTES:
1.

All numbers are sampled, not 100% tested.

Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of V

and

. See Note 3 for typical conditions.

Typical conditions are 25°C with V

and V

at the center of the specifed voltage range. Production programming using

= 5.0V, V

= 12.0V typically results in a 60% reduction in programming time.

Contact your Intel representative for information regarding maximum byte/word write specifications.

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PRODUCT PREVIEW

6.0

EXTENDED OPERATING CONDITIONS

Table 17. Extended Temperature and V

Operating Conditions

Symbol

Parameter

Notes

Min

Max

Units

Operating Temperature

+85

°C

2.7V3.6V V

Supply

Voltage

2.7

3.6

Volts

3.3V V

Supply Voltage (±

0.3V)

3.0

3.6

Volts

5V V

Supply Voltage (10%)

4.50

5.50

Volts

NOTES:
1. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
2. 10% V

specifications apply to 100 ns versions in their standard test configuration.

6.1

Applying V

Voltages

When applying V

voltage to the device, a delay may be required before initiating device

operation, depending on the V

ramp rate. If V

ramps slower than 1V/100 µs (0.01 V/µs)

then no delay is required. If V

ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2

µs is required before initiating device opeation. RP# = GND is recommended during power-
up to protect against spurious write signals when V

is between V

LKO

and V

CCMIN

Ramp

Rate

Required Timing

1V/100

No delay required.

> 1V/100

A delay time of 2

s is required before any device operation is initiated,

including read operations, command writes, program operations, and erase
operations. This delay

is measured beginning from the time V

reaches

CCMIN

(2.7V for 2.7V3.6V operation, 3.0V for 3.3

0.3V operation; and

4.5V for 5V operation).

NOTES:
1.

These requirements must be strictly followed to guarantee all other read and write specifications.

To switch between 3.3V and 5V operation, the system should first transition V

from the existing voltage range to GND, and then

to the new voltage. Any time the V

supply drops below V

CCMIN

, the chip may be reset, aborting any operations pending or in

progress.

These guidelines must be followed for any V

transition from GND.

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PRODUCT PREVIEW

6.2

DC Characteristics

Table 18. DC Characteristics: Extended Temperature Operation

Prod

TBE-120

TBV-90

TBE-120

Sym Paramet

2.7V3.6V

3.3V ±

0.3V

5V ± 10% Unit

Test Conditions

Note

Typ Ma

Input
Load
Current

1.0

µA V

= V

Max

= V

or GND

Output
Leakage
Current

± 10

± 10 µA V

= V

Max

= V

or GND

CCS

Standby
Current

1,3

110

150

µA CMOS Levels

= V

Max

CE# = RP# = WP#
=
V

± 0.2V

0.4

1.5

0.4

1.5

0.8

2.5

mA TTL Levels

= V

Max

CE# = RP# =
BYTE#
= V

CCD

Deep

Power-
Down
Current

0.2

µA V

= V

Max

= V

or GND

RP# = GND ±
0.2V

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PRODUCT PREVIEW

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod

TBE-120

TBV-90

TBE-120

Sym Paramet

2.7V3.6V

3.3V ±

0.3V

5V ± 10% Unit

Test Conditions

Note

Typ Ma

CCW

Write

Current
for Word
or Byte

1,4

mA V

= V

PPH

1 (at

5V)
Word/Byte
Program
in Progress

mA V

= V

PPH

2 (at

12V)
Word/Byte
Program
in Progress

CCE

Erase

Current

1,4

mA V

= V

PPH

1 (at

5V)
Block Erase in
Progress

mA V

= V

PPH

2 (at

12V)
Block Erase in
Progress

CCES

Erase

Suspend
Current

1,2

2.5

8.0

12.0 mA V

= V

PPH

1 (at

5V)
CE# = V

Block Erase
Suspend

PPS

Standby
Current

± 5 ± 15 ± 5 ± 15 ± 5 ± 15 µA V

< V

PPH

PPD

Deep

Power-
down
Current

0.2

µA RP# = GND ±

0.2V

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PRODUCT PREVIEW

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod

TBE-120

TBV-90

TBE-120

Sym Paramet

2.7V3.6V

3.3V ±

0.3V

5V ± 10% Unit

Test Conditions

Note

Typ Ma

PPE

Erase

Current

1,4

mA V

= V

PPH

Block Erase in
Progress
V

= V

PPH

1 (at

5V)

mA V

= V

PPH

Block Erase in
Progress
V

= V

PPH

2 (at

12V)

PPES

Erase

Suspend
Current

200

µA V

= V

PPH

Block Erase
Suspend

in Progress

RP#

RP# Boot
Block
Unlock
Current

1,4

500

µA RP# = V

= 12V

Intelligen
t
Identifier
Current

1,4

500

µA A

= V

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PRODUCT PREVIEW

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120

TBV-90

TBE-120

Sym Paramet

2.7V

3.6V

3.3V ±

0.3V

5V ± 10% Unit

Test Conditions

Note

Min Ma

Intelligen
t
Identifier
Voltage

11.4 12.

11.4 12.6 11.

12.6

Input
Low
Voltage

0.5 0.8 0.5

0.8

0.5

0.8

Input
High
Voltage

2.0 V

0.5

2.0

0.5

2.0 V

0.5

Output
Low
Voltage

0.4

0.45

= V

Min

= 12V

= 5.8 mA (5V)

2 mA (3.3V)

1 Output

High
Voltage
(TTL)

2.4

= V

Min

= 2.5 mA

2 Output

High
Voltage

0.85

0.8

5 !
V

= V

Min

= 2.5 mA

(CMOS)

0.4

0.4V

0.4

= V

Min

= 100 µA

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PRODUCT PREVIEW

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

PPL

Lock-Out
Voltage

0.0

1.5

0.0

1.5

0.0

1.5

Complete Write
Protection

PPH

during
Prog/Eras
e
Operation
s

4.5

5.5

4.5

5.5

4.5

5.5

at 5V

PPH

11.4 12.

11.4 12.6 11.

12.6

at 12V

LKO

Erase/Wri
te Lock
Voltage

2.0

RP#
Unlock
Voltage

11.4 12.

11.4 12.6 11.

12.6

Boot Block Write/

Erase

= 12V

Table 19. Capacitance (T

= 25 °C, f = 1 MHz)

Symbol

Parameter

Notes

Typ

Max

Units

Conditions

Input
Capacitance

= 0V

OUT

Output
Capacitance

OUT

= 0V

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V

= 5.0V, T = +25°C. These currents are valid for all product

versions (packages and speeds).

2. I

CCES

is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I

CCES

and I

CCR

3. Block erases and word/byte writes inhibited when V

= V

PPLK

, and not guaranteed in the range between V

PPH

1 and V

PPLK

4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

± 0.2V or GND ± 0.2V. TTL Inputs are either V

or V

7. For the 28F008B address pin A

follows the C

OUT

capacitance numbers.

8. For all BV/CV/BE/CE parts, V

LKO

= 2.0V for 2.7V, 3.3V and 5.0V operations.

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PRODUCT PREVIEW

TEST POINTS

INPUT

OUTPUT

1.35

2.7

0.0

1.35

0539_18

NOTE:
AC test inputs are driven at 2.7 for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise

and fall times (10%90%) <10 ns.

Figure 16. 2.73.6V Input Range and Measurement Points

TEST POINTS

INPUT

OUTPUT

1.5

3.0

0.0

1.5

0539_09

NOTE:
AC test inputs are driven at 3.0V for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise

and fall times (10%90%) <10 ns.

Figure 17. 3.3V Input Range and Measurement Points

TEST POINTS

INPUT

OUTPUT

2.0

0.8

2.0

2.4

0.45

0539_10

NOTE:
AC test inputs are driven at V

(2.4 V

TTL

) for a logic "1" and V

(0.45 V

TTL

) for a logic "0." Input timing begins at V

(2.0 V

TTL

)

and V

(0.8 V

TTL

) . Output timing ends at V

and V

. Input rise and fall times (10%90%) < 10 ns.

Figure 18. 5V Input Range and Measurement Points

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PRODUCT PREVIEW

6.3

AC Characteristics

Table 20. AC Characteristics: Read Only Operations

(1)

(Extended Temperature)

Prod TBE-120

TBV-90

TBE-120

Sym

Parameter

2.7

3.6V

(5)

3.3±0.3V

(

5V±10%

(

Unit

Loa

50 pF

100 pF

Note

AVAV

Read Cycle Time

120

AVQV

Address to Output Delay

120

ELQV

CE# to Output Delay

120

PHQV

RP# to Output Delay

1.5

0.4

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# to Output in High Z

Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First

ELFL

ELFH

CE# Low to BYTE# High
or Low

AVFL

Address to BYTE# High or
Low

FLQV

FHQV

BYTE# to Output Delay

3,4

120

FLQZ

BYTE# Low to Output in
High Z

NOTES:

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PRODUCT PREVIEW

Table 21. AC Characteristics: WE#-Controlled Write Operations

(1)

(Extended

Temperature)

Prod TBE-120

TBV-90

TBE-120

Sym

Parameter

2.7

3.6V

(9)

3.3±0.3V

(

5V±10%

(

10)

Units

Loa

50 pF

100 pF

Note

AVAV

Write Cycle Time

120

PHWL

RP# High Recovery to
WE# Going Low

1.5

0.4

ELWL

CE# Setup to WE# Going
Low

PHHWH

Boot Block Lock Setup to
WE# Going High

6,8

200

100

VPWH

Setup to WE#

Going High

5,8

200

100

AVWH

Address Setup to WE#
Going High

DVWH

Data Setup to WE# Going
High

WLWH

WE# Pulse Width

WHDX

Data Hold Time from WE#
High

WHAX

Address Hold Time from
WE# High

WHEH

CE# Hold Time from WE#
High

WHWL

WE# Pulse Width High

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PRODUCT PREVIEW

Table 21. AC Characteristics: WE#-Controlled Write Operations

(1)

(Extended

Temperature) (Continued)

Prod TBE-120

TBV-90

TBE-120

Sym

Parameter

2.7

3.6V

(9)

3.3±0.3V

(

5V±10%

(

10)

Unit

Loa

50 pF

100 pF

Note

QWL

Hold from Valid SRD

5,8

QVPH

RP# V

Hold from Valid

SRD

6,8

PHBR

Boot-Block Lock Delay

7,8

200

100

NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

Characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algori

thms are now controlled internally which

includes verify and margining operations.

3. Refer to command definition table for valid A

. (Table 7)

4. Refer to command definition table for valid D

. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at V

or WP# should be held at V

until operation completes successfully.

7. Time t

PHBR

is required for successful locking of the boot block.

8. Sampled, but not 100% tested.
9. See Test Configurations (Figure 19), 2.73.6V and 3.3

0.3V Standard Test component values.

10. See Test Configurations (Figure 19), 5V Standard Test component values.

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PRODUCT PREVIEW

Table 22. AC Characteristics: CE#Controlled Write Operations

(1,11)

(Extended

Temperature)

Prod TBE-120

TBV-90

TBE-120

Sym

Parameter

2.7

3.6V

(9)

3.3±0.3V

(

5V±10%

(

10)

Unit

Loa

50 pF

100 pF

Note

AVAV

Write Cycle Time

120

PHEL

RP# High Recovery to CE#
Going Low

1.5

0.4

WLEL

WE# Setup to CE# Going
Low

PHHEH

Boot Block Lock Setup to
CE# Going High

6,8

200

100

VPEH

Setup to CE# Going

High

5,8

200

100

AVEH

Address Setup to CE#
Going High

DVEH

Data Setup to CE# Going
High

ELEH

CE# Pulse Width

EHDX

Data Hold Time from CE#
High

EHAX

Address Hold Time from
CE# High

EHWH

WE# Hold Time from CE#
High

EHEL

CE# Pulse Width High

EHQV1

Duration of Word/Byte
Write Operation

2,5

µs

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PRODUCT PREVIEW

Table 22. AC Characteristics: CE#Controlled Write Operations

(1,11)

(Extended

Temperature)

EHQV2

Duration of Erase
Operation (Boot)

2,5,6 0.3

0.3

EHQV3

Duration of Erase
Operation (Parameter)

2,5

0.3

EHQV4

Duration of Erase
Operation (Main)

2,5

0.6

QWL

Hold from Valid SRD

5,8

QVPH

RP# V

Hold from Valid

SRD

6,8

PHBR

Boot-Block Lock Delay

7,8

200

100

NOTES:
See WE# Controlled Write Operations for notes 1 through 10.
11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines

the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative

to the CE# waveform.

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PRODUCT PREVIEW

Table 23. Extended Temperature Operations - Erase and Program Timings

5V ± 10%

12V ± 5%

2.73.6V

3.3 ±

0.3V

5V ±

10%

2.73.6V

3.3 ±

0.3V

5V ±

10%

Parameter

Typ Ma

Boot/Parameter
Block Erase
Time

0.88 TB

0.84

0.8

0.46 TB

0.44

0.34

Main Block
Erase Time

2.5 TB

2.4

1.9

14 1.36 TB

1.3

1.1

Main Block
Write Time
(Byte Mode)

1.87

1.7

1.4

1.76

1.6

1.2

Main Block
Write Time
(Word Mode)

1.21

1.1

0.9

0.88

0.8

0.6

Byte Write
Time

8.8

µs

Word Write
Time

14.3

8.8

µs

NOTES:
1.

All numbers are sampled, not 100% tested.

Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of V

and

. See Note 3 for typical conditions.

Typical conditions are 25°C with V

and V

at the center of the specifed voltage range. Production programming using

= 5.0V, V

= 12.0V typically results in a 60% reduction in programming time.

Contact your Intel representative for information regarding maximum byte/word write specifications.

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PRODUCT PREVIEW

Product line designator

for all Intel Flash products

Density / Organization
00X = x8-only (X = 1, 2, 4, 8)
X00 = x8/x16 Selectable (X = 2, 4, 8)

Access Speed
ns, BE: V = 2.7V
BV: V = 5V

Architecture
B = Boot Block
C = Compact 48-Lead TSOP
Boot Block

Operating Temperature
T = Extended Temp
Blank = Commercial Temp

Package
E

= TSOP

= 44-Lead PSOP

= Ext. Temp 44-Lead PSOP

E 2 8 F 8 0

0 CV - T 0

T = Top Boot
B = Bottom Boot

Voltage Options (V / V )
V = (5 or 12 / 3.3 or 5)
E = (5 or 12 / 2.7 or 5)

0530-23

VALID COMBINATIONS:

40-Lead TSOP

44-Lead PSOP

48-Lead TSOP

Commercial

E28F008BVT70

PA28F800BVT70

E28F800CVT70

E28F008BVB70

PA28F800BVB70

E28F800CVB70

E28F008BVT120

PA28F800BVT120

E28F008BVB120

PA28F800BVB120

Extended

TE28F008BVT90

TB28F800BVT90

TE28F800CVT90

TE28F008BVB90

TB28F800BVB90

TE28F800CVB90

TE28F008BET120

TE28F800CET120

TE28F008BEB120

TE28F800CEB120

Table 24. Summary of Line Items

Name

Package

Temperature

2.73.6

3.3±0.3

5 ± 10%

12 ± 5%

40-Ld
TSOP

44-Ld
PSOP

48-Ld
TSOP

Comm

Ext

28F008

28F800

28F008

28F800

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PRODUCT PREVIEW

7.2

References

Order

Number

Document

290531

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

290530

4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

290448

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

290449

28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory
Datasheet

290450

28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory
Datasheet

290451

28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

292148

AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to
Replace
EEPROM"

292172

AP-617 "Additional Flash Data Protection Using V

, RP#, and WP#"

292130

AB-57 "Boot Block Architecture for Safe Firmware Updates"

292154

AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"

7.3

Revision History

-001

Initial release of datasheet, no specifications included

-002

Explanation of WP# on 44-lead PSOP added; AC/DC Specifications
added, including BE product text and 2.7V specifications.

-003

28F800BE row removed from Table 1
Applying V

voltages (Sections 5.1 and 6.1) rewritten for clarity.

Minor cosmetic changes/edits.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: E28F008BVB70

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: E28F008BVB70