E
PRODUCT PREVIEW
May 1998
Order Number: 290644-001
n
High Performance
54 MHz Effective Zero Wait-State
Performance
Synchronous Burst-Mode Reads
Asynchronous Page-Mode Reads
n
SmartVoltage Technology
2.7 V
-
3.6 V Read and Write
Operations for Low Power Designs
12 V V
PP
Fast Factory Programming
n
Flexible I/O Voltage
1.65 V I/O Reduces Overall System
Power Consumption
5 V-Safe I/O Enables Interfacing to
5 V Devices
n
Enhanced Data Protection
Absolute Write Protection with
V
PP
= GND
Block Locking
Block Erase/Program Lockout
during Power Transitions
n
Density Upgrade Path
8- and 16-Mbit
n
Manufactured on ETOXTM V Flash
Technology
n
Supports Code Plus Data Storage
Optimized for Flash Data Integrator
(FDI) Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Flexible Blocking Architecture
Eight 4-Kword Blocks for Data
32-Kword Main Blocks for Code
Top or Bottom Configurations
Available
n
Extended Cycling Capability
Minimum 10,000 Block Erase Cycles
Guaranteed
n
Low Power Consumption
Automatic Power Savings Mode
Decreases Power Consumption
n
Automated Program and Block Erase
Algorithms
Command User Interface for
Automation
Status Register for System
Feedback
n
Industry-Standard Packaging
56-Lead SSOP
BGA* CSP
Intel's Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous
burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the
intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory
paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for
improved system performance. Therefore, it reduces the total memory requirement which helps increase
reliability and reduce overall system power consumption and cost.
This family of products is manufactured on Intel's 0.4
m ETOXTM V process technology. They are available
in industry-standard packages: the
BGA* CSP, ideal for board-constrained applications, and the rugged
56-lead SSOP.
FAST BOOT BLOCK
FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3
Includes Extended and Automotive Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel's Website at http://www.intel.com
COPYRIGHT INTEL CORPORATION, 1998
CG-041493
*Third-party brands and names are the property of their respective owners
E
FAST BOOT BLOCK DATASHEET
3
PRODUCT PREVIEW
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.2 Product Overview.........................................5
2.0 PRODUCT DESCRIPTION..............................6
2.1 Pinouts.........................................................6
2.2 Pin Description .............................................6
2.3 Memory Blocking Organization.....................9
2.3.1 Parameter Blocks ..................................9
2.3.2 Main Blocks ...........................................9
3.0 PRINCIPLES OF OPERATION .....................12
3.1 Bus Operations ..........................................12
3.1.1 Read....................................................12
3.1.2 Output Disable.....................................12
3.1.3 Standby ...............................................12
3.1.4 Write....................................................12
3.1.5 Reset...................................................13
4.0 COMMAND DEFINITIONS ............................13
4.1 Read Array Command................................15
4.2 Read Identifier Codes Command ...............15
4.3 Read Status Register Command................15
4.4 Clear Status Register Command................15
4.5 Block Erase Command ..............................15
4.6 Program Command....................................17
4.7 Block Erase Suspend/Resume Command .17
4.8 Program Suspend/Resume Command.......17
4.9 Set Read Configuration Command.............19
4.9.1 Read Configuration..............................19
4.9.2 Frequency Configuration .....................20
4.9.3 Data Output Configuration ...................20
4.9.4 WAIT# Configuration ...........................20
4.9.5 Burst Sequence...................................20
4.9.6 Clock Configuration .............................20
4.9.7 Burst Length ........................................20
5.0 DATA PROTECTION.....................................26
5.1 V
PP
= V
IL
for Complete Protection ..............26
5.2 WP# = V
IL
for Block Locking ......................26
5.3 WP# = V
IH
for Block Unlocking...................26
6.0 V
PP
VOLTAGES ............................................26
7.0 POWER CONSUMPTION..............................26
7.1 Active Power ..............................................26
7.2 Automatic Power Savings ..........................26
7.3 Standby Power...........................................27
7.4 Power-Up/Down Operation.........................27
7.4.1 RST# Connection ................................27
7.4.2 V
CC
, V
PP
and RST# Transitions ...........27
7.5 Power Supply Decoupling ..........................27
7.5.1 V
PP
Trace on Printed Circuit Boards ....27
8.0 ELECTRICAL SPECIFICATIONS .................28
8.1 Absolute Maximum Ratings........................28
8.2 Extended Temperature Operating
Conditions .................................................28
8.3 Capacitance ...............................................29
8.4 DC Characteristics--Extended
Temperature..............................................30
8.5 AC Characteristics--Read-Only
Operations--Extended Temperature .........32
8.6 AC Characteristics--Write Operations--
Extended Temperature..............................38
8.7 AC Characteristics--Reset Operation--
Extended Temperature..............................40
8.8 Extended Temperature Block Erase and
Program Performance ...............................41
8.9 Automotive Temperature Operating
Conditions .................................................41
FAST BOOT BLOCK DATASHEET
E
4
PRODUCT PREVIEW
8.10 Capacitance .............................................42
8.11 DC Characteristics--Automotive
Temperature..............................................43
8.12 AC Characteristics--Read-Only
Operations--Automotive Temperature ......44
8.13 Automotive Temperature Frequency
Configuration Settings ...............................45
8.14 Automotive Temperature Block Erase and
Program Performance ...............................45
9.0 ORDERING INFORMATION..........................46
10.0 ADDITIONAL INFORMATION .....................47
REVISION HISTORY
Date of
Revision
Version
Description
05/12/98
-001
Original version
E
FAST BOOT BLOCK DATASHEET
5
PRODUCT PREVIEW
1.0
INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot
Block memory information. Section 1.0 provides a
flash memory overview. Sections 2.0 through 8.0
describe the memory functionality and electrical
specifications for extended and automotive
temperature product offerings.
1.2
Product Overview
The Fast Boot Block flash memory family provides
density upgrades with pinout compatibility for 8- and
16-Mbit densities. This family of products are high
performance, low voltage memories with a 16-bit
data bus and individually erasable blocks. These
blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are
positioned at either the top (denoted by -T suffix) or
bottom (denoted by -B suffix) of the address map.
The rest of the device is grouped into
32-Kword main blocks. The upper two (or lower
two) parameter and all main blocks can be locked
for complete code protection.
The device's optimized architecture and interface
dramatically increases read performance beyond
previously attainable levels. It supports
asynchronous page-mode and synchronous burst
reads from main blocks (parameter blocks support
single asynchronous and synchronous reads).
Upon initial power-up or return from reset, the
device defaults to a page-mode read configuration.
Page-mode read configuration is ideal for non-clock
memory systems and is compatible with page-
mode ROM. Synchronous burst reads are enabled
by writing to the read configuration register. In
synchronous burst mode, the CLK input increments
an internal burst address generator, synchronizes
the flash memory with the host CPU, and outputs
data on every rising (or falling) CLK edge up to
54 MHz (25 MHz for automotive temperature). An
output signal, WAIT#, is also provided to ease CPU
to flash memory communication and
synchronization during continuous burst operations.
In addition to the enhanced architecture and
interface, this family of products incorporates
SmartVoltage technology which enables fast factory
programming and low power designs. Specifically
designed for low voltage systems, Fast Boot Block
flash memory components support read operations
at 2.7 V (3.3 V for automotive temperature) V
CC
and
block erase and program operations at 2.7
V
(3.3 V for automotive temperature) and 12 V V
PP
.
The 12 V V
PP
option renders the fastest program
performance to increase factory programming
throughput. With the 2.7 V (3.3 V for automotive
temperature) V
PP
option, V
CC
and V
PP
can be tied
together for a simple, low power design. In addition
to the voltage flexibility, the dedicated V
PP
pin gives
complete data protection when V
PP
V
PPLK
.
The flexible input/output (I/O) voltage capability
helps reduce system power consumption and
simplify interfacing to sub 2.7 V and 5 V CPUs.
Powered by V
CCQ
pins, the I/O buffers can operate
at a lower voltage than the flash memory core. With
V
CCQ
voltage at 1.65 V, the I/Os swing between
GND and 1.65 V, reducing I/O power consumption
by 65% over standard 3
V flash memory
components. The low voltage and 5 V-safe feature
also helps ease CPU interfacing by adapting to the
CPU's bus voltage.
The device's Command User Interface (CUI) serves
as the interface between the system processor and
internal flash memory operation. A valid command
sequence written to the CUI initiates device
automation. This automation is controlled by an
internal Write State Machine (WSM) which
automatically executes the algorithms and timings
necessary for block erase and program operations.
The status register provides WSM feedback by
signifying block erase or program completion and
status.
Block erase and program automation allows erase
and program operations to be executed using an
industry-standard two-write command sequence. A
block erase operation erases one block at a time,
and data is programmed in word increments. Erase
suspend allows system software to suspend an
ongoing block erase operation in order to read from
or program data to any other block. Program
suspend allows system software to suspend an
ongoing program operation in order to read from
any other location.
Fast Boot Block flash memory devices offer two low
power savings features: Automatic Power Savings
(APS) and standby mode. The device automatically
enters APS mode following the completion of a read
cycle. Standby mode is initiated when the system
deselects the device by driving CE# inactive or
RST# active. RST# also resets the device to read
array, provides write protection, and clears the
status register. Combined, these two features
significantly reduce power consumption.
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