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Электронный компонент: intel387

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Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
January 1994
COPYRIGHT
INTEL CORPORATION 1995
Order Number 240225-009
Intel387
TM
SX
MATH COPROCESSOR
Y
New Automatic Power Management
Low Power Consumption
Typically 100 mA in Dynamic Mode
and 4 mA in Idle Mode
Y
Socket Compatible with Intel387 Family
of Math CoProcessors
Hardware and Software Compatible
Supported by Over 2100 Commercial
Software Packages
10% to 15% Performance Increase
on Whetstone and Livermore
Benchmarks
Y
Compatible with the Intel386
TM
SX
Microprocessor
Extends CPU Instruction Set to
Include Trigonometric Logarithmic
and Exponential
Y
High Performance 80-Bit Internal
Architecture
Y
Implements ANSI IEEE Standard
754-1985 for Binary Floating-Point
Arithmetic
Y
Available in a 68-Pin PLCC Package
See Intel Packaging Specification Order
231369
The Intel387
TM
SX Math CoProcessor is an extension to the Intel386
TM
SX microprocessor architecture The
combination of the Intel387
TM
SX with the Intel386
TM
SX microprocessor dramatically increases the process-
ing speed of computer application software that utilizes high performance floating-point operations An internal
Power Management Unit enables the Intel387
TM
SX to perform these floating-point operations while maintain-
ing very low power consumption for portable and desktop applications The internal Power Management Unit
effectively reduces power consumption by 95% when the device is idle
The Intel387
TM
SX Math CoProcessor is available in a 68-pin PLCC package and is manufactured on Intel's
advanced 1 0 micron CHMOS IV technology
240225 22
Intel386 and Intel387 are trademarks of Intel Corporation
1
Intel387
TM
SX Math CoProcessor
CONTENTS
PAGE
1 0 PIN ASSIGNMENT
5
1 1 Pin Description Table
6
2 0 FUNCTIONAL DESCRIPTION
7
2 1 Feature List
7
2 2 Math CoProcessor Architecture
7
2 3 Power Management
8
2 3 1 Dynamic Mode
8
2 3 2 Idle Mode
8
2 4 Compatibility
8
2 5 Performance
8
3 0 PROGRAMMING INTERFACE
9
3 1 Instruction Set
9
3 1 1 Data Transfer Instructions
9
3 1 2 Arithmetic Instructions
9
3 1 3 Comparison Instructions
10
3 1 4 Transcendental
Instructions
10
3 1 5 Load Constant Instructions
10
3 1 6 Processor Instructions
11
3 2 Register Set
11
3 2 1 Status Word (SW) Register
12
3 2 2 Control Word (CW)
Register
15
3 2 3 Data Register
16
3 2 4 Tag Word (TW) Register
16
3 2 5 Instruction and Data
Pointers
16
3 3 Data Types
18
3 4 Interrupt Description
18
3 5 Exception Handling
18
3 6 Initialization
21
3 7 Processing Modes
21
3 8 Programming Support
21
CONTENTS
PAGE
4 0 HARDWARE SYSTEM
INTERFACE
21
4 1 Signal Description
22
4 1 1 Intel386 CPU Clock 2
(CPUCLK2)
22
4 1 2 Intel387 Math CoProcessor
Clock 2 (NUMCLK2)
22
4 1 3 Clocking Mode (CKM)
23
4 1 4 System Reset (RESETIN)
23
4 1 5 Processor Request
(PEREQ)
23
4 1 6 Busy Status (BUSY )
23
4 1 7 Error Status (ERROR )
23
4 1 8 Data Pins (D15 D0)
23
4 1 9 Write Read Bus Cycle
(W R )
23
4 1 10 Address Stobe (ADS )
23
4 1 11 Bus Ready Input
(READY )
24
4 1 12 Ready Output
(READYO )
24
4 1 13 Status Enable (STEN)
24
4 1 14 Math CoProcessor Select 1
(NPS1 )
24
4 1 15 Math CoProcessor Select 2
(NPS2)
24
4 1 16 Command (CMD0 )
24
4 1 17 System Power (V
CC
)
24
4 1 18 System Ground (V
SS
)
24
4 2 System Configuration
25
4 3 Math CoProcessor Architecture
26
4 3 1 Bus Control Logic
26
4 3 2 Data Interface and Control
Unit
26
4 3 3 Floating Point Unit
26
4 3 4 Power Management Unit
26
2
2
CONTENTS
PAGE
4 4 Bus Cycles
26
4 4 1 Intel387 SX Math
CoProcessor Addressing
27
4 4 2 CPU Math CoProcessor
Synchronization
27
4 4 3 Synchronous Asynchronous
Modes
27
4 4 4 Automatic Bus Cycle
Termination
27
5 0 BUS OPERATION
27
5 1 Non-pipelined Bus Cycles
28
5 1 1 Write Cycle
28
5 1 2 Read Cycle
29
5 2 Pipelined Bus Cycles
29
5 3 Mixed Bus Cycles
30
5 4 BUSY
and PEREQ Timing
Relationship
32
6 0 PACKAGE SPECIFICATIONS
33
6 1 Mechanical Specifications
33
6 2 Thermal Specifications
33
CONTENTS
PAGE
7 0 ELECTRICAL
CHARACTERISTICS
33
7 1 Absolute Maximum Ratings
33
7 2 D C Characteristics
34
7 3 A C Characteristics
35
8 0 Intel387 SX MATH COPROCESSOR
INSTRUCTION SET
41
APPENDIX A
Intel387 SX MATH
COPROCESSOR COMPATIBILITY
A-1
A 1 8087 80287 Compatibility
A-1
A 1 1 General Differences
A-1
A 1 2 Exceptions
A-2
APPENDIX B
COMPATIBILITY
BETWEEN THE 80287 AND 8087
MATH COPROCESSOR
B-1
3
3
CONTENTS
PAGE
FIGURES
Figure 1-1
Intel387 SX Math
CoProcessor Pinout
5
Figure 2-1
Intel387 SX Math
CoProcessor Block
Diagram
7
Figure 3-1
Intel 386 SX CPU and
Intel387 Math CoProcessor
Register Set
11
Figure 3-2
Status Word
12
Figure 3-3
Control Word
15
Figure 3-4
Tag Word Register
16
Figure 3-5
Instruction and Data Pointer
Image in Memory 32-Bit
Protected Mode Format
17
Figure 3-6
Instruction and Data Pointer
Image in Memory 16-Bit
Protected Mode Format
17
Figure 3-7
Instruction and Data Pointer
Image in Memory 32-Bit
Real Mode Format
17
Figure 3-8
Instruction and Data Pointer
Image in Memory 16-Bit
Real Mode Format
18
Figure 4-1
Intel386 SX CPU and
Intel387 SX Math
CoProcessor System
Configuration
25
Figure 5-1
Bus State Diagram
28
Figure 5-2
Non-Pipelined Read and
Write Cycles
29
Figure 5-3
Fastest Transition to and
from Pipelined Cycles
30
Figure 5-4
Pipelined Cycles with Wait
States
31
Figure 5-5
BUSY
and PEREQ Timing
Relationship
32
Figure 7-1a Typical Output Valid Delay
vs Load Capacitance at Max
Operating Temperature
37
Figure 7-1b Typical Output Slew Time vs
Load Capacitance at Max
Operating Temperature
37
Figure 7-1c Maximum I
CC
vs
Frequency
37
CONTENTS
PAGE
Figure 7-2
CPUCLK2 NUMCLK2
Waveform and
Measurement Points for
Input Output
38
Figure 7-3
Output Signals
38
Figure 7-4
Input and I O Signals
39
Figure 7-5
RESET Signal
39
Figure 7-6
Float from STEN
40
Figure 7-7
Other Parameters
40
TABLES
Table 1-1
Pin Cross Reference
Functional Grouping
5
Table 3-1
Condition Code
Interpretation
13
Table 3-2
Condition Code Interpretation
after FPREM and FPREM1
Instructions
14
Table 3-3
Condition Code Resulting
from Comparison
14
Table 3-4
Condition Code Defining
Operand Class
14
Table 3-5
Mapping Condition Codes to
Intel386 CPU Flag Bits
14
Table 3-6
Intel387 SX Math
CoProcessor Data Type
Representation in Memory
19
Table 3-7
CPU Interrupt Vectors
Reserve for Math
CoProcessor
20
Table 3-8
Intel387 SX Math
CoProcessor Exceptions
20
Table 4-1
Pin Summary
22
Table 4-2
Output Pin Status during
Reset
23
Table 4-3
Bus Cycle Definition
26
Table 6-1
Thermal Resistances
( C Watt) i
JC
and i
JA
33
Table 6-2
Maximum T
A
at Various
Airflows
33
Table 7-1
D C Specifications
34
Table 7-2a Timing Requirements of the
Bus Interface Unit
35
Table 7-2b Timing Requirements of the
Execution Unit
36
Table 7-2c Other AC Parameters
36
Table 8-1
Instruction Formats
41
4
4
Intel387
TM
SX MATH COPROCESSOR
1 0
PIN ASSIGNMENT
The Intel387 SX Math CoProcessor pinout as
viewed from the top side of the component is shown
in Figure 1-1 V
CC
and V
SS
(GND) connections must
be made to multiple pins The circuit board should
include V
CC
and V
SS
planes for power distribution
and all V
CC
and V
SS
pins must be connected to the
appropriate plane
NOTE
Pins identified as N C should remain completely
unconnected
240225 1
Figure 1-1 Intel387
TM
SX Math CoProcessor Pinout
Table 1-1 Pin Cross Reference
Functional Grouping
BUSY
36
D00
19
V
CC
4
V
SS
5
N C
1
PEREQ
56
D01
20
9
14
10
ERROR
35
D02
23
13
21
17
D03
8
22
25
18
ADS
47
D04
7
26
27
52
CMD0
48
D05
6
31
32
65
NPS1
44
D06
3
33
34
67
NPS2
45
D07
2
37
38
68
STEN
40
D08
24
39
42
W R
41
D09
28
43
55
READY
49
D10
29
46
60
READYO
57
D11
30
50
61
D12
16
58
63
D13
15
62
66
CKM
59
D14
12
64
CPUCLK2
54
D15
11
NUMCLK2
53
RESETIN
51
5
5