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January 1994

INTEL CORPORATION 1995

Order Number 240225-009

Intel387

MATH COPROCESSOR

New Automatic Power Management

Low Power Consumption
Typically 100 mA in Dynamic Mode
and 4 mA in Idle Mode

Socket Compatible with Intel387 Family
of Math CoProcessors

Hardware and Software Compatible
Supported by Over 2100 Commercial
Software Packages
10% to 15% Performance Increase
on Whetstone and Livermore
Benchmarks

Compatible with the Intel386

Microprocessor

Extends CPU Instruction Set to
Include Trigonometric Logarithmic
and Exponential

High Performance 80-Bit Internal
Architecture

Implements ANSI IEEE Standard
754-1985 for Binary Floating-Point
Arithmetic

Available in a 68-Pin PLCC Package

See Intel Packaging Specification Order

231369

The Intel387

SX Math CoProcessor is an extension to the Intel386

SX microprocessor architecture The

combination of the Intel387

SX with the Intel386

SX microprocessor dramatically increases the process-

ing speed of computer application software that utilizes high performance floating-point operations An internal
Power Management Unit enables the Intel387

SX to perform these floating-point operations while maintain-

ing very low power consumption for portable and desktop applications The internal Power Management Unit
effectively reduces power consumption by 95% when the device is idle

The Intel387

SX Math CoProcessor is available in a 68-pin PLCC package and is manufactured on Intel's

advanced 1 0 micron CHMOS IV technology

240225 � 22

Intel386 and Intel387 are trademarks of Intel Corporation

Intel387

SX Math CoProcessor

CONTENTS

PAGE

1 0 PIN ASSIGNMENT

1 1 Pin Description Table

2 0 FUNCTIONAL DESCRIPTION

2 1 Feature List

2 2 Math CoProcessor Architecture

2 3 Power Management

2 3 1 Dynamic Mode

2 3 2 Idle Mode

2 4 Compatibility

2 5 Performance

3 0 PROGRAMMING INTERFACE

3 1 Instruction Set

3 1 1 Data Transfer Instructions

3 1 2 Arithmetic Instructions

3 1 3 Comparison Instructions

3 1 4 Transcendental

Instructions

3 1 5 Load Constant Instructions

3 1 6 Processor Instructions

3 2 Register Set

3 2 1 Status Word (SW) Register

3 2 2 Control Word (CW)

3 2 3 Data Register

3 2 4 Tag Word (TW) Register

3 2 5 Instruction and Data

Pointers

3 3 Data Types

3 4 Interrupt Description

3 5 Exception Handling

3 6 Initialization

3 7 Processing Modes

3 8 Programming Support

CONTENTS

PAGE

4 0 HARDWARE SYSTEM

INTERFACE

4 1 Signal Description

4 1 1 Intel386 CPU Clock 2

(CPUCLK2)

4 1 2 Intel387 Math CoProcessor

Clock 2 (NUMCLK2)

4 1 3 Clocking Mode (CKM)

4 1 4 System Reset (RESETIN)

4 1 5 Processor Request

(PEREQ)

4 1 6 Busy Status (BUSY )

4 1 7 Error Status (ERROR )

4 1 8 Data Pins (D15 � D0)

4 1 9 Write Read Bus Cycle

(W R )

4 1 10 Address Stobe (ADS )

4 1 11 Bus Ready Input

(READY )

4 1 12 Ready Output

(READYO )

4 1 13 Status Enable (STEN)

4 1 14 Math CoProcessor Select 1

(NPS1 )

4 1 15 Math CoProcessor Select 2

(NPS2)

4 1 16 Command (CMD0 )

4 1 17 System Power (V

)

4 1 18 System Ground (V

)

4 2 System Configuration

4 3 Math CoProcessor Architecture

4 3 1 Bus Control Logic

4 3 2 Data Interface and Control

Unit

4 3 3 Floating Point Unit

4 3 4 Power Management Unit

CONTENTS

PAGE

4 4 Bus Cycles

4 4 1 Intel387 SX Math

CoProcessor Addressing

4 4 2 CPU Math CoProcessor

Synchronization

4 4 3 Synchronous Asynchronous

Modes

4 4 4 Automatic Bus Cycle

Termination

5 0 BUS OPERATION

5 1 Non-pipelined Bus Cycles

5 1 1 Write Cycle

5 1 2 Read Cycle

5 2 Pipelined Bus Cycles

5 3 Mixed Bus Cycles

5 4 BUSY

and PEREQ Timing

Relationship

6 0 PACKAGE SPECIFICATIONS

6 1 Mechanical Specifications

6 2 Thermal Specifications

CONTENTS

PAGE

7 0 ELECTRICAL

CHARACTERISTICS

7 1 Absolute Maximum Ratings

7 2 D C Characteristics

7 3 A C Characteristics

8 0 Intel387 SX MATH COPROCESSOR

INSTRUCTION SET

APPENDIX A

Intel387 SX MATH

COPROCESSOR COMPATIBILITY

A-1

A 1 8087 80287 Compatibility

A-1

A 1 1 General Differences

A-1

A 1 2 Exceptions

A-2

APPENDIX B

COMPATIBILITY

BETWEEN THE 80287 AND 8087
MATH COPROCESSOR

B-1

CONTENTS

PAGE

FIGURES

Figure 1-1

Intel387 SX Math
CoProcessor Pinout

Figure 2-1

Intel387 SX Math
CoProcessor Block
Diagram

Figure 3-1

Intel 386 SX CPU and
Intel387 Math CoProcessor
Register Set

Figure 3-2

Status Word

Figure 3-3

Control Word

Figure 3-4

Tag Word Register

Figure 3-5

Instruction and Data Pointer
Image in Memory 32-Bit
Protected Mode Format

Figure 3-6

Instruction and Data Pointer
Image in Memory 16-Bit
Protected Mode Format

Figure 3-7

Instruction and Data Pointer
Image in Memory 32-Bit
Real Mode Format

Figure 3-8

Instruction and Data Pointer
Image in Memory 16-Bit
Real Mode Format

Figure 4-1

Intel386 SX CPU and
Intel387 SX Math
CoProcessor System
Configuration

Figure 5-1

Bus State Diagram

Figure 5-2

Non-Pipelined Read and
Write Cycles

Figure 5-3

Fastest Transition to and
from Pipelined Cycles

Figure 5-4

Pipelined Cycles with Wait
States

Figure 5-5

BUSY

and PEREQ Timing

Relationship

Figure 7-1a Typical Output Valid Delay

vs Load Capacitance at Max
Operating Temperature

Figure 7-1b Typical Output Slew Time vs

Load Capacitance at Max
Operating Temperature

Figure 7-1c Maximum I

Frequency

CONTENTS

PAGE

Figure 7-2

CPUCLK2 NUMCLK2
Waveform and
Measurement Points for
Input Output

Figure 7-3

Output Signals

Figure 7-4

Input and I O Signals

Figure 7-5

RESET Signal

Figure 7-6

Float from STEN

Figure 7-7

Other Parameters

TABLES

Table 1-1

Pin Cross Reference
Functional Grouping

Table 3-1

Condition Code
Interpretation

Table 3-2

Condition Code Interpretation
after FPREM and FPREM1
Instructions

Table 3-3

Condition Code Resulting
from Comparison

Table 3-4

Condition Code Defining
Operand Class

Table 3-5

Mapping Condition Codes to
Intel386 CPU Flag Bits

Table 3-6

Intel387 SX Math
CoProcessor Data Type
Representation in Memory

Table 3-7

CPU Interrupt Vectors
Reserve for Math
CoProcessor

Table 3-8

Intel387 SX Math
CoProcessor Exceptions

Table 4-1

Pin Summary

Table 4-2

Output Pin Status during
Reset

Table 4-3

Bus Cycle Definition

Table 6-1

Thermal Resistances
( C Watt) i

and i

Table 6-2

Maximum T

at Various

Airflows

Table 7-1

D C Specifications

Table 7-2a Timing Requirements of the

Bus Interface Unit

Table 7-2b Timing Requirements of the

Execution Unit

Table 7-2c Other AC Parameters

Table 8-1

Instruction Formats

Intel387

SX MATH COPROCESSOR

1 0

PIN ASSIGNMENT

The Intel387 SX Math CoProcessor pinout as
viewed from the top side of the component is shown
in Figure 1-1 V

and V

(GND) connections must

be made to multiple pins The circuit board should

include V

and V

planes for power distribution

and all V

and V

pins must be connected to the

appropriate plane

NOTE

Pins identified as N C should remain completely
unconnected

240225 � 1

Figure 1-1 Intel387

SX Math CoProcessor Pinout

Table 1-1 Pin Cross Reference

Functional Grouping

BUSY

D00

N C

PEREQ

D01

ERROR

D02

D03

ADS

D04

CMD0

D05

NPS1

D06

NPS2

D07

STEN

D08

W R

D09

READY

D10

READYO

D11

D12

D13

CKM

D14

CPUCLK2

D15

NUMCLK2

RESETIN

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