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Intel 450KX/GX PCIset
The information in this document is subject to change.
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COPYRIGHT INTEL CORPORATION 1996
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Contents
Chapter 1
Intel 450KX/GX PCIset Overview
1.0 Intel 450KX PCIset ....................................................................................................................................5
2.0 Intel 450GX PCIset ....................................................................................................................................6
3.0 Host Bus Efficiency ..................................................................................................................................6
4.0 System Memory Map ................................................................................................................................7
4.1 Compatibility Area ...............................................................................................................................8
4.2 Extended Memory (ISA) .....................................................................................................................9
4.3 Extended Memory (EISA) .................................................................................................................10
4.4 Extended Memory (above 4 Gbytes) ................................................................................................12
4.5 System Management Mode (SMM) ..................................................................................................12
5.0 I/O Space (PB Only) ................................................................................................................................12
6.0 Memory Mapped I/O ...............................................................................................................................13
Chapter 2
82454KX/GX PCI Bridge (PB)
1.0 PB Signal Descriptions ..........................................................................................................................19
1.1 PB Signals .......................................................................................................................................19
1.2 Signal State During Reset ................................................................................................................25
2.0 PB Register Description ........................................................................................................................26
2.1 Initialization and Configuration ..........................................................................................................26
2.2 I/O Space Registers ..........................................................................................................................27
2.2.1 CONFADD--Configuration Address Register ........................................................................28
2.2.2 TRC--Turbo and Reset ControL ............................................................................................29
2.2.3 CONFDATA--Configuration Data Register ............................................................................30
2.3 PCI Configuration Space ..................................................................................................................30
2.4 PB PCI Configuration Registers .......................................................................................................32
2.4.1 VID--Vendor Identification Register .......................................................................................34
2.4.2 DID--Device Identification Register .......................................................................................34
2.4.3 PCICMD--PCI Command Register .......................................................................................34
2.4.4 PCISTS--PCI Status Register ...............................................................................................35
2.4.5 RID--Revision Identification Register ....................................................................................36
2.4.6 CLASSC--Class Code Register ............................................................................................36
2.4.7 CLSIZE--Cache Line Size Register ......................................................................................36
2.4.8 PLTMR--PCI Latency Timer ..................................................................................................37
2.4.9 HEADT--Header Type Register .............................................................................................37
2.4.10 BIST--Bist register ..............................................................................................................37
2.4.11 TSM--Top of System Memory Register ...............................................................................38
2.4.12 PDM--PCI Decode Mode ....................................................................................................38
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2.4.13 BDNUM--Bridge Device Number Register ..........................................................................39
2.4.14 PBNUM--PCI Bus Number Register ...................................................................................39
2.4.15 PSBNUM--Subordinate Bus Number Register ...................................................................40
2.4.16 PBC--PB Configuration Register .........................................................................................40
2.4.17 DCC--Deturbo Counter Register .........................................................................................41
2.4.18 CRWC--CPU Read/Write Control Register .........................................................................41
2.4.19 PRWC--PCI Read/Write Control .........................................................................................42
2.4.20 SMME--SMRAM Enable Register .......................................................................................43
2.4.21 VBAE--Video Buffer Area Enable Register .........................................................................43
2.4.22 PAM[0:6]--Programmable Attribute MAp Register ...............................................................44
2.4.23 ERRCMD--Error Reporting Command Register .................................................................45
2.4.24 ERRSTS--Error Reporting Status Register .........................................................................45
2.4.25 MGR--Memory Gap Range Register ..................................................................................46
2.4.26 MGUA--Memory Gap Upper Address Register ...................................................................46
2.4.27 PFB--PCI Frame Buffer Register .........................................................................................47
2.4.28 HMGSA--High Memory Gap Range Start Address Register ..............................................48
2.4.29 HMGEA--High Memory Gap End Address Register ...........................................................48
2.4.30 IOSR1--I/O Space Range 1 Register (82454GX Only) .......................................................49
2.4.31 PCIRSR--PCI Reset Register .............................................................................................49
2.4.32 IOSR2--I/O Space Range 2 Register (82454GX Only) .......................................................50
2.4.33 APICR--I/O APIC Range Register ......................................................................................50
2.4.34 CONFVR--Configuration Values Driven on Reset Register ................................................51
2.4.35 CSCONFV--Captured System Configuration Values Register ............................................52
2.4.36 SMMR--SMRAM Range Register .......................................................................................53
2.4.37 HBIOSR--High BIOS Range Register .................................................................................53
2.4.38 EXERRCMD--PB Extended Error Reporting Command Register ......................................53
2.4.39 EXERRSTS--PB Extended Error Reporting Status ............................................................55
2.4.40 PBRTMR--PB Retry Timers ................................................................................................56
3.0 PB Functional Description ....................................................................................................................57
3.1 Memory and I/O Map ........................................................................................................................57
3.1.1 Memory Address Map ............................................................................................................57
3.1.2 I/O Address Map ....................................................................................................................59
3.2 Host Bus Interface ............................................................................................................................60
3.3 PCI Bus Interface ..............................................................................................................................61
3.4 Data Integrity and Error Handling .....................................................................................................62
3.4.1 Host Bus Errors ......................................................................................................................62
3.4.2 PCI Bus Errors .......................................................................................................................62
3.4.2.1 PB Master Operation on PCI ....................................................................................63
3.4.2.2 PB Target Operation on PCI .....................................................................................63
3.5 Dual PB Architectures (82454GX Only) ............................................................................................65
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3.6 Peripheral Operation and Performance ............................................................................................68
3.6.1 Matching Peripherals to the 450KX/GX .................................................................................68
3.6.2 Distributing Peripherals Within the I/O Subsystem .................................................................69
3.6.3 PCI-to-PCI Bridges ................................................................................................................69
3.6.4 BIOS Performance Tuning ......................................................................................................69
3.7 Clock, Reset, and Configuration .......................................................................................................70
3.7.1 System clocking .....................................................................................................................70
3.7.1.1 Host Bus Clock .........................................................................................................70
3.7.1.2 PCI Clock ..................................................................................................................71
3.7.2 System Reset .........................................................................................................................71
3.7.3 System Initialization ...............................................................................................................72
3.7.4 Dual PB Configuration (82454GX only) .................................................................................72
3.7.5 Using the 82379AB SIO.A PCI-to-ISA Bridge with the 450KX/GX .........................................73
3.8 Host to PCI Bus Command Translation ............................................................................................76
3.9 PCI to Host Bus Command Translation ............................................................................................77
4.0 PB Pinout and Package Information .....................................................................................................79
4.1 Pin Assignment .................................................................................................................................79
4.2 Package Information .........................................................................................................................87
Chapter 3
Memory Controller (MC)
1.0 MC Signal Description ...........................................................................................................................93
1.1 DC Signals ........................................................................................................................................93
1.2 DP Signals ........................................................................................................................................96
1.3 MIC Signals ......................................................................................................................................98
1.4 Signal State During Reset ..............................................................................................................100
2.0 MC Register Description ......................................................................................................................101
2.1 Initialization and Configuration ........................................................................................................101
2.2 I/O Space Registers ........................................................................................................................102
2.2.1 CONFADD--Configuration Address Register ......................................................................103
2.2.2 CONFDATA--Configuration Data Register ..........................................................................103
2.3 MC Configuration Registers ............................................................................................................104
2.3.1 VID--Vendor Identification Register .....................................................................................105
2.3.2 DID--Device Identification Register .....................................................................................105
2.3.3 PCICMD--PCI Command Register .....................................................................................106
2.3.4 PCISTS--PCI Status Register .............................................................................................106
2.3.5 RID--Revision Identification Register ..................................................................................106
2.3.6 CLASSC--Class Code Register ..........................................................................................107
2.3.7 BASEADD--MC Base Address Register (450GX only) .......................................................107
2.3.8 CDNUM--Controller Device Number Register ....................................................................108
2.3.9 CMD--Command Register ..................................................................................................108
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