Intel
82802AB/82802AC
Firmware Hub (FWH)
Datasheet
November 2000
Document Number:
290658-004
R
Intel
82802AB/AC Firmware Hub
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2
Datasheet
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82802AB/AC Firmware Hub (FWH) may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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2
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2
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2
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Copyright Intel Corporation 1999-2001
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Datasheet 3
Contents
1.
Architectural Overview ................................................................................................................. 9
1.1.
Interface Overview........................................................................................................... 9
1.1.1.
Intel Firmware Hub Interface....................................................................... 10
1.1.2.
Address/Address-Multiplexed Interface ...................................................... 10
1.2.
Nonvolatile Flash Memory Core .................................................................................... 10
2.
Pinout Configurations................................................................................................................. 13
2.1.
Pin Descriptions............................................................................................................. 14
3.
Interface Operation Description ................................................................................................. 17
3.1.
Read 17
3.2.
Write 17
3.3.
Output Disable............................................................................................................... 17
3.4.
Reset 17
3.5.
Operational Effects of Hardware Write-Protect Pins TBL# and WP# ........................... 18
4.
Functional Descriptions.............................................................................................................. 19
4.1.
Read Array Command................................................................................................... 21
4.2.
Read Identifier Codes Command.................................................................................. 21
4.3.
Read Status Register Command................................................................................... 21
4.4.
Clear Status Register Command................................................................................... 21
4.5.
Block Erase Command ................................................................................................. 22
4.6.
Program Command....................................................................................................... 22
4.7.
Block Erase Suspend Command .................................................................................. 23
4.8.
Program Suspend Comand........................................................................................... 23
4.9.
Register Based Locking, General-Purpose Input, and Random Number Generator
Registers 23
4.9.1.
T_BLOCK_LK and T_MINUSxx_LK -- Block-Locking Registers ............... 25
4.9.2.
General-Purpose Input Register ................................................................. 26
4.9.2.1.
GPI_REG -- General-Purpose Input Register ............................... 26
4.9.3.
Random Number Generator Registers ....................................................... 27
4.9.3.1.
RNG Hardware Status Register ..................................................... 27
4.9.3.2.
RNG Data Status Register ............................................................. 27
4.9.3.3.
RNG Data Register......................................................................... 28
4.10.
Using the Random Number Generator ......................................................................... 28
4.11.
Detecting and Initializing the RNG Device..................................................................... 28
4.11.1.
Detecting the RNG Device .......................................................................... 28
4.11.2.
Initializing the RNG Device.......................................................................... 29
4.11.3.
Selecting Appropriate FWH IDs and Densities ........................................... 29
4.11.4.
Mapping FWH Devices onto Memory Map ................................................. 30
4.11.5.
Paging FWH Devices for Greater Than 4 MB of FWH Memory ................. 30
4.11.6.
Programming Multiple FWH Devices.......................................................... 30
4.12.
CUI Automation Flowcharts........................................................................................... 31
5.
Electrical Specifications ............................................................................................................. 33
5.1.
Absolute Maximum Ratings........................................................................................... 33
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Datasheet
5.2.
Operating Conditions .....................................................................................................33
5.2.1.
Interface DC Input/Output Specifications ....................................................34
5.2.2.
Interface AC Input/Output Specifications.....................................................36
5.2.3.
Intel FWH Interface AC Timing Specifications ............................................37
5.2.3.1.
Clock Specification..........................................................................37
5.2.3.2.
Signal Timing Parameters...............................................................38
5.3.
Block Programming Times ............................................................................................40
5.4.
Intel Firmware Hub Interface..........................................................................................40
5.4.1.
Intel FWH Interface Cycles..........................................................................40
5.4.1.1.
Read Cycle Sequence.....................................................................40
5.4.1.2.
Single-Byte Read Waveforms.........................................................42
5.4.1.3.
Write Cycle Sequence.....................................................................42
5.4.1.4.
Write Waveforms ............................................................................43
5.4.1.5.
Response To Invalid Fields.............................................................43
5.4.1.6.
Abort Operations .............................................................................44
5.4.1.7.
Intel FWH Cycle Timing Information ...............................................44
5.5.
RNG Parameters ...........................................................................................................45
6.
PROM Programming Specifications ...........................................................................................47
6.1.
Programming ("A/A Mux") Mode Operation ...................................................................47
6.2.
Bus Operation ................................................................................................................47
6.2.1.
Output Disable/Enable.................................................................................47
6.2.2.
Row/Column Addresses ..............................................................................47
6.2.3.
Read Operation ...........................................................................................47
6.2.4.
Read Identifier Codes Operation .................................................................48
6.2.5.
Write Operation ...........................................................................................48
6.3.
Command Definitions ....................................................................................................48
6.4.
Electrical Characteristics in A/A Mux Mode ...................................................................48
6.4.1.
Reset Operations.........................................................................................49
6.4.2.
AC Waveforms for Reset Operations..........................................................49
6.4.3.
A/A Mux Read-Only Operations
(1,3)
.............................................................49
6.4.4.
A/A Mux Write Operations
(1,2)
.....................................................................51
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Figures
Figure 1.
Simplified Block Diagram ..................................................................................... 8
Figure 2.
Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11
Figure 3.
Intel FWH Boot-Configuration System Memory Map......................................... 11
Figure 4.
32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13
Figure 5.
40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13
Figure 6.
Automated Block Erase Flowchart..................................................................... 31
Figure 7.
Clock Waveform ................................................................................................ 37
Figure 8.
Output Timing Parameters................................................................................. 38
Figure 9.
Input Timing Parameters ................................................................................... 39
Figure 10.
FWH Single-Byte Read Waveforms .................................................................. 42
Figure 11.
Write Waveforms ............................................................................................... 43
Figure 12.
Intel FWH Output Timing Parameters ............................................................... 45
Figure 13.
Intel FWH Input Timing Parameters .................................................................. 46
Figure 14.
A/A Mux Read Timing Diagram ......................................................................... 50
Figure 15.
A/A Mux Write Timing Diagram ......................................................................... 52
Tables
Table 1.
Pin Descriptions ................................................................................................. 14
Table 2.
Command Definitions......................................................................................... 19
Table 3.
Status Register Definition .................................................................................. 20
Table 4.
Identifier Codes.................................................................................................. 21
Table 5.
Intel Firmware Hub Register Configuration Map................................................ 24
Table 6.
Register-Based Locking Value Definitions......................................................... 25
Table 7.
Temperature and VCC....................................................................................... 33
Table 8.
Intel FWH Interface DC Input/Output Specifications.......................................... 34
Table 9.
Power Supply Specifications -- All Interfaces ................................................... 35
Table 10.
Intel FWH Interface AC Input/Output Specifications.......................................... 36
Table 11.
Clock Specification............................................................................................. 37
Table 12.
Signal Timing Parameters.................................................................................. 38
Table 13.
Interface Measurement Condition Parameters .................................................. 39
Table 14.
AC Waveform for Reset Operation.................................................................... 39
Table 15.
Programming Times .......................................................................................... 40
Table 16.
FWH Read Cycle ............................................................................................... 41
Table 17.
FWH Write Cycle ............................................................................................... 42
Table 18.
Signal Timing Parameters.................................................................................. 44
Table 19.
RNG Timing Characteristics .............................................................................. 45
Table 20.
RNG Statistical Characteristics.......................................................................... 45
Table 21.
Bus Operations .................................................................................................. 48
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