Электронный компонент: IntelCeleron

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Intel

�

Celeron

�

Processor

� Low Power/Ultra Low Power

300 MHz (ULP) and 400A MHz (LP) Processor in a BGA2 Package

Datasheet

Product Features

s

300/100 MHz processor core/bus
speed at 1.1 V (Ultra Low Power)

s

400A/100 MHz processor core/bus
speed at 1.35 V (Low Power)

s

Supports the Intel Architecture with
Dynamic Execution

s

On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache

s

On-die second level cache (128-Kbyte)

s

Integrated GTL+ termination

s

On-die thermal diode

s

Integrated math co-processor

s

Power Management Features

-- Quick Start and Deep Sleep modes

provide low-power dissipation

s

Fully compatible with previous Intel
microprocessors

-- Binary compatible with all applications

-- Support for MMXTM technology

-- Support for Streaming SIMD Extensions

s

BGA2 packaging technology

-- Supports thin form factor designs

-- Exposed die enables efficient heat

dissipation

Document Number: 273509-001

October 2001

2

Datasheet

Information in this document is provided in connection with Intel

�

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

�

Celeron

�

Processor � Low Power and Intel

�

Celeron

�

Processor � Ultra Low Power may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available on request.

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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Copyright � Intel Corporation, 2001

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Datasheet

3

Intel

�

Celeron

�

Processor � LP/ULP

Contents

1.0

Introduction.................................................................................................................................... 9

1.1

Overview ............................................................................................................................. 10

1.2

Terminology ........................................................................................................................ 10

1.3

References .........................................................................................................................11

2.0

Intel

�

Celeron

�

Processor � LP/ULP Features ......................................................................... 11

2.1

Features in the Intel

�

Celeron

�

Processor � LP/ULP ......................................................... 11

2.1.1

On-die GTL+ Termination ...................................................................................... 11

2.1.2

Streaming SIMD Extensions ..................................................................................11

2.2

Power Management............................................................................................................ 12
2.2.1

Clock Control Architecture ..................................................................................... 12

2.2.2

Normal State .......................................................................................................... 12

2.2.3

Auto Halt State....................................................................................................... 12

2.2.4

Stop Grant State .................................................................................................... 13

2.2.5

Quick Start State.................................................................................................... 14

2.2.6

HALT/Grant Snoop State ....................................................................................... 14

2.2.7

Sleep State ............................................................................................................14

2.2.8

Deep Sleep State................................................................................................... 15

2.2.9

Operating System Implications of Low-power States ............................................15

2.2.10 GTL+ Signals ......................................................................................................... 15
2.2.11 Intel

�

Celeron

�

Processor � LP/ULP CPUID......................................................... 16

3.0

Electrical Specifications ............................................................................................................. 17

3.1

Processor System Signals .................................................................................................. 17
3.1.1

Power Sequencing Requirements ......................................................................... 18

3.1.2

Test Access Port (TAP) Connection ...................................................................... 18

3.1.3

Catastrophic Thermal Protection ........................................................................... 19

3.1.4

Unused Signals......................................................................................................19

3.1.5

Signal State in Low-power States .......................................................................... 19
3.1.5.1

System Bus Signals ............................................................................... 19

3.1.5.2

CMOS and Open-drain Signals ............................................................. 19

3.1.5.3

Other Signals .........................................................................................20

3.2

Power Supply Requirements .............................................................................................. 20
3.2.1

Decoupling Recommendations .............................................................................. 20

3.2.2

Voltage Planes....................................................................................................... 20

3.3

System Bus Clock and Processor Clocking........................................................................ 21

3.4

Maximum Ratings ............................................................................................................... 21

3.5

DC Specifications ............................................................................................................... 23

3.6

AC Specifications................................................................................................................ 26
3.6.1

System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........ 26

4.0

System Signal Simulations......................................................................................................... 35

4.1

System Bus Clock (BCLK) and PICCLK AC Signal Quality Specifications ........................35

4.2

GTL+ AC Signal Quality Specifications .............................................................................. 36

4.3

Non-GTL+ Signal Quality Specifications............................................................................. 40
4.3.1

PWRGOOD Signal Quality Specifications ............................................................. 40

Intel

�

Celeron

�

Processor � LP/ULP

4

Datasheet

5.0

Mechanical Specifications.......................................................................................................... 41

5.1

Surface-mount BGA2 Package Dimensions....................................................................... 41

5.2

Signal Listings..................................................................................................................... 43

6.0

Thermal Specifications ............................................................................................................... 51

6.1

Thermal Diode .................................................................................................................... 52

7.0

Processor Initialization and Configuration ............................................................................... 53

7.1

Description.......................................................................................................................... 53
7.1.1

Quick Start Enable................................................................................................. 53

7.1.2

System Bus Frequency.......................................................................................... 53

7.1.3

APIC Enable .......................................................................................................... 53

7.2

Clock Frequencies and Ratios............................................................................................ 53

8.0

Processor Interface ..................................................................................................................... 54

8.1

Alphabetical Signal Reference............................................................................................ 54
8.1.1

A[35:3]# (I/O - GTL+) ............................................................................................. 54

8.1.2

A20M# (I - 1.5 V Tolerant) ..................................................................................... 54

8.1.3

ADS# (I/O - GTL+) ................................................................................................. 54

8.1.4

AERR# (I/O - GTL+) .............................................................................................. 54

8.1.5

AP[1:0]# (I/O - GTL+) ............................................................................................ 54

8.1.6

BCLK (I - 2.5 V Tolerant) ....................................................................................... 55

8.1.7

BERR# (I/O - GTL+) .............................................................................................. 55

8.1.8

BINIT# (I/O - GTL+) ............................................................................................... 55

8.1.9

BNR# (I/O - GTL+)................................................................................................. 55

8.1.10 BP[3:2]# (I/O - GTL+) ............................................................................................ 56
8.1.11 BPM[1:0]# (I/O - GTL+) ......................................................................................... 56
8.1.12 BPRI# (I - GTL+).................................................................................................... 56
8.1.13 BREQ0# (I/O - GTL+) ............................................................................................ 56
8.1.14 BSEL[1:0] (I � 3.3 V Tolerant)................................................................................ 56
8.1.15 CLKREF (Analog) .................................................................................................. 56
8.1.16 CMOSREF (Analog) .............................................................................................. 57
8.1.17 D[63:0]# (I/O - GTL+)............................................................................................. 57
8.1.18 DBSY# (I/O - GTL+) .............................................................................................. 57
8.1.19 DEFER# (I - GTL+) ................................................................................................ 57
8.1.20 DEP[7:0]# (I/O - GTL+) .......................................................................................... 57
8.1.21 DRDY# (I/O - GTL+) .............................................................................................. 57
8.1.22 EDGCTRLP (Analog)............................................................................................. 57
8.1.23 FERR# (O - 1.5 V Tolerant Open-drain) ................................................................ 58
8.1.24 FLUSH# (I - 1.5 V Tolerant)................................................................................... 58
8.1.25 HIT# (I/O - GTL+), HITM# (I/O - GTL+) ................................................................. 58
8.1.26 IERR# (O - 1.5 V Tolerant Open-drain) ................................................................. 58
8.1.27 IGNNE# (I - 1.5 V Tolerant) ................................................................................... 58
8.1.28 INIT# (I - 1.5 V Tolerant)........................................................................................ 58
8.1.29 INTR (I - 1.5 V Tolerant) ........................................................................................ 59
8.1.30 LINT[1:0] (I - 1.5 V Tolerant).................................................................................. 59
8.1.31 LOCK# (I/O - GTL+) .............................................................................................. 59
8.1.32 NMI (I - 1.5 V Tolerant) .......................................................................................... 59
8.1.33 PICCLK (I - 2.5 V Tolerant).................................................................................... 59
8.1.34 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) .......................................................... 60

Datasheet

5

Intel

�

Celeron

�

Processor � LP/ULP

8.1.35 PLL1, PLL2 (Analog) ............................................................................................. 60
8.1.36 PRDY# (O - GTL+) ................................................................................................ 60
8.1.37 PREQ# (I - 1.5 V Tolerant) .................................................................................... 60
8.1.38 PWRGOOD (I - 2.5 V Tolerant) ............................................................................. 60
8.1.39 REQ[4:0]# (I/O - GTL+).......................................................................................... 61
8.1.40 RESET# (I - GTL+) ................................................................................................ 61
8.1.41 RP# (I/O - GTL+) ................................................................................................... 61
8.1.42 RS[2:0]# (I - GTL+) ................................................................................................ 61
8.1.43 RSP# (I - GTL+)..................................................................................................... 61
8.1.44 RSVD (TBD) .......................................................................................................... 62
8.1.45 RTTIMPEDP (Analog) ........................................................................................... 62
8.1.46 SLP# (I - 1.5 V Tolerant) ........................................................................................ 62
8.1.47 SMI# (I - 1.5 V Tolerant) ........................................................................................ 62
8.1.48 STPCLK# (I - 1.5 V Tolerant)................................................................................. 62
8.1.49 TCK (I - 1.5 V Tolerant) .........................................................................................62
8.1.50 TDI (I - 1.5 V Tolerant) ........................................................................................... 62
8.1.51 TDO (O - 1.5 V Tolerant Open-drain) .................................................................... 63
8.1.52 TESTHI (I - 1.5 V Tolerant) .................................................................................... 63
8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................63
8.1.54 THERMDA, THERMDC (Analog)........................................................................... 63
8.1.55 TMS (I - 1.5 V Tolerant) .........................................................................................63
8.1.56 TRDY# (I - GTL+) .................................................................................................. 63
8.1.57 TRST# (I - 1.5 V Tolerant) ..................................................................................... 63
8.1.58 VID[4:0] (O � Open-drain)...................................................................................... 63
8.1.59 VREF (Analog)....................................................................................................... 64

8.2

Signal Summaries............................................................................................................... 65

9.0

PLL RLC Filter Specification ......................................................................................................67

9.1

Introduction .........................................................................................................................67

9.2

Filter Specification .............................................................................................................. 67

9.3

Recommendation for Low Power Systems ......................................................................... 69

9.4

Comments .......................................................................................................................... 70

Document Outline

• Intel� Celeron� Processor � Low Power/Ultra Low Power
• Contents
  • Figures
    • Figure 1. Signal Groups of an Intel� Celeron� Processor � LP/ULP System
    • Figure 2. Clock Control States
    • Figure 3. Vcc Ramp Rate Requirement
    • Figure 4. PLL RLC Filter
    • Figure 5. PICCLK/TCK Clock Timing Waveform
    • Figure 6. BCLK Timing Waveform
    • Figure 7. Valid Delay Timings
    • Figure 8. Setup and Hold Timings
    • Figure 9. Cold/Warm Reset and Configuration Timings
    • Figure 10. Power-on Reset Timings
    • Figure 11. Test Timings (Boundary Scan)
    • Figure 12. Test Reset Timings
    • Figure 13. Quick Start/Deep Sleep Timing
    • Figure 14. Stop Grant/Sleep/Deep Sleep Timing
    • Figure 15. BCLK/PICCLK Generic Clock Waveform
    • Figure 16. Low to High, GTL+ Receiver Ringback Tolerance
    • Figure 17. High to Low, GTL+ Receiver Ringback Tolerance
    • Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform
    • Figure 19. Surface-mount BGA2 Package - Top and Side View
    • Figure 20. Surface-mount BGA2 Package - Bottom View
    • Figure 21. Pin/Ball Map - Top View
    • Figure 22. PWRGOOD Relationship at Power On
    • Figure 23. PLL Filter Specifications
  • Tables
    • Table 1. Clock State Characteristics
    • Table 2. Intel� Celeron� Processor � LP/ULP CPUID
    • Table 3. Intel� Celeron� Processor � LP/ULP CPUID Cache and TLB Descriptors
    • Table 4. System Signal Groups 
    • Table 5. Recommended Resistors for Intel� Celeron� Processor � LP/ULP Signals
    • Table 6. Intel� Celeron� Processor � LP/ULP Absolute Maximum Ratings
    • Table 7. Power Specifications
    • Table 8. GTL+ Signal Group DC Specifications
    • Table 9. GTL+ Bus DC Specifications
    • Table 10. Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
    • Table 11. System Bus Clock AC Specifications
    • Table 12. Supported Processor Frequencies
    • Table 13. GTL+ Signal Groups AC Specifications
    • Table 14. CMOS and Open-drain Signal Groups AC Specifications
    • Table 15. Reset Configuration AC Specifications
    • Table 16. APIC Bus Signal AC Specifications
    • Table 17. TAP Signal AC Specifications
    • Table 18. Quick Start/Deep Sleep AC Specifications
    • Table 19. Stop Grant/Sleep/Deep Sleep AC Specifications
    • Table 20. BCLK Signal Quality Specification
    • Table 21. PICCLK Signal Quality Specifications
    • Table 22. GTL+ Signal Group Ringback Specification
    • Table 23. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
    • Table 24. Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
    • Table 25. Surface-mount BGA2 Package Specifications
    • Table 26. Signal Listing in Order by Pin/Ball Number (Sheet 3 of 3)
    • Table 27. Signal Listing in Order by Signal Name (Sheet 3 of 3)
    • Table 28. Voltage and No-Connect Pin/Ball Locations
    • Table 29. Power Specifications for the Intel� Celeron� Processor � LP/ULP
    • Table 30. Thermal Diode Interface
    • Table 31. Thermal Diode Specifications
    • Table 32. BSEL[1:0] Encoding
    • Table 33. Voltage Identification Encoding
    • Table 34. Input Signals 
    • Table 35. Output Signals
    • Table 36. Input/Output Signals (Single Driver) 
    • Table 37. Input/Output Signals (Multiple Driver)
    • Table 38. PLL Filter Inductor Recommendations
    • Table 39. PLL Filter Capacitor Recommendations
    • Table 40. PLL Filter Resistor Recommendations
  • Revision History
• 1.0 Introduction
  • 1.1 Overview
  • 1.2 Terminology
  • 1.3 References
• 2.0 Intel� Celeron� Processor � LP/ULP Features
  • 2.1 Features in the Intel� Celeron� Processor � LP/ULP
    • 2.1.1 On-die GTL+ Termination
    • 2.1.2 Streaming SIMD Extensions
  • 2.2 Power Management
    • 2.2.1 Clock Control Architecture
    • 2.2.2 Normal State
    • 2.2.3 Auto Halt State
    • 2.2.4 Stop Grant State
    • 2.2.5 Quick Start State
    • 2.2.6 HALT/Grant Snoop State
    • 2.2.7 Sleep State
    • 2.2.8 Deep Sleep State
    • 2.2.9 Operating System Implications of Low-power States
    • 2.2.10 GTL+ Signals
    • 2.2.11 Intel� Celeron� Processor � LP/ULP CPUID
• 3.0 Electrical Specifications
  • 3.1 Processor System Signals
    • 3.1.1 Power Sequencing Requirements
    • 3.1.2 Test Access Port (TAP) Connection
    • 3.1.3 Catastrophic Thermal Protection
    • 3.1.4 Unused Signals
    • 3.1.5 Signal State in Low-power States
      • 3.1.5.1 System Bus Signals
      • 3.1.5.2 CMOS and Open-drain Signals
      • 3.1.5.3 Other Signals
  • 3.2 Power Supply Requirements
    • 3.2.1 Decoupling Recommendations
    • 3.2.2 Voltage Planes
  • 3.3 System Bus Clock and Processor Clocking
  • 3.4 Maximum Ratings
  • 3.5 DC Specifications
  • 3.6 AC Specifications
    • 3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications
• 4.0 System Signal Simulations
  • 4.1 System Bus Clock (BCLK) and PICCLK AC Signal Quality Specifications
  • 4.2 GTL+ AC Signal Quality Specifications
  • 4.3 Non-GTL+ Signal Quality Specifications
    • 4.3.1 PWRGOOD Signal Quality Specifications
• 5.0 Mechanical Specifications
  • 5.1 Surface-mount BGA2 Package Dimensions
  • 5.2 Signal Listings
• 6.0 Thermal Specifications
  • 6.1 Thermal Diode
• 7.0 Processor Initialization and Configuration
  • 7.1 Description
    • 7.1.1 Quick Start Enable
    • 7.1.2 System Bus Frequency
    • 7.1.3 APIC Enable
  • 7.2 Clock Frequencies and Ratios
• 8.0 Processor Interface
  • 8.1 Alphabetical Signal Reference
    • 8.1.1 A[35:3]# (I/O - GTL+)
    • 8.1.2 A20M# (I - 1.5 V Tolerant)
    • 8.1.3 ADS# (I/O - GTL+)
    • 8.1.4 AERR# (I/O - GTL+)
    • 8.1.5 AP[1:0]# (I/O - GTL+)
    • 8.1.6 BCLK (I - 2.5 V Tolerant)
    • 8.1.7 BERR# (I/O - GTL+)
    • 8.1.8 BINIT# (I/O - GTL+)
    • 8.1.9 BNR# (I/O - GTL+)
    • 8.1.10 BP[3:2]# (I/O - GTL+)
    • 8.1.11 BPM[1:0]# (I/O - GTL+)
    • 8.1.12 BPRI# (I - GTL+)
    • 8.1.13 BREQ0# (I/O - GTL+)
    • 8.1.14 BSEL[1:0] (I � 3.3 V Tolerant)
    • 8.1.15 CLKREF (Analog)
    • 8.1.16 CMOSREF (Analog)
    • 8.1.17 D[63:0]# (I/O - GTL+)
    • 8.1.18 DBSY# (I/O - GTL+)
    • 8.1.19 DEFER# (I - GTL+)
    • 8.1.20 DEP[7:0]# (I/O - GTL+)
    • 8.1.21 DRDY# (I/O - GTL+)
    • 8.1.22 EDGCTRLP (Analog)
    • 8.1.23 FERR# (O - 1.5 V Tolerant Open-drain)
    • 8.1.24 FLUSH# (I - 1.5 V Tolerant)
    • 8.1.25 HIT# (I/O - GTL+), HITM# (I/O - GTL+)
    • 8.1.26 IERR# (O - 1.5 V Tolerant Open-drain)
    • 8.1.27 IGNNE# (I - 1.5 V Tolerant)
    • 8.1.28 INIT# (I - 1.5 V Tolerant)
    • 8.1.29 INTR (I - 1.5 V Tolerant)
    • 8.1.30 LINT[1:0] (I - 1.5 V Tolerant)
    • 8.1.31 LOCK# (I/O - GTL+)
    • 8.1.32 NMI (I - 1.5 V Tolerant)
    • 8.1.33 PICCLK (I - 2.5 V Tolerant)
    • 8.1.34 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain)
    • 8.1.35 PLL1, PLL2 (Analog)
    • 8.1.36 PRDY# (O - GTL+)
    • 8.1.37 PREQ# (I - 1.5 V Tolerant)
    • 8.1.38 PWRGOOD (I - 2.5 V Tolerant)
    • 8.1.39 REQ[4:0]# (I/O - GTL+)
    • 8.1.40 RESET# (I - GTL+)
    • 8.1.41 RP# (I/O - GTL+)
    • 8.1.42 RS[2:0]# (I - GTL+)
    • 8.1.43 RSP# (I - GTL+)
    • 8.1.44 RSVD (TBD)
    • 8.1.45 RTTIMPEDP (Analog)
    • 8.1.46 SLP# (I - 1.5 V Tolerant)
    • 8.1.47 SMI# (I - 1.5 V Tolerant)
    • 8.1.48 STPCLK# (I - 1.5 V Tolerant)
    • 8.1.49 TCK (I - 1.5 V Tolerant)
    • 8.1.50 TDI (I - 1.5 V Tolerant)
    • 8.1.51 TDO (O - 1.5 V Tolerant Open-drain)
    • 8.1.52 TESTHI (I - 1.5 V Tolerant)
    • 8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)
    • 8.1.54 THERMDA, THERMDC (Analog)
    • 8.1.55 TMS (I - 1.5 V Tolerant)
    • 8.1.56 TRDY# (I - GTL+)
    • 8.1.57 TRST# (I - 1.5 V Tolerant)
    • 8.1.58 VID[4:0] (O � Open-drain)
    • 8.1.59 VREF (Analog)
  • 8.2 Signal Summaries
• 9.0 PLL RLC Filter Specification
  • 9.1 Introduction
  • 9.2 Filter Specification
  • 9.3 Recommendation for Low Power Systems
  • 9.4 Comments