Intel

Celeron

Processor for the PGA370

Socket up to 1.40 GHz on 0.13 Micron

Process

Datasheet

Product Features

The Intel

Celeron

processor is designed for uni-processor based Value PC desktops and is binary

compatible with previous generation Intel architecture processors. The Intel Celeron

processor provides

good performance for applications running on advanced operating systems such as Windows* 95/98,
WindowsNT*, Windows* 2000, WindowsXP* and UNIX*. This is achieved by integrating the best
attributes of Intel processors--the dynamic execution performance of the P6 microarchitecture plus the

capabilities of MMXTM technology--bringing a balanced level of performance to the Value PC market
segment. The Intel Celeron processor offers the dependability you would expect from Intel at an
exceptional value. Systems based on Intel Celeron processors also include the latest features to simplify

system management and lower the cost of ownership for small business and home environments.

Available at 1.4 GHz, 1.30 GHz, 1.20 GHz,

1.10A GHz, 1A GHz and 900 MHz with

100 MHz system bus

256 KB on-die Level 2 (L2) cache with Error

Correcting Code (ECC))

Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and

dedicated internal high-speed cache bus

Internet Streaming SIMD Extensions for

enhanced video, sound and 3D performance

Binary compatible with applications running

on previous members of the Intel

microprocessor line

Dynamic execution micro architecture

Power Management capabilities

--System Management mode
--Multiple low-power states

Optimized for 32-bit applications running on

advanced 32-bit operating systems

Flip Chip Pin Grid Array (FC-PGA2) packaging

technology

Integrated high performance 16 KB instruction

and 16 KB data, nonblocking, level one cache

Integrated Full Speed level two cache allows for

low latency on read/store operations

Error-correcting code for System Bus data

May 2002

Order Number:

298596-004

Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

Celeron

processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, Celeron, MMX, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Contents

1.0

Introduction.........................................................................................................................9
1.1

Terminology.........................................................................................................10
1.1.1

Package and Processor Terminology ....................................................10

1.1.2

Processor Naming Convention...............................................................11

1.2

Related Documents.............................................................................................12

2.0

Electrical Specifications....................................................................................................13
2.1

Processor System Bus and V

REF .......................................................................................... 13

2.2

Clock Control and Low Power States..................................................................14
2.2.1

Normal State--State 1 ...........................................................................15

2.2.2

AutoHALT Powerdown State--State 2...................................................15

2.2.3

Stop-Grant State--State 3 .....................................................................15

2.2.4

HALT/Grant Snoop State--State 4 ........................................................15

2.2.5

Sleep State--State 5..............................................................................16

2.2.6

Deep Sleep State--State 6 ....................................................................16

2.2.7

Clock Control..........................................................................................17

2.3

Power and Ground Pins ......................................................................................17
2.3.1

Phase Lock Loop (PLL) Power...............................................................17

2.4

Decoupling Guidelines ........................................................................................18
2.4.1

Processor VCC

CORE

Decoupling............................................................18

2.5

Processor System Bus Clock and Processor Clocking .......................................19

2.6

Voltage Identification ...........................................................................................19

2.7

Processor System Bus Unused Pins...................................................................21

2.8

Processor System Bus Signal Groups ................................................................22
2.8.1

Asynchronous vs. Synchronous for System Bus Signals.......................23

2.8.2

System Bus Frequency Select Signals ..................................................24

2.9

Test Access Port (TAP) Connection....................................................................25

2.10

Maximum Ratings................................................................................................25

2.11

Processor Voltage Level Specifications ..............................................................25

2.12

AGTL System Bus Specifications........................................................................30

2.13

System Bus Timing Specifications ......................................................................31

3.0

Signal Quality Specifications ............................................................................................41
3.1

BCLK/BCLK# & PICCLK Signal Quality Specifications and

Measurement Guidelines ....................................................................................41

3.2

AGTL Signal Quality Specifications and Measurement Guidelines.....................42
3.2.1

Overshoot/Undershoot Guidelines .........................................................43

3.2.2

Overshoot/Undershoot Magnitude .........................................................44

3.2.3

Overshoot/Undershoot Pulse Duration...................................................44

3.2.4

Activity Factor.........................................................................................44

3.2.5

Reading Overshoot/Undershoot Specification Tables............................45

3.2.6

Determining if a System Meets the Overshoot/Undershoot

Specifications .........................................................................................46

3.3

Non-AGTL Signal Quality Specifications and Measurement Guidelines.............47
3.3.1

Overshoot/Undershoot Guidelines .........................................................48

3.3.2

Ringback Specification ...........................................................................48

3.3.3

Settling Limit Guideline...........................................................................49

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Datasheet

3.4

VTT_PWRGD Signal Quality Specification ......................................................... 49
3.4.1

Transition region .................................................................................... 49

3.4.2

Transition time........................................................................................ 50

3.4.3

Noise ...................................................................................................... 50

4.0

Thermal Specifications and Design Considerations......................................................... 51
4.1

Thermal Specifications........................................................................................ 51
4.1.1

THERMTRIP# Requirement................................................................... 51

4.1.2

Thermal Diode........................................................................................ 52

4.2

Thermal Metrology .............................................................................................. 52

5.0

Mechanical Specifications................................................................................................ 53
5.1

FC-PGA2 Mechanical Specifications .................................................................. 53

5.2

Recommended Mechanical Keep-Out Zones ..................................................... 55

5.3

Processor Markings ............................................................................................ 56

5.4

Processor Signal Listing...................................................................................... 57

6.0

Boxed Processor Specifications....................................................................................... 68
6.1

Mechanical Specifications................................................................................... 68
6.1.1

Mechanical Specifications for the FC-PGA2 Package ........................... 68

6.1.2

Boxed Processor Heatsink Weight......................................................... 70

6.2

Thermal Specifications........................................................................................ 70
6.2.1

Boxed Processor Cooling Requirements ............................................... 70

6.2.2

Boxed Processor Thermal Cooling Solution Clip ................................... 71

6.3

Electrical Requirements for the Boxed Processor............................................... 71
6.3.1

Electrical Requirements ......................................................................... 71

7.0

Processor Signal Description ........................................................................................... 73
7.1

Alphabetical Signals Reference .......................................................................... 73

7.2

Signal Summaries ............................................................................................... 80

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

List of Figures

Integrated Heat Spreader (IHS) ............................................................................9

AGTL Bus Topology in a Uniprocessor Configuration.........................................14

Stop Clock State Machine ...................................................................................14

PLL Filter Specification........................................................................................18

Differential/Single-Ended Clocking Example.......................................................19

Power Good and Bus Select Interconnect Diagram.....................................21

BSEL[1:0] Example for a System Design............................................................24

Vcc Static and Transient Tolerance ....................................................................28

Clock Waveform ..................................................................................................36

BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform ..............................37

System Bus Valid Delay Timings ........................................................................37

System Bus Setup and Hold Timings..................................................................38

System Bus Reset and Configuration Timings....................................................38

Platform Power-On Sequence and Timings ........................................................39

Power-On Reset and Configuration Timings.......................................................39

Test Timings (TAP Connection) ..........................................................................40

Test Reset Timings .............................................................................................40

BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins ...........42

Low to High AGTL Receiver Ringback Tolerance...............................................43

Maximum Acceptable AGTL Overshoot/Undershoot Waveform .........................47

Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback ......................47

Noise Estimation .................................................................................................50

Package Dimensions...........................................................................................53

Volumetric Keep-Out ...........................................................................................55

Component Keep-Out .........................................................................................55

Top Side Processor Markings .............................................................................56

Processor Pinout ................................................................................................57

Conceptual Boxed Processor for the PGA370 Socket ........................................68

Comparison between FC-PGA and FC-PGA2 package......................................69

Side View of Space Requirements for the Boxed Processor ..............................69

Dimensions of Mechanical Step Feature in Heatsink Base.................................70

Thermal Airspace Requirement for all Boxed Processor Fan

Heatsinks in the PGA370 Socket ........................................................................71

Boxed Processor Fan Heatsink Power Cable Connector Description.................72

Motherboard Power Header Placement Relative to the Boxed Processor..........72

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Datasheet

List of Tables

Processor Identification....................................................................................... 11

System Bus Clock in Deep Sleep Mode (Differential Mode only) ....................... 16

Voltage Identification Definition .......................................................................... 20

System Bus Signal Groups ................................................................................ 23

Frequency Select Truth Table for BSEL[1:0] ...................................................... 24

Absolute Maximum Ratings ................................................................................ 25

Voltage and Current Specifications..................................................................... 26

Power Supply Current Slew Rate (dIcccore/dt)................................................... 27

Vcc Static & Transient Tolerance........................................................................ 28

AGTL Signal Group Levels Specifications .......................................................... 29

Non-AGTL Signal Group Levels Specifications .................................................. 29

3.3 Volt CMOS Output Signal Group DC Specifications ..................................... 30

Processor AGTL Bus Specifications ................................................................... 30

System Bus Timing Specifications (Single-Ended Clock) ................................... 31

System Bus Timing Specifications (Differential Clock) ....................................... 32

Valid System Bus to Core Frequency Ratios ..................................................... 33

System Bus Timing Specifications (AGTL Signal Group) ................................... 33

System Bus Timing Specifications (CMOS Signal Group).................................. 33

System Bus Timing Specifications (Reset Conditions) ...................................... 34

System Bus Timing Specifications (APIC Clock and APIC I/O) .......................... 34

System Bus Timing Specifications (TAP Connection) ........................................ 35

Platform Power-On Timings ................................................................................ 36

BCLK (Single-Ended Clock Mode) Signal Quality Specifications for

Simulation at the Processor Pins ........................................................................ 41

BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality

Specifications for Simulation at the Processor Pins............................................ 41

AGTL Signal Groups Ringback Tolerance Specifications at the

Processor Pins .................................................................................................... 42

Example Platform Information............................................................................. 45

100 MHz AGTL Signal Group Overshoot/Undershoot Tolerance ...................... 46

33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance........................ 48

Signal Ringback Specifications for Non-AGTL Signal Simulation at the

Processor Pins .................................................................................................... 49

Processor Thermal Design Power ..................................................................... 51

THERMTRIP# Time Requirement....................................................................... 51

Thermal Diode Parameters ................................................................................. 52

Thermal Diode Interface...................................................................................... 52

The Processor Package Dimensions .................................................................. 54

Processor Case Loading Parameters ................................................................. 54

Signal Listing in Order by Signal Name .............................................................. 58

Signal Listing in Order by Pin Number ................................................................ 63

Boxed Processor Fan Heatsink Spatial Dimensions........................................... 70

Fan Heatsink Power and Signal Specifications................................................... 72

Signal Description ............................................................................................... 73

Output Signals..................................................................................................... 80

Input Signals ....................................................................................................... 80

Input/Output Signals (Single Driver).................................................................... 81

Input/Output Signals (Multiple Driver) ................................................................. 82

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

1.0

Introduction

The Intel

Celeron

processor based on 0.13 micron process core for the PGA370 socket is the

next member of the P6 family, in the Intel IA-32 processor line and hereafter will be referred to as

simply "the processor". The processor will continue in the package technology called flip-chip pin
grid array but will contain a Integrated Heat Spreader (IHS) (see

Figure 1

). The flip-chip with IHS

package will be labeled as FC-PGA2 and will utilize the same 370-pin zero insertion force socket

(PGA370). Thermal solutions contact the IHS directly for the FC-PGA2 package and not to the
bare-die as with the FC-PGA attachment.

The processor, like its predecessors in the P6 family of processors, implements a Dynamic
Execution microarchitecture--a unique combination of multiple branch prediction, data flow

analysis, and speculative execution. The processor delivers higher performance than the Intel

Celeron

processor based on 0.18 micron process core, while maintaining binary compatibility

with all previous Intel Architecture processors. The processor also executes Intel

MMX

technology instructions for enhanced media and communication performance just as the
predecessor Celeron processor based on 0.18 micron process core. Additionally, the processor
executes Streaming SIMD (single-instruction, multiple data) Extensions for enhanced floating

point and 3-D application performance. The processor utilizes multiple low-power states such as
Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times.

The processor includes an integrated on-die, 256KB 8-way set associative level-two (L2) cache.
The L2 cache implements the Advanced Transfer Cache Architecture with a 256-bit wide bus. The
processor also includes a 16 KB level one (L1) instruction cache and 16 KB L1 data cache. These

cache arrays run at the full speed of the processor core. The processor for the PGA370 socket has a
dedicated L2 cache bus, thus maintaining the dual independent bus architecture to deliver high bus
bandwidth and performance. Memory is cacheable for 64 GB of addressable memory space,

allowing significant headroom for desktop systems. Refer to the Specification Update document
for this processor to determine the cacheability and cache configuration options for a specific
processor. Contact your nearest Intel Sales Representative for the latest Processor Specification

Update.

The processor will support a lower voltage differential and single-ended clocking for the system
bus. The previous generation Intel

Celeron processors for the PGA370 socket will function in a

platform that supports this processor, if the platform has been designed to be backward compatible.
In addition, the processor will not function in a previous generation platform due to incompatible
system bus signal levels and clock type. Care must be taken to ensure the correct processors are

installed in the correct PGA370 socket platforms.

Figure 1. Integrated Heat Spreader (IHS)

FC-PGA2 w/IHS FC-PGA

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

1.1

Terminology

In this document, a `#' symbol after a signal name refers to an active low signal. This means that a

signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal
is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to
a hex `A' (H= High logic level, L= Low logic level).

The term "system bus" refers to the interface between the processor, system core logic (a.k.a. the

chipset components), and other bus agents.

1.1.1

Package and Processor Terminology

The following terms are used often in this document and are explained here for clarification:

The processor - The entire product including all internal components.

256k UP processor - The desktop version of the 0.13 micron process processor. Contains

256KB of L2 cache and is uni-processor capable only.

PGA370 socket - 370-pin Zero Insertion Force (ZIF) socket which a FC-PGA packaged
processor plugs into.

FC-PGA - Flip Chip Pin Grid Array. The package technology used on processors based on the
0.18 micron process for the PGA370 socket. The FC-PGA package has the processor die
exposed.

FC-PGA2 - Flip Chip Pin Grid Array 2. The package technology used on the processor for the
PGA370 socket. The FC-PGA2 package contains an Integrated Heat Spreader which covers
the processor die.

Advanced Transfer Cache (ATC) - L2 cache architecture used on the Celeron

processors.

ATC consists of microarchitectural improvements that provide a higher data bandwidth
interface into the processor core that is completely scaleable with the processor core

frequency.

Keep-out zone - The area on or near a FC-PGA packaged processor that system designs can
not utilize.

Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.

Processor - For this document, the term processor is the generic form of the Celeron

processor based on 0.13 micron process core for the PGA370 socket in the FC-PGA2 package.

Processor core - The processor's execution engine.

Integrated Heat Spreader (IHS) - The Integrated Heat Spreader (IHS) is a metal cover on the
die and it is an integral part of the processor. The IHS promotes heat spreading away from the

die backside to ease thermal constraints

The cache and L2 cache are industry designated names.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

1.1.2

Processor Naming Convention

NOTES:

1. Refer to the Intel

Celeron

Processor Specification Update for the exact CPUID for each processor.

2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.

With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same
frequency as the processor core and has enhanced buffering.

3. 1.20 GHz at Vcc

CORE

= 1.475 volts and S-Spec number SL5XS.

Table 1. Processor Identification

Processor

Core Frequency

System Bus

Frequency

(MHz)

L2 Cache Size

(Kbytes)

L2 Cache

Type

CPUID

1.4

1.40

100

256

ATC

06Bxh

1.30

1.30 GHz

100

256

ATC

06Bxh

1.20

1.20 GHz

100

256

ATC

06Bxh

1.20

1.20 GHz

100

256

ATC

06Bxh

1.10A

1.10A GHz

100

256

ATC

06Bxh

1A GHz

100

256

ATC

06Bxh

900 900 MHz

100

256

ATC

06Bxh

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

1.2

Related Documents

The reader of this specification should also be familiar with material and concepts presented in the

following documents

1,2

NOTES:

1. Unless otherwise noted, this reference material can be found on the Intel Developer's Website located at

http://developer.intel.com.

2. For a complete listing of Intel Celeron processor reference material, please refer to the Intel Developer's

Website at http://developer.intel.com/design/Celeron/.

3. This material is available through an Intel Field Sales Representative.

Document

Intel Order Number

AP-485, Intel

Processor Identification and the CPUID Instruction

241618

AP-589, Design for EMI

243334

Intel

Architecture Software Developer's Manual 243193

Volume I: Basic Architecture

243190

Volume II: Instruction Set Reference

243191

Volume III: System Programming Guide

243192

P6 Family of Processors Hardware Developer's Manual

244001

IA-32 Processors and Related Products 1999 Databook

243565

370-Pin Socket (PGA370) Design Guidelines

244410

PGA370 Heat Sink Cooling in MicroATX Chassis

245025

815 B-step Chipset Platform Design Guide

CK-815 Clock Synthesizer/Driver Specification

CK-408 Clock Synthesizer/Driver Specification

VRM 8.5 DC-DC Converter Design Guidelines

249659

Extensions to the Pentium

Pro Processor BIOS Writer's Guide Revision

Intel

Pentium

III Processor in the FC-PGA2, 370-pin Package Thermal Design

Guidelines

249660

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.0

Electrical Specifications

2.1

Processor System Bus and V

REF

The processor uses the original low voltage signaling of the Gunning Transceiver Logic (GTL)
technology for the system bus. The GTL system bus operates at 1.25V signal levels versus GTL+
which operates at 1.5 V signal levels. The GTL+ signal technology is used by the Intel

Pentium

Pro, Intel

Pentium

II and Intel

Pentium

III

processors.

Current P6 family processors vary from the Intel

Pentium

Pro processor in their output buffer

implementation. The buffers that drive the system bus signals on the processor are actively driven
to V

for one clock cycle after the low to high transition to improve rise times. These signals are

open-drain and require termination to a supply. Because this specification is different from the
standard GTL specification, it is referred to as AGTL, or Assisted GTL in this and other
documentation related to the processor.

AGTL logic and AGTL+ logic are not compatible with each other due to differences with the signal

switching levels. The processor cannot be installed into platforms where the chipset only supports
the AGTL+ signal levels. For more information on AGTL or AGTL+ routing, please refer to the
appropriate platform design guide.

AGTL inputs use differential receivers which requires a reference voltage (V

REF

). V

REF

is used by

the differential receivers to determine if the input signal is a logical 0 or a logical 1. The V

REF

signal is typically implemented as a voltage divider on the platform. Noise decoupling is critical for
the V

REF

signal. Refer to the platform design guide for the recommended decoupling requirements.

Another important item for the AGTL system bus is termination.

System bus termination is used to pull each signal to a high voltage level and to control reflections

on the transmission line. The processor contains on-die termination resistors that provide
termination for one end of the system bus. The other end of the system bus should also be
terminated near the chipset by resistors placed on the platform or on-die termination within the

chipset. It is recommended that the system bus is implemented using Dual-End Termination (DET)
to meet the timings and signal integrity specified by the processor.

Figure 2

is a schematic

representation of the AGTL bus topology for the processor, when the chipset has does not have on-

die termination.

Note: The RESET# signal requires a discrete external termination resistor on the system board.

The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL
signals are based on flight time as opposed to capacitive deratings. Analog signal simulations of the
system bus, including trace lengths, is highly recommended especially when not following the

recommended layout guidelines.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.2

Clock Control and Low Power States

Processors allow the use of Sleep, and Deep Sleep states to reduce power consumption by stopping
the clock to internal sections of the processor, depending on each particular state. See

Figure 3

for a

visual representation of the processor low power states.

For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep

Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a `1' (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer's

Manual, Volume 3: System Programming Guide.

Figure 2. AGTL Bus Topology in a Uniprocessor Configuration

Processor

Chipset

I/O

Note: RESET# requires external termination.

Figure 3. Stop Clock State Machine

PCB757a

2. Auto HALT Power Down State

BCLK running.
Snoops and interrupts allowed.

HALT Instruction and
HALT Bus Cycle Generated

INIT#, BINIT#, INTR,
SM I#, RESET#

1. Normal State

Norm al execution.

STPCLK#
Asserted

STPCLK#
De-asserted

3. Stop Grant State

BCLK running.
Snoops and interrupts allowed.

SLP#
Asserted

SLP#
De-asserted

5. Sleep State

BCLK running.
No snoops or interrupts allowed.

BCLK
Input
Stopped

BCLK
Input
Restarted

6. Deep Sleep State

BCLK stopped.
No snoops or interrupts allowed.

4. HALT/Grant Snoop State

BCLK running.
Service snoops to caches.

Snoop Event Occurs

Snoop Event Serviced

Snoop
Event
Occurs

Snoop
Event
Serviced

STPCLK# Asserted

STPCLK# De-asserted

and Stop-Grant State

entered from

AutoHALT

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.2.1

Normal State--State 1

This is the normal operating state for the processor.

2.2.2

AutoHALT Powerdown State--State 2

AutoHALT is a power state entered when the processor executes the HALT instruction. The

processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI,
INTR). RESET# causes the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.

FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT

state.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT
state.

2.2.3

Stop-Grant State--State 3

The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.

Since the AGTL signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to V

) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the system bus should be driven to the inactive state.

BINIT# and FLUSH# are not serviced during the Stop-Grant state.

RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant

state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal.

A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the
system bus (see

Section 2.2.4

). A transition to the Sleep state (see

Section 2.2.5

) occurs with the

assertion of the SLP# signal.

While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] are latched by the processor, and only

serviced when the processor returns to the Normal state. Only one occurrence of each event is
recognized and serviced upon return to the Normal state.

2.2.4

HALT/Grant Snoop State--State 4

The processor responds to snoop transactions on the system bus while in Stop-Grant state or in

AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor stays in this state until the snoop on the system bus has been serviced
(whether by the processor or another agent on the system bus). After the snoop is serviced, the

processor returns to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.2.5

Sleep State--State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be

entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctly executes the reset sequence.

While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see

Section 2.2.6

). Once in the Sleep state, the SLP# pin can be

deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum

assertion of one BCLK period.

2.2.6

Deep Sleep State--State 6

The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from

the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is
stopped. BCLK and BCLK# have to be separated by at least 0.2V during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.

To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL

stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus

while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.

NOTES:

1. The values in this table are based on differential probe measurement of the Bclk.
2. The DC voltage level specified must be maintained when the system bus clock is not active (e.g., Deep Sleep

Mode). V

BCLK#

has to be 200 mV less than V

BCLK

Table 2. System Bus Clock in Deep Sleep Mode (Differential Mode only)

Symbol

Parameter

Min

Max

Units

Notes

BCLK

BCLK Voltage Level when not active

0.4

1.45

BCLK

BCLK#

BCLK# Voltage Level when not active

BCLK

0.2

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.2.7

Clock Control

BCLK provides the clock signal for the processor and on-die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not

stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.

When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the

Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).

PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep

Sleep state to the Sleep state, PICCLK must be restarted with BCLK.

2.3

Power and Ground Pins

The operating voltage for the processor is the same for the core and the L2 cache. V

CCCORE

defined as the power pins that supply voltage to the processor's core and cache. The Voltage
Regulator Module (VRM) or Voltage Regulator are controlled by the five voltage identification
(VID) signals driven by the processor. The VID signals specify the voltage required by the

processor core. Refer to

Section 2.6

for further details on the VID voltage settings.

The processor has 74 V

CCCORE

, 7 V

REF

, 20 V

, V

CCCMOS1.5

, V

CCCMOS1.8,

CCCMOS2.0

and 74

inputs. The V

REF

inputs are used as the AGTL reference voltage for the processor. The V

inputs (1.25V) are used to provide an AGTL termination voltage to the processor. V

CCCMOS1.5

and

CCCMOS1.8

and V

CCCMOS2.0

are not voltage input pins to the processor but rather voltage sources

for the pullup resistors which are connected to CMOS (non-AGTL) input/output signals driven to/
from the processor. The V

inputs are ground pins for the processor core and L2 cache.

On the platform, all V

CCCORE

pins must be connected to a voltage island (an island is a portion of

a power plane that has been divided, or an entire plane) to minimize any voltage drop that may
occur due to trace impedance. It is also highly recommended for the platform to provide either a
voltage island or a wide trace for the V

pins. Similarly, all Vss pins must be connected to a

system ground plane. These recommendations can be found in the platform design guide layout
section.

2.3.1

Phase Lock Loop (PLL) Power

It is highly critical that phase lock loop power delivery to the processor meets Intel's requirements.

A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Refer to the Phase Lock Loop Power section in the
appropriate platform design guide for the recommended filter implementation.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.4

Decoupling Guidelines

Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can

cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in

Table 7

. Failure to do so can result in timing

violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot).

2.4.1

Processor V

CORE

Decoupling

The regulator for the V

CCCORE

input must be capable of delivering the dI

CCCORE

/dt (defined in

Table 7

) while maintaining the required tolerances (also defined in

Table 7

). Failure to meet these

specifications can result in timing violations (during V

CCCORE

sag) or a reduced lifetime of the

component (during V

CCCORE

overshoot).

The processor requires both high frequency and bulk decoupling on the system motherboard for

proper AGTL bus operation. The minimum recommendation for the processor decoupling
requirement is listed below. All capacitors should be placed next to and within the PGA370 socket
cavity and mounted on the primary side of the motherboard. The capacitors are arranged to

minimize the overall inductance between the V

CCCORE

and Vss power pins.

Decoupling Recommendations:

CCCORE

decoupling: A minimum of sixteen 4.7 uF capacitors in a 1206 package.

decoupling: Twenty 0.1 uF capacitors in 0603 packages.

REF

decoupling: 0.1 uF and 0.001 uF capacitors in 0603 package placed near the V

REF

pins.

For additional decoupling requirements, refer to the appropriate platform design guide for
recommended capacitor component value/quantity and placement.

Figure 4. PLL Filter Specification

0.2 dB

0 dB

-0.5 dB

Forbidden

Zone

Forbidden

Zone

-40 dB

-28 dB

fpeak

1 MHz

66 MHz

force

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.5

Processor System Bus Clock and Processor Clocking

The processor will implement an auto-detect mechanism that will allow the processor to use either

single-ended or differential signaling for the system bus and processor clocking. The processor
checks to see if the signal on pin Y33 is toggling. If this signal is toggling then the processor
operates in differential mode. Refer to

Figure 5

for an example on differential clocking. Resistor

values and clock topology are listed in the appropriate platform design guide for a differential
implementation.

Note: References to BCLK throughout this document will also imply to it's complement signal, BCLK#

in differential implementations, and when noted otherwise.

Since legacy PGA370 socket platforms use a different single-ended clocking specification than the
processor, the processor will not function when placed into these platforms. The BCLK input

directly controls the operating speed of the system bus interface. All AGTL system bus timing
parameters are specified with respect to the crossing point of the rising edge of the BCLK and the
falling edge of BCLK# inputs in a differential implementation. See the P6 Family of Processors

Hardware Developer's Manual for further details. The reference voltage of the BCLK in the P6
Family of Processors Hardware Developer Manual is re-defined as the crossing point of the BCLK
and BCLK# in a differential implementation.

2.6

Voltage Identification

There are five voltage identification (VID) pins on the PGA370 socket. These pins can be used to

support automatic selection of V

CCCORE

voltages. The VID pins for the processor are open drain

signals versus opens or shorts found on the previous Intel Celeron

FC-PGA processor. Refer to

Table 11

for level specifications for the VID signals. This pull-up resistor may be either external

logic on the motherboard or internal to the Voltage Regulator.

The VID signals rely on a 3.3 V pull-up resistor to set the signal to a logic high level. The VID pins
are needed to fully support voltage specification variations on current and future processors. The
voltage selection range for the processor is defined in

Table 3

. The VID25mV signal is a new

signal that allows the voltage regulator or voltage regulator module (VRM) to output voltage levels
in 25 mV increment necessary for the processor only. The current Celeron processor in the FC-
PGA package will not have this VID25mV signal. The VID25mV pin location is actually a Vss pin

Figure 5. Differential/Single-Ended Clocking Example

Clk E

Diff Si

BCLK

BCLK#

Clock

Driver

Processor
or Chipset

Clock

Driver

Processor
or Chipset

BCLK

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

on the model 68xh based on 0.18 micron process core processor. By connecting the VID25mV
signal to the Vss pin, it will disable the 25 mV stepping granularity output and the regulator will

resort to 50 mV stepping increment. The voltage regulator or VRM must supply the voltage that is
requested or disable itself.

In addition to the new signal "VID25mV", the processor will introduce a second new signal labeled
as "VTT_PWRGD". The VTT_PWRGD signal informs the platform that the VID and BSEL

signals are stable and should be sampled. During Power-up, the VID signals will be in an
indeterminate state for a small period of time. The voltage regulator or the VRM should not latch
the VID signals until the VTT_PWRGD signal is asserted by the VRM and sampled active. The

assertion of the VTT_PWRGD signal indicates the VID signals are stable and are driven to the
final state by the processor. Refer to

Figure 14

for power-up timing sequence for the

VTT_PWRGD and the VID signals.

NOTES:

1. 0 = Processor pin connected to V

. and 1 = Open on processor; may be pulled up to TTL V

(3.3 V max) on

baseboard.

Table 3. Voltage Identification Definition

VID25mV

VID3

VID2

VID1

VID0

Vcc

CORE

1.05

1.075

1.10

1.125

1.15

1.175

1.20

1.225

1.25

1.275

1.30

1.325

1.35

1.375

1.40

1.425

1.45

1.475

1.50

1.525

1.55

1.575

1.60

1.625

1.65

1.675

1.70

1.725

1.75

1.775

1.80

1.825

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

The VID pins should be pulled up to a 3.3 V level. This may be accomplished with pull-ups
internal to the voltage regulator, which ensures valid VID pull-up voltage during Power-up and

Power-down sequences. If external resistors are used for the VID[3:0, 25mV] signal, then the
power source must be guaranteed to be stable whenever the supply to the voltage regulator is
stable. This will prevent the possibility of the processor supply going above the specified V

CCCORE

in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this
can be accomplished by using the input voltage to the converter for the VID line pull-ups. A
resistor equal to 1 k

may be used to connect the VID signals to the voltage regulator input.

Note: Intel requires that designs utilize VRM 8.5 and Not VRM 8.4 guidelines to meet the processor

requirements.

To re-emphasize, VRM 8.5 introduces two new signals [VID25mV and VTT_PWRGD] that is
utilized by the processor and platform. Ignoring and not connecting these two new pins, as
documented in the Platform Design Guidelines, will prevent the processor from operating at the
specified voltage levels and core frequency.

Figure 6

provides a high-level interconnection

schematic. Refer to the VRM 8.5 DC-DC Converter Design Guideline and the appropriate Platform
Design Guidelines for further detailed information on the voltage identification and bus select
implementation. Refer to

Figure 14

for VID power-up sequence and timing requirements.

2.7

Processor System Bus Unused Pins

All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to V

CCCORE

, V

REF

, V

or to any other signal (including each other) can result in component

malfunction or incompatibility with future processors. See

Section 5.4

for a pin listing of the

processor and the location of each RESERVED pin.

PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
V

CCCMOS1.5

even when the APIC will not be used. A separate pull-up resistor must be provided for

each PICD signal.

For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (V

) and logic low (V

) requirements are met. See

Table 11

for level

specifications of non-AGTL signals.

Figure 6. V

Power Good and Bus Select Interconnect Diagram

VRM 8.5

Voltage Regulator

VTT_PWRGD

(output)

Intel

Celeron

Processor based on

0.13 Micron Process

VTT_PWRGD
(input)

CORE

1 k

Clock

Driver

BSEL[1:0]

VID[3:0, 25mV]

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

For unused AGTL inputs, the on-die termination will be sufficient. No external R

is necessary on

the motherboard

For unused CMOS inputs, active low signals should be connected through a pull-up resistor to

CCCMOS1.5

and meet V

requirements. Unused active high CMOS inputs should be connected

through a pull-down resistor to ground (V

) and meet V

requirements. Unused CMOS outputs

can be left unconnected. A resistor must be used when tying bidirectional signals to power or

ground. When tying any signal to power or ground, a resistor will also allow for system testability.

2.8

Processor System Bus Signal Groups

To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a

high-level source provided termination resistors. However, the processor includes on-die
termination for AGTL signals and termination resistors placed on the platform are not necessary
except for the RESET# signal which still requires external termination.

AGTL input signals have differential input buffers which use V

REF

as a reference signal. AGTL

output signals require termination to 1.25 V. In this document, the term "AGTL Input" refers to the
AGTL input group as well as the AGTL I/O group when receiving. Similarly, "AGTL Output"
refers to the AGTL output group as well as the AGTL I/O group when driving.

The PWRGOOD signal input is a 1.8 V signal level and must be pulled up to V

CCCMOS1.8

. The

VTT_PWRGD is not 1.8 V tolerant and must be connected to V

TT (

1.25 V)

Other CMOS inputs

(A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) are
only 1.5 V tolerant and must be pulled up to V

CCCMOS1.5

. The CMOS, APIC, and TAP outputs are

open drain and must be pulled to the appropriate level to meet the input specifications of the
interfacing device.

The groups and the signals contained within each group are shown in

Table 4

. Refer to

Section 7.0

for a description of these signals.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. See

Section 7.0

for information on the these signals.

2. The BR0# pin is the only BREQ# signal that is bidirectional. See

Section 7.0

for more information.

3. This signal is 1.25 V.
4. These signals are 1.5 V.
5. This signal is 1.8 V.
6. V

CORE

is the power supply for the processor core and is described in

Section 2.6

VID[3:0,25mV] is described in

Section 2.6

is used to terminate the system bus and generate V

REF

on the motherboard.

is system ground.

BSEL[1:0] is described in

Section 2.8.2

and

Section 7.0

All other signals are described in

Section 7.0

7. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform

design guide for the recommended pulldown resistor value.

8. These signals are 3.3 V.
9. These signals are 2.0 V.

10. 1.25 V signal for Differential clock application and 2.5 V for Single-ended clock application.

2.8.1

Asynchronous vs. Synchronous for System Bus Signals

All AGTL signals are synchronous to BCLK (BCLK/BCLK#). All of the CMOS, Clock, APIC,
and TAP signals can be applied asynchronously to BCLK (BCLK/BCLK#). All APIC signals are

synchronous to PICCLK. All TAP signals are synchronous to TCK.

Table 4. System Bus Signal Groups

Group Name

Signals

AGTL Input

BPRI#, DEFER#, RESET#, RSP#

AGTL Output

PRDY#

AGTL I/O

A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#

, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,

RS[2:0]#, TRDY#

CMOS Input
(1.25 V)

VTT_PWRGD

CMOS Input
(1.5 V)

A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#

CMOS Input
(1.8 V)

PWRGOOD

CMOS Output
(1.5 V)

FERR#, IERR#, THERMTRIP#

CMOS Output

(3.3 V)

VID[3:0,25mV], BSEL[1:0]

System Bus
Clock

(1.25 V/2.5 V)

BCLK0, BCLK0#

APIC Clock

PICCLK

APIC I/O

PICD[1:0]

TAP Input

TCK, TDI, TMS, TRST#

TAP Output

TDO

Power/Other

CPUPRES#, DYN_OE, NCHTRL, PLL[2:1], SLEWCTRL, RTTCTRL

,THERMDN,

THERMDP, V

CORE

, V

REF

, V

, Reserved,

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.8.2

System Bus Frequency Select Signals

The System Bus Frequency Select Signals (BSEL [1:0]) are used to select the system bus
frequency for the processor. The BSEL signals are also used by the chipset and system bus clock

generator. The BSEL pins for the processor are open drain signals versus opens or shorts found on
the previous Intel Celeron FC-PGA processor. Refer to

Table 11

for level specifications for the

BSEL signals.

The BSEL signals rely on a 3.3 V pull-up resistor to set the signal to a logic high level. Similar to

the VID signals described in

Section 2.6

, the VTT_PWRGD signal also informs the platform that

the BSEL signals are stable and should be sampled. During Power-up, the BSEL signals will be in
a indeterminate state for a small period of time. The chipset or system bus clock generator should

not sample and/or latch the BSEL signals until the VTT_PWRGD signal is asserted. The assertion
of the VTT_PWRGD signal indicates the BSEL signals are stable and are driven to the final state
by the processor. Refer to

Figure 14

for power-up timing sequence for the VTT_PWRGD and the

BSEL signals.

Table 5

defines the possible combinations of the BSEL signals and the frequency associated with

each combination. The frequency selection is determined by the processor(s) and driven out to the
chipset and system bus clock generator. All system bus agents must operate at the same frequency
determined by the processor. The processor operates at 100 MHz system bus frequency based on

the system bus specified rating marked on the package. Over or under-clocking the system bus
frequency outside the specified rating marked on the package is not recommended.

Figure 7. BSEL[1:0] Example for a System Design

Table 5. Frequency Select Truth Table for BSEL[1:0]

BSEL1

BSEL0

Frequency

Reserved

100 MHz

Reserved

Reseved

Processor

BSEL0

BSEL1

Chipset

Clock Driver

1 k

3.3V

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the processor be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage. Similar

considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.

2.10

Maximum Ratings

Table 6

contains processor stress ratings only. Functional operation at the absolute maximum and

minimum is not implied nor guaranteed. The processor should not receive a clock while subjected
to these conditions. Functional operating conditions are given in the timing and level tables in

Section 2.11

through

Section 2.13

. Extended exposure to the maximum ratings may affect device

reliability. Furthermore, although the processor contains protective circuitry to resist damage from
static electric discharge, one should always take precautions to avoid high static voltages or electric
fields.

NOTES:

1. Input voltage can never exceed V

+1.78 volts.

2. Input voltage can never exceed V

+ 2.08 volts.

3. Input voltage can never go below -0.3 V
4. Parameter applies to CMOS, APIC, and TAP bus signal groups only.

2.11

Processor Voltage Level Specifications

The processor voltage level specifications in this section are defined at the PGA370 socket pins
(bottom side of the motherboard). See

Section 7.0

for the processor signal descriptions and

Section 5.4

for the signal listings.

Most of the signals on the processor system bus are in the AGTL signal group. These signals are

specified to be terminated to 1.25 V. The voltage level specifications for these signals are listed in

Table 10 on page 29

To allow connection with other devices, the clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL levels. The voltage level specifications for these pins are listed in

Table 11

on page 29

Table 6. Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

STORAGE

Processor storage temperature

-40

°C

CORE

and

Processor core voltage and termination
supply voltage with respect to V

0.5

1.75

inAGTL

AGTL buffer input voltage

-0.3

1.78

1, 3

inCMOS1.5

CMOS buffer DC input voltage with respect
to V

-0.3

2.08

2, 3, 4

VID &

BSEL

Max VID and BSEL pin current

-0.3

3.6

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Table 7

through

Table 13

list the voltage level specifications for the processor. Specifications are

valid only while meeting specifications for junction temperature, clock frequency, and input

voltages. Care should be taken to read all notes associated with each parameter.

Table 7. Voltage and Current Specifications (Sheet 1 of 2)

Symbol

Parameter

Core Freq

Min

Typ

Max

Unit

Notes

1, 2

CORE

for processor core

1.4 GHz

1.30 GHz
1.20 GHz

1.20

GHz

1.10A GHz

1A GHz

900 MHz

1.5
1.5
1.5

1.475
1.475
1.475
1.475

3, 13

Static AGTL bus
termination voltage

1.25

1.25 ±3%

, 4

Transient AGTL bus
termination voltage

1.25

1.25 ±9%

, 4

cc_cmos1.5

1.5

1.5 ± 10%

, 12

cc_cmos1.8

1.8

1.8 ± 10%

, 12

Baseboard
V

CORE

Tolerance,
Static

Processor core voltage
static tolerance level at the
PGA370 socket pins

Refer to

Figure 8

and

Table 9

for Tolerance
values

Baseboard
V

CORE

Tolerance,
Transient

Processor core voltage
transient tolerance level at
the PGA370 socket pins

CCCORE

for processor core

1.4 GHz

1.30 GHz
1.20 GHz

1.20

GHz

1.10A GHz

1A GHz

900 MHz

22.6
22.5
21.5
20.6
19.9
19.1
18.1

6, 13

CCCMOS1.5

for Vcc

CMOS1.5

250

CCCMOS1.8

for Vcc

CMOS1.8

CCCMOS3.3

for Vcc

CMOS3.3

Termination voltage supply
current

2.3

SGnt

Stop-Grant for

processor core

15.37

7, 8

DSLP

Deep Sleep

1.4 GHz

1.30 GHz
1.20 GHz

1.20

GHz

1.1A GHz

1A GHz

900 MHz

12.0
12.0
12.0
11.0
11.0
11.0
11.0

CORE

/dt

Power supply current slew
rate

Refer to

Table 8

for Slew

Rate

A/µs

8, 9, 10, 11

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Celeron processor based on 0.13 micron process core.
3. Vcc

CORE

and Icc

CORE

supply the processor core and the on-die L2 cache.

4. V

must be held to 1.25 V ±9% while the AGTL bus is active. It is required that V

be held to 1.25 V ±3%

while the processor system bus is static (idle condition). The ±3% range is the required design target; ±9%
will come from the transient noise added. This is measured at the PGA370 socket pins on the bottom side of
the baseboard.

5. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the

processor socket pin on the soldered-side of the motherboard.

CORE

must return to within the static

voltage specification within 100

s after a transient event; see the VRM 8.5 DC-DC Converter Design

Guidelines

for further details.

6. Maximum I

is measured at V

typical voltage and under a maximum signal loading conditions.

7. The current specified is also for AutoHALT state.
8. Maximum values are specified by design/characterization at nominal Vcc

CORE

9. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum

inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.

10. dIcc/dt specifications are measured and specified at the PGA370 socket pins.
11. Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output

load ranges specified in the tables above. See VRM 8.5 Specification.

12.Pull ups only.
13. For frequencies beyond 1.40 GHz, refer to the latest flexible motherboard 1 extended (FMB1-E) guidelines

available via your Intel Representative.

14. 1.20 GHz at Vcc

CORE

= 1.475 volts and S-Spec number SL5XS.

Table 8

contains typical slew rate data for the processor. Actual slew rate values and wave-shapes

may vary slightly depending on the type and size of decoupling capacitors used in a particular
implementation.

/dt

Termination current slew
rate

Table

A/µs

8, 9, 10 See

Table 13

Table 7. Voltage and Current Specifications (Sheet 2 of 2)

Symbol

Parameter

Core Freq

Min

Typ

Max

Unit

Notes

1, 2

Table 8. Power Supply Current Slew Rate (dIcc

core

/dt)

c
k
e
t

(A

)

Slew Rate: 26 A Load Step
Slew Rate (26 A): ICC at Socket

Time (us)

ICC at Socket (A)

0.1

26.23

0.15

23.18

0.5

20.03

21.10

1.5

21.88

22.29

2.5

22.30

22.07

3.5

21.78

21.58

4.5

21.51

PWL SLew Rate Data

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Table 9. Vcc Static & Transient Tolerance

Icc (A)

Voltage Deviation from VID Setting (mV)

Static Tolerance

Transient Tolerance

Min

Max

Min

Max

-5

-15

-25

-35

-45

-55

-5

-65

-15

-76

-5

-75

-25

-87

-15

-85

-35

-98

-25

-95

-45

-110

-35

-105

-55

-121

-45

-115

-65

-132

-55

-125

-75

-144

-65

-135

-85

-155

-75

Figure 8. Vcc Static and Transient Tolerance

-40

-80

-60

-10 0

-12 0

-14 0

-20

2 0

4 0

6 0

1 0

2 0

3 0

c
c

Droop f

r
om

I
D

t
t
i
ng (m

)

Ic c L o ad (A )

8 0

Tran s ien t M a xim u m L o a d L ine

S ta tic M ax im u m L o ad L in e

Tran s ie n t M in im u m L o a d L in e

S tatic M in im u m L o a d L in e

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the

processor at a frequency up to 1.40 GHz

on 0.13 micron.

2. All inputs, outputs, and I/O pins must comply with the signal quality specifications in

Section 3.0

3. Minimum and maximum V

are given in

Table 13 on page 30

4. (0

1.25 V +3%) and (0

OUT

1.25 V+3%).

5. Refer to the processor I/O Buffer Models for I/V characteristics.
6. Steady state input voltage must not be above V

+ 1.65 V or below V

1.65 V.

7. Does not apply to Vcc leakage current due to the presence of on-die RTT.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor

up to 1.40 GHz frequency on

0.13 micron.

2. Parameter measured at 9 mA (for use with TTL inputs).
3. (0

1.8 V +10%).

4. (0

OUT

1.8 V +10%).

5. For BCLK specifications, refer to

Table 24 on page 41

6. (0

1.5 V +10%).

7. (0

OUT

1.5 V +10%).

8. Applies to non-AGTL signal PWRGOOD.
9. Applies to non-AGTL signal PICCLK.

10.Applies to non-AGTL signals except BCLK, PICCLK, and PWRGOOD.
11.Applies to non-AGTL signal VTT_PWRGD.
12.Vcmos_ref = 2/3 Vcc_cmos1.5, refer to

Table 7 on page 26

13.Applies to PICD[1:0] only

Table 10. AGTL Signal Group Levels Specifications

Symbol

Parameter

Min

Max

Unit

Notes

Input Low Voltage

REF

- 0.200

Input High Voltage

REF

+ 0.200

2, 3, 6

Ron

Buffer On Resistance

16.67

Leakage Current for inputs,
outputs, and I/O

±100

µA

4, 7

Table 11. Non-AGTL Signal Group Levels Specifications

Symbol

Parameter

Min

Max

Unit

Notes

IL1.2

Input Low Voltage

0.4

IL1.5

Input Low Voltage

0.150

Vcmos_ref - 0.300

IL1.8

Input Low Voltage

-0.36

0.36

IL2.0

Input Low Voltage

-0.40

0.40

IH1.2

Input High Voltage

1.03

IH1.5

Input High Voltage

Vcmos_ref +

0.250

CC_CMOS1.5 +

10%

6, 10, 12

IH1.5PICD

Input High Voltage PICD[1:0]

Vcmos_ref +

0.200

2.0

12, 13

IH1.8

Input High Voltage

1.44

2.16

IH2.0

Input High Voltage

1.60

Output Low Voltage

0.30

7, 9, All
outputs are
open-drain

Output Low Current

Input Leakage Current

±100

µA

3, 6

Output Leakage Current

±100

µA

3, 4, 6, 7

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.12

AGTL System Bus Specifications

It is recommended that the AGTL bus be routed in a daisy-chain fashion with termination resistors

to V

. These termination resistors are placed electrically between the ends of the signal traces and

the V

voltage supply. The valid high and low levels are determined by the input buffers using a

reference voltage called V

REF

. Refer to the appropriate platform design guide for more information

Table 13

lists the nominal specification for the AGTL termination voltage (V

). The AGTL

reference voltage (V

REF

) is generated on the system motherboard and should be set to 2/3 V

for

the processor and other AGTL logic. It is important that the baseboard impedance be specified and
held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL signal group traces

is known and well-controlled. For more details on the AGTL buffer specification, see the
Intel

Pentium

II Processor Developer's Manual and AP-585, Intel

Pentium

II Processor

AGTL Guidelines.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the

processor up to 1.40 GHz frequency.

2. The processor for the PGA370 socket contain AGTL termination resistors on the processor die, except for the

RESET# input.

3. V

must be held to 1.25 V ±9%. It is required that V

be held to 1.25 V ±3% while the processor system bus

is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard.

4. Uni-processor platforms require a 56

resistor and dual-processor platforms require a 68

resistor.

Tolerance for on-die Rtt is ±10% (56

, 68

resistors). Rtt is ±15% (100

resistors).

5. V

REF

is generated on the motherboard and should be 2/3 V

±5% nominally. Insure that there is adequate

REF

decoupling on the motherboard.

Table 12. 3.3 Volt CMOS Output Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

Nominal Voltage

3.45

3.3 + 5%

Output High Voltage

0.9

Output Leakage Current

100

µA

Table 13. Processor AGTL Bus Specifications

Symbol

Parameter

Min

Typ

Max

Units

Notes

1,2

Bus Termination Voltage

1.1375

1.25

On-die R

Termination Resistor

56
68

115

REF

Bus Reference Voltage

2/3V

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

2.13

System Bus Timing Specifications

The processor system bus timings specified in this section are defined at the socket pins on the

bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See

Section 7.0

for the processor signal definitions.

Table 14

through

Table 21

list the timing specifications associated with the processor system bus.

These specifications are broken into the following categories:

Table 14

contains the system bus

clock specifications for Single-ended clock mode operation and

Table 15

contains the system bus

clock specifications for Differential clock mode operation.

Table 17

contains the AGTL

specifications,

Table 18

contains the CMOS signal group specifications,

Table 19

contains timings

for the reset conditions,

Table 20

and covers APIC bus timing, and

Table 21

covers TAP timing.

All processor system bus timing specifications for the AGTL signal group are relative to the rising
edge of the BCLK input. All AGTL timings are referenced to V

REF

for both `0' and `1' logic levels

unless otherwise specified..

AGTL layout guidelines are also available in the appropriate platform design guide.

Care should be taken to read all notes associated with a particular timing parameter.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the

processor up to 1.40 GHz frequency on

0.13 micron process.

2. Period, jitter, offset and skew measured at 1.25 V.
3. Measured from 0.5 to 2.0 V.
4. CLKREF (BCLK#) = 1.25 V with ±5% DC tolerance. CLKREF must be generated from a stable source. AC

tolerances must be less than -40 dB at 1 MHz.

5. BCLK High Time is measured above 2.0 V.
6. BCLK Low Time is measured below 0.5 V.

Table 14. System Bus Timing Specifications (Single-Ended Clock)

T# Parameter

100 MHz

Unit

Figure

Notes

1,4

Min

Max

T1: BCLK Period - average

10.0

10.15

abs

: BCLK Period - Instantaneous

minimum

9.75

T2: BCLK Period Stability

250

T5: BCLK Rise Time

0.4

1.6

T6: BCLK Fall Time

0.4

1.6

T3: BCLK High Time

2.5

T4: BCLK Low Time

2.4

T7: BCLK Input High

2.2

T8: BCLK Input Low

0.3

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

1. Unless otherwise noted, all specifications in this table apply to the

processor up to 1.40 GHz frequency on

0.13 micron process.

2. All timings for the AGTL signals are referenced at the rising edge of BCLK and the falling edge of BCLK# at

the processor pin. All AGTL signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor pins.

3. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to

core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, 100 MHz.

Table 16

shows the supported ratios for each processor.

4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be

used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured at adjacent crossing points of BCLK and BCLK# which is defined as the rising edge of BCLK and
the falling edge of BCLK# at the processor pin. The jitter present must be accounted for as a component of
BCLK timing skew between devices.

5. The clock driver's closed loop jitter bandwidth must be set low to allow any PLL-based device to track the

jitter created by the clock driver. The 20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than

500 kHz. This specification may be ensured by design characterization and/or measured with a

spectrum analyzer. See the appropriate clock synthesizer/driver specification for details

6. Measurement taken from differential waveform, defined as BCLK BCLK#.
7. Rise time is measured from -0.35 to +0.35V and fall time is measured from 0.35 V to -0.35 V.
8. Measured at the socket pin.

Table 15. System Bus Timing Specifications (Differential Clock)

T# Parameter

100 MHz

Unit

Figure

Notes

1,2,6

Min

Max

T1: BCLK Period - average

10.0

10.2

3, 4

abs

: BCLK Period - Instantaneous minimum

9.8

3, 4

T2: BCLK Period Stability

200

Vcross: Crossing point at 1V Swing

0.51

0.76

T5: BCLK Rise Time

175

550

7, 8

T6: BCLK Fall Time

175

550

7, 8

Rise/Fall Time Matching

325

BCLK Duty Cycle

45%

55%

Input High Voltage

0.92

1.45

Input Low Voltage

-0.2

0.35

Rising Edge Ring Back

0.35

Falling Edge Ring Back

-0.35

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency

multipliers.

2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the

processor.

3. Individual processors will only operate at their specified system bus frequency; 100 MHz.
4. 1.20 GHz at Vcc

CORE

= 1.475 volts and S-Spec number SL5XS.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz on 0.13 micron

process.

2. These specifications are tested during manufacturing.
3. All timings for the AGTL signals are referenced to the rising edge of BCLK and the falling edge of BCLK# at

the processor pin. All AGTL signal timings (compatibility signals, etc.) are referenced at 0.80 V at the
processor pins.

4. Valid delay timings for these signals are specified into 50

to 1.25 V, V

REF

at 0.8 V ±2% and with 56

on-die R

5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from V

REF

200 mV to V

REF

+ 200 mV. This assumes an edge

rate of 0.3V/ns.

8. Specification is for a maximum 0.8 V swing from V

0.8V to V

. This assumes an edge rate of 3 V/ns.

9. This should be measured after V

CORE

, V

, Vcc

CMOS

, and BCLK (and BCLK#) are stable

10.BREQ signals observe a 1.2 ns minimum setup time.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.

Table 16. Valid System Bus to Core Frequency Ratios

1, 2, 3

Processor

Core Frequency

BCLK Frequency

(MHz)

Frequency

Multiplier

1.4 GHz

1.40

100

1.30

1.30 GHz

100

1.20

1.20 GHz

100

1.20

GHz

100

1.1A

1.1A GHz

100

1A GHz

100

900

900 MHz

100

Table 17. System Bus Timing Specifications (AGTL Signal Group)

T# Parameter

Min

Max

Unit

Figure

Notes

1,2,3

T7: AGTL Output Valid Delay

0.40

3.25

T8: AGTL Input Setup Time

1.30

5, 6, 7, 10

T9: AGTL Input Hold Time

1.00

T10: RESET# Pulse Width

1.00

6, 9

Table 18. System Bus Timing Specifications (CMOS Signal Group)

T# Parameter

Min

Max

Unit

Figure

Notes 1

,2,3,4

T14: CMOS Input Pulse Width, except

PWRGOOD

BCLKs

Active and
Inactive states

T15: PWRGOOD Inactive Pulse Width

BCLKs

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

4. All CMOS outputs shall be asserted for at least 2 system bus clocks.
5. When driven inactive or after V

CORE

, V

CCCMOS

, and BCLK and BCLK# are stable.

NOTE:

1. Unless otherwise noted, all specifications in this table apply to all the processor up to 1.40 GHz frequency.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. These specifications are tested during manufacturing.
3. All timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.9 V at the processor pins.

All APIC I/O signal timings are referenced at 1.0 V at the processor pins.

4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150

load pulled up to 1.5 V.

Table 19. System Bus Timing Specifications (Reset Conditions)

T# Parameter

Min

Max

Unit

Figure

Notes

T16: Reset Configuration Signals

(A[14:5]#, BR0#, INIT#) Setup Time

BCLKs

Before deassertion
of RESET#

T17: Reset Configuration Signals

(A[14:5]#, BR0#, INIT#) Hold Time

BCLKs

After clock that
deasserts RESET#

Table 20. System Bus Timing Specifications (APIC Clock and APIC I/O)

1, 2, 3

T# Parameter

Min

Max

Unit

Figure

Notes

T21: PICCLK Frequency

2.0

33.3

MHz

T22: PICCLK Period

30.0

500.0

T23: PICCLK High Time

10.5

@ > 1.60 V

T24: PICCLK Low Time

10.5

@ < 0.40 V

T25: PICCLK Rise Time

0.25

3.0

(0.40 V 1.60 V)

T26: PICCLK Fall Time

0.25

3.0

(1.60 0.40 V)

T27: PICD[1:0] Setup Time

8.0

T28: PICD[1:0] Hold Time

2.5

T29a: PICD[1:0] Valid Delay (Rising Edge)

1.5

8.7

4, 5, 6

T29b: PICD[1:0] Valid Delay (Falling Edge)

1.5

12.0

4, 5, 6

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. All timings for the TAP signals are referenced to the TCK rising edge at 1.0 V at the processor pins. All TAP

signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.

3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to TAP operations.

9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.

10.Not 100% tested. Specified by design characterization.

Table 21. System Bus Timing Specifications (TAP Connection)

T# Parameter

Min

Max

Unit

Figure

Notes

1,2,3

T30: TCK Frequency

16.667

MHz

T31: TCK Period

60.0

T32: TCK High Time

25.0

Vcmos_ref + 0.200 V, 10

T33: TCK Low Time

25.0

Vcmos_ref 0.200 V, 10

T34: TCK Rise Time

5.0

(Vcmos_ref 0.200 V)
(Vcmos_ref + 0.200 V),
4, 10

T35: TCK Fall Time

5.0

(Vcmos_ref + 0.200 V)
(Vcmos_ref 0.200 V),
4, 10

T36: TRST# Pulse Width

40.0

Asynchronous, 10

T37: TDI, TMS Setup Time

5.0

T38: TDI, TMS Hold Time

14.0

T39: TDO Valid Delay

1.0

10.0

6, 7

T40: TDO Float Delay

25.0

6, 7, 10

T41: All Non-Test Outputs Valid Delay

2.0

25.0

6, 8, 9

T42: All Non-Test Inputs Setup Time

25.0

6, 8, 9, 10

T43: All Non-Test Inputs Setup Time

5.0

5, 8, 9

T44: All Non-Test Inputs Hold Time

13.0

5, 8, 9

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform

during processor power-up sequence.

2. Configuration Input signals include: A[14:5], BR0#, INIT#. For timing of these signals, refer to

Table 18

and

Figure 13

Notes: For

Figure 9

through

Figure 19

, the following apply:

Figure 9

through

Figure 19

are to be used in conjunction with

Table 14

through

Table 21

2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of

BCLK and the falling edge of BCLK# at the crossing point for differential clock mode and to

the rising edge of BCLK at BCLK

VREF

(1.25 V) for single-ended clock mode. All AGTL

signal timings (address bus, data bus, etc.) are referenced at 2/3V

at the processor pins.

3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising

edge at 0.9 V. All APIC I/O signal timings are referenced at 1.0 V at the processor pins.

4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at

1.0 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.

Table 22. Platform Power-On Timings

T# Parameter

Min

Max

Unit

Figure

Notes

T45: Valid Time Before VTT_PWRGD

1.0

T46: Valid Time Before PWRGOOD

2.0

T47: RESET# Inactive to Valid Outputs

BCLK

T48: RESET# Inactive to Drive Signals

BCLK

Figure 9. Clock Waveform

V ih

B C L K #

B C L K

V il

V c ro s s

T p

T p = T 1 (B C L K P e rio d )

N O T E : S in g le -E n d e d c lo c k u s e s B C L K o n ly ,
D iffe re n tia l c lo c k u s e s B L C K a n d B C L K #

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Figure 10. BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform

Figure 11. System Bus Valid Delay Timings

Vringback

(rise)

Vringback

(fall)

= T5, T25, T34, (Rise Tim e)

= T6, T26, T35, (Fall Tim e)

= T3, T23, T32, (High Tim e)

= T4, T24, T33, (Low Tim e)

= T1, T22, T31 (BC LK, TCK, PIC CLK Period)

V1 = BCLK is referenced to 0.30V (D ifferential Mode), 0.50V (Single-Ended Mode)

TCK is referenced to Vref - 200 m V, PICC LK is referenced to 0.4V.

V2 = BCLK is refernced to 0.9V (Differental Mode), 2.0V (Single-Ended Mode)

TCK is referenced to Vref + 200 m V, PICC LK is refernced to 1.6V

V3 = BCLK and BLCK# crossing point of the rising edge of BLCK and the falling edge of BCLK# (Differential Mode),

BCLK i refereced to 1.25V (Single-Ended Mode), PIC CLK is reference to 1.0V, TCK is referenced to Vcm osref

Vih diff

Vil diff

BCLK

Signal

Valid

Tpw

Tx = T7, T29a, T29b (Valid Delay)

Tpw = T14, T15 (Pulse Width)

V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups

BCLK#

Valid

NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.0

Signal Quality Specifications

Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term

reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in

Table 23

Table 24

, and

Table 27

ensures that

signal quality effects will not adversely affect processor operation.

3.1

BCLK/BCLK# & PICCLK Signal Quality Specifications and

Measurement Guidelines

Table 24

describes the signal quality specifications at the processor pins for the processor system

bus clock (BCLK/BCLK#) and APIC clock (PICCLK) signals. References made to BCLK signal

quality specifications also applies to BCLK#.

Figure 18

describes the signal quality waveform for

the system bus clock at the processor pins.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the BCLK/BCLK# and PICCLK signals can dip back to after passing the V

(rising) or V

(falling)

voltage limits. This specification is an absolute value.

Table 23. BCLK (Single-Ended Clock Mode) Signal Quality Specifications for Simulation at

the Processor Pins

T# Parameter

Min

Nom

Max

Unit

Figure

Notes

V1: BCLK V

0.3

V2: BCLK V

2.2

V3: BCLK Absolute Voltage Range

-0.5

3.1

V4: BCLK Rising Edge Ringback

2.0

V5: BCLK Falling Edge Ringback

0.5

Table 24. BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality Specifications

for Simulation at the Processor Pins

T# Parameter

Min

Nom

Max

Unit

Figure

Notes

V1: BCLK V

-0.2

0.35

V1: PICCLK V

0.40

V2: BCLK V

0.92

1.45

V2 PICCLK V

1.60

V3: BCLK Absolute Voltage Range

-0.2

1.45

V3: PICCLK Absolute Voltage Range

-0.4

2.4

V4: BCLK Rising Edge Ringback

0.35

V4: PICCLK Rising Edge Ringback

1.60

V5: BCLK Falling Edge Ringback

-0.35

V5: PICCLK Falling Edge Ringback

0.40

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.2

AGTL Signal Quality Specifications and Measurement

Guidelines

Many scenarios have been simulated to generate a set of AGTL layout guidelines which are
available in the appropriate platform design guide. Refer to the Intel

Pentium

II Processor

Developer's Manual (Order Number 243502) for the AGTL buffer specification.

Table 25

provides the AGTL signal quality specifications for the processor for use in simulating

signal quality at the processor pins.

The processor maximum allowable overshoot and undershoot specifications for a given duration of
time are detailed in

Table 24

through

Table 26

Figure 19

shows the AGTL ringback tolerance and

Figure 20

shows the overshoot/undershoot waveform.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. Specifications are for the edge rate of 0.3 3 V/ns. See

Figure 19

for the generic waveform.

3. All values specified by design characterization.
4. See

Table 24

for maximum allowable overshoot.

5. Ringback between V

REF

+ 100 mV and V

REF

+ 200 mV or V

REF

300 mV and V

REF

100 mVs requires the

flight time measurements to be adjusted as described in the Intel AGTL Specifications. Ringback below
V

REF

+ 100 mV or above V

REF

100 mV is not supported.

6. Intel recommends simulations not exceed a ringback value of V

REF

±200 mV to allow margin for other

sources of system noise.

7. A negative value for

indicates that the amplitude of ringback is above V

REF

. (i.e.,

= -100 mV specifies the

signal cannot ringback below V

REF

+ 100 mV).

and

: are measured relative to V

REF

: is measured relative to V

REF

+ 200 mV.

Figure 18. BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins

Table 25. AGTL Signal Groups Ringback Tolerance Specifications at the Processor Pins

T# Parameter

Min

Unit

Figure

Notes

1,2,3

: Overshoot

100

4, 8

: Minimum Time at High

0.50

: Amplitude of Ringback

±200

5, 6, 7, 8

: Final Settling Voltage

200

: Duration of Squarewave Ringback

N/A

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.2.1

Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V

. The overshoot guideline limits transitions beyond V

or V

due to the fast

signal edge rates. The processor can be damaged by repeated overshoot events on 1.25 V or 2.5 V

tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of

excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.

When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide

overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the processor performance, care must be taken to ensure that ESD

models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O capacitance
characterization. Therefore, removing the ESD diodes from an I/O Buffer model will impact results
and may yield excessive overshoot/undershoot.

Figure 19. Low to High AGTL Receiver Ringback Tolerance

i b k

t l

0.7V Clk Ref

Clock

Time

start

REF

- 0.2

REF

+ 0.2

Note: High to low case is analogous

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.2.2

Overshoot/Undershoot Magnitude

Magnitude describes the maximum potential difference between a signal and its voltage reference
level, V

(overshoot) and V

(undershoot). While overshoot can be measured relative to V

using one probe (probe to signal and GND lead to V

), undershoot must be measured relative to

. This could be accomplished by simultaneously measuring the V

plane while measuring the

signal undershoot. Today's oscilloscopes can easily calculate the true undershoot waveform. The

true undershoot waveform can also be obtained with the following oscilloscope data file analysis:

Converted Undershoot Waveform = V

- Signal_measured

Note: The converted undershoot waveform appears as a positive (overshoot) signal.

Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact

must be determined independently.

After the true waveform conversion, the undershoot/overshoot specifications shown in

Table 26

through

Table 29

can be applied to the converted undershoot waveform using the same magnitude

and pulse duration specifications used with an overshoot waveform.

Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in

Table 26

through

Table 29

. These specifications must not be violated at any time regardless of

bus activity or system state. Within these specifications are threshold levels that define different

allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications (1.78 V AGTL, 2.08 V CMOS), the pulse magnitude, duration
and activity factor must all be used to determine if the overshoot/undershoot pulse is within

specifications.

3.2.3

Overshoot/Undershoot Pulse Duration

Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.32 V AGTL, 1.80 V CMOS). The total time could

encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses
within a single overshoot/undershoot event may need to be measured to determine the total pulse
duration.

Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot

pulse duration.

Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered

together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the

individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that
total event.

3.2.4

Activity Factor

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a

clock. Since the highest frequency of assertion of an AGTL or a CMOS signal is every other clock,
an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER
clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform

occurs one time in every 200 clock cycles.

The specifications provided in

Table 26

through

Table 29

show the Maximum Pulse Duration

allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table
entry is independent of all others, meaning that the Pulse Duration reflects the existence of

overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can
be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the

event occurs at all times and no other events can occur).

Note: Activity factor for AGTL signals is referenced to system bus clock frequency.

Note: Activity factor for CMOS signals is referenced to PICCLK frequency.

3.2.5

Reading Overshoot/Undershoot Specification Tables

The overshoot/undershoot specification for the processor is not a simple single value. Instead,

many factors are needed to determine what the over/undershoot specification is. In addition to the
magnitude of the overshoot, the following parameters must also be known: the junction
temperature the processor will be operating at, the width of the overshoot (as measured above
TBD V) and the Activity Factor (AF). To determine the allowed overshoot for a particular

overshoot event, the following must be done:

1. Determine the signal group that particular signal falls into. If the signal is an AGTL signal

operating with a 100 MHz system bus, use

Table 27

(100 MHz AGTL signal group). If the

signal is a CMOS signal, use

Table 28

(33 MHz CMOS signal group).

2. Determine the maximum case temperature (Tcase) for the range of processors that the system

will support (65

C).

3. Determine the Magnitude of the overshoot (relative to V

)

4. Determine the Activity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)

allowed.

6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse

Duration measured is less than the Pulse Duration shown in the table, then the signal meets the

specifications.

The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.

Below is an example showing how the maximum pulse duration is determined for a given

waveform.

Given the above parameters, and using

Table 27

(65

C/AF = 0.1 column) the maximum allowed

pulse duration is 7.5 ns. Since the measure pulse duration is 7.5 ns, this particular overshoot event
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/

undershoot events meet the specifications.

Table 26. Example Platform Information

Required Information

Maximum Platform Support

Notes

PSB Signal Group

100 MHz AGTL

Max Tcase

72 °C

Overshoot Magnitude

1.78 V

Measured Value

Activity Factor (AF)

0.1

Measured overshoot occurs on
average every 20 clocks

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.2.6

Determining if a System Meets the Overshoot/Undershoot

Specifications

The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have

multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
you add the total impact of all overshoot events, the system may fail. A guideline to ensure a

system passes the overshoot and undershoot specifications is shown below. It is important to meet
these guidelines; otherwise, contact your Intel field representative.

1. Insure no AGTL signal ever exceeds 1.78 V and no CMOS signal ever exceeds 2.08 V.

2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot

specifications in the following tables

3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse

duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.

The following notes apply to

Table 26

through

Table 29

NOTES:

1. Overshoot/Undershoot Magnitude = 1.78 V(AGTL), 2.08 V(CMOS) is an Absolute value and

should never be exceeded

2. Overshoot is measured relative to V

3. Undershoot is measured relative to V

4. Overshoot/Undershoot Pulse Duration is measured relative to 1.32 V for AGTL and 1.80 V for

CMOS.

5. Rinbacks below V

can not be subtracted from Overshoots/Undershoots

6. Lesser Undershoot does not allocate longer or larger Overshoot

7. OEM's are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines

provided in the specific platform design guide.

8. All values specified by design characterization

Notes: 1. Measurements taken at the processor socket pins on the solder-side of the motherboard.

2. Overshoot/Undershoot Magnitude = 1.78 V is an absolute value and should never be exceeded.
3. BCLK Period = 10.0 ns.

Table 27. 100 MHz AGTL Signal Group Overshoot/Undershoot Tolerance

1, 2, 3

Overshoot/

Undershoot

Magnitude

(V)

Maximum Pulse

Duration at

Tcase = 60 °C (ns)

Maximum Pulse

Duration at

Tcase = 69 °C (ns)

Maximum Pulse

Duration at

Tcase = 71 °C (ns)

Maximum Pulse

Duration at

Tcase = 72 °C (ns)

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

1.78

1.5

0.153

8.7

0.87

0.087

0.6

0.06

0.6

0.06

1.73

3.1

0.31

2.0

0.20

1.3

0.13

1.2

0.12

1.68

6.8

0.68

4.6

0.46

2.8

0.28

2.7

0.27

1.63

1.42

1.0

6.0

0.6

5.7

0.57

1.58

2.95

2.3

12.7

1.27

1.2

1.53

6.2

5.0

2.65

2.46

1.48

13.2

5.45

5.10

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.3

Non-AGTL Signal Quality Specifications and Measurement

Guidelines

There are three signal quality parameters defined for non-AGTL signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in

Figure 21

for the non-

AGTL signal group.

NOTE:

1. V

= 1.80 V for all non-AGTL signals except for BCLK, PICCLK, and PWRGOOD. V

=2.0 V for PICCLK,

and V

=1.8 V for PWRGOOD. BCLK and PICCLK signal quality is detailed in

Section 3.1

Figure 20. Maximum Acceptable AGTL Overshoot/Undershoot Waveform

Vos_ref

1.78 V Max

1.32 V

Vss

Time dependent Overshoot

Time dependent Undershoot

-0.46 V Min

0.1 ns

0.3 ns

1 ns

0.1 ns

0.3 ns

1 ns

1.47 V

1.62 V

-0.15 V
-0.30 V

Figure 21. Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback

Undershoot

Overshoot

Settling Limit

Rising-Edge
Ringback

Falling-Edge
Ringback

Time

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

3.3.1

Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V

. The overshoot guideline limits transitions beyond V

or V

due to the fast

signal edge rates (see

Figure 21

for non-AGTL signals). The processor can be damaged by repeated

overshoot events on 1.25 V or 1.8 V tolerant buffers if the charge is large enough (i.e., if the
overshoot is great enough). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the

ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the
absence of diodes on the input. These guidelines should be verified in simulations without the on-
chip ESD protection diodes present because the diodes will begin clamping the 1.25 V and 2.5 V

tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below
V

. If signals are not reaching the clamping voltage, this will not be an issue. A system should not

rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.

Note: The undershoot guideline limits transitions exactly as described for the ATGL signals. See

Figure 20

3.3.2

Ringback Specification

Ringback refers to the amount of reflection seen after a signal has switched. The ringback

specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See

Figure 21

for an illustration of ringback. Excessive ringback can cause false signal

detection or extend the propagation delay. The ringback specification applies to the input pin of

each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL signals.

Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See

Table 29

for the signal ringback specifications for non-AGTL signals for simulations at the

processor pins.

Table 28. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance

Overshoot/

Undershoot

Magnitude

(V)

Maximum Pulse Duration at

Tcase = 69 °C (ns)

Maximum Pulse Duration at

Tcase = 71 °C (ns)

Maximum Pulse Duration at

Tcase = 72 °C (ns)

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

2.38

3.5

0.35

1.9

0.19

1.7

0.17

2.33

8.0

0.8

4.0

0.40

3.6

0.36

2.28

1.8

8.0

0.80

7.7

0.77

2.23

4.1

1.80

1.60

2.18

9.0

37.5

3.75

3.42

2.13

8.00

7.12

2.08

16.00

14.5

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTES:

1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. Non-AGTL signals except PWRGOOD.

3.3.3

Settling Limit Guideline

Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach

before its next transition. The amount allowed is 10% of the total signal swing (V

) above

and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.

Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be

done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.

3.4

VTT_PWRGD Signal Quality Specification

The VTT_PWRGD signal is an input to the processor used to determine that the V

power is

stable and the VID and BSEL signals should be driven to their final state by the processor. To

ensure the processor correctly reads this signal, it must meet the following requirement while the
signal is in its transition region of 300 mV to 900 mV. Also, VTT_PWRGD should only enter the
transition region once, after V

is at nominal values, for the assertion of the signal.

Amount of noise (glitch) < 100 mV

In addition, the VTT_PWRGD signal should have a reasonable transition time through the
transition region. A sharp edge on the signal transition will minimize the chance of noise causing a
glitch on this signal. Intel recommends the following transition time for the VTT_PWRGD signal.

Transition time (300 mV to 900 mV)

100 us

3.4.1

Transition region

The transition region covered by this requirement is 300 mV to 900 mV. Once the VTT_PWRGD

signal is in that voltage range, the processor is more sensitive to noise which may be present on the
signal. The transition region when the signal first crosses the 300 mV voltage level and continues
until the last time it is below 900 mV.

Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor

Pins

Input Signal Group

Transition

Maximum Ringback

(with Input Diodes Present)

Unit

Figure

Non-AGTL Signals

Vcmos_ref + 0.200

Non-AGTL Signals

Vcmos_ref - 0.300

PWRGOOD

1.44

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

4.0

Thermal Specifications and Design Considerations

This chapter provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to Intel

Pentium

III

Processor in the FC-PGA2, 370-pin

Package Thermal Design Guidelines (Order Number 249660). The processor uses flip chip pin
grid array packaging technology with a Integrated Heat Spreader and has a case temperature (T

case

)

specified.

4.1

Thermal Specifications

Table 30

provides the thermal design power dissipation and maximum temperatures for the

processor. Systems should design for the highest possible processor power, even if a processor with
a lower thermal dissipation is planned. A thermal solution should be designed to ensure the case

temperature never exceeds these specifications.

1. These values are specified at nominal V

CORE

for the processor pins.

2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL bus

termination. The maximum power for each of these components does not occur simultaneously.

3. Processor core power includes only the power dissipated by the core die.
4. For frequencies beyond 1.4 GHz, refer to the latest flexible motherboard 1 extended (FMB1-E) guidelines

available via your Intel Representative.

5. 1.20 GHz at Vcc

CORE

= 1.475 volts and S-Spec number SL5XS.

4.1.1

THERMTRIP# Requirement

In the event the processor drives the THERMTRIP# signal active during valid operation, both the

and V

supplies to the processor must be turned off to prevent thermal runaway of the

processor. Valid operation refers to the operating conditions where the THERMTRIP# signal is
guaranteed valid. The time required from THERMTRIP# asserted to V

rail at 1/2 nominal is 5 s

and THERMTRIP# asserted to V

rail at 1/2 nominal is 5 s.

NOTE:

Once V

and V

supplies are turned off the THERMTRIP# signal will be deactivated. System logic

should ensure no "unsafe" power cycling occurs due to this deassertion.

Table 30. Processor Thermal Design Power

Processor

Processor Core

Frequency

L2 Cache Size

(Kbytes)

Processor Power

(W)

Maximum T

CASE

(°C)

1.40

256

34.8

1.30

1.30 GHz

256

33.4

1.20

1.20 GHz

256

32.1

1.20

1.20 GHz

256

29.9

1.10A

1.10A GHz

256

28.9

1A GHz

256

27.8

900

900 MHz

256

26.3

Table 31. THERMTRIP# Time Requirement

Power Rail

Power Target

Time Required for Power Drop

1/2 Nominal V

5 seconds

1/2 Nominal V

5 seconds

Datasheet

Intel

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Processor for PGA370 up to 1.40 GHz on 0.13

Process

4.1.2

Thermal Diode

The processor incorporates an on-die diode that may be used to monitor the die temperature
(junction temperature). A thermal sensor located on the motherboard, or a stand-alone

measurement kit, may monitor the die temperature of the processor for thermal management or
instrumentation purposes.

Table 32

and

Table 33

provide the diode parameter and interface

specifications.

The processor uses an Integrated Heat Spreader (IHS) and has a case temperature requirement.

Please see the Intel

Pentium

III

Processor in the FC-PGA2, 370-pin Package Thermal Design

Guidelines document for details on measuring the case temperature. The thermal diode should be
used for system thermal management and not determining spec compliance.

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 75

C with a forward bias current of 5 150

3. Characterized at 75

C with a forward bias current of 5 300

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation:
I

=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the

diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

5. Not 100% tested. Specified by design characterization.

4.2

Thermal Metrology

The thermal metrology for the processor in the FC-PGA2 package should be followed to evaluate
the thermal performance of proposed cooling solutions. The thermal metrology is contained in the
Intel

Pentium

III

Processor in the FC-PGA2, 370-pin Package Thermal Design Guidelines.

Please contact your local Intel field office to obtain this document.

Table 32. Thermal Diode Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Forward Bias Current

N/A

150

µA

Diode Ideality Factor

1.001452

1.007152

1.012852

2, 4, 5

Forward Bias Current

N/A

300

µA

Diode Ideality Factor

1.000807

1.009528

1.018249

3, 4, 5

Table 33. Thermal Diode Interface

Pin Name

PGA370 Socket pin #

Pin Description

THERMDP

AL31

diode anode (p_junction)

THERMDN

AL29

diode cathode (n_junction)

Datasheet

Intel

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Processor for PGA370 up to 1.40 GHz on 0.13

Process

5.0

Mechanical Specifications

The processor uses a FC-PGA2 package technology. Mechanical specifications for the processor
are given in this section. See

Section 1.1.1

for a complete terminology listing.

The processor utilizes a PGA370 socket for installation into the motherboard. Details on the socket

are available in the 370-Pin Socket (PGA370) Design Guidelines.

Note: For

Figure 23

, the following apply:

1. Unless otherwise specified, the following drawings are dimensioned in inches.

2. All dimensions provided with tolerances are guaranteed to be met for all normal production

product.

3. Figures and drawings labeled as "Reference Dimensions" are provided for informational

purposes only. Reference dimensions are extracted from the mechanical design database and

are nominal dimensions with no tolerance information applied. Reference dimensions are
NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in
parentheses without tolerances are reference dimensions.

4. Drawings are not to scale.

5.1

FC-PGA2 Mechanical Specifications

The following figure with package dimensions is provided to aid in the design of heatsink and clip
solutions as well as demonstrate where pin-side capacitors will be located on the processor.

Table 34

includes the measurements for these dimensions in both inches and millimeters.

Figure 23. Package Dimensions

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTE:

Capacitors will be placed on the pin-side of the FC-PGA2 package in the area defined by G1, G2, and
G3. This area is a keepout zone for motherboard designers.

For

Table 35

, the following apply:

1. It is not recommended to use any portion of the processor substrate as a mechanical reference

or load bearing surface for thermal solutions.

2. Parameters assume uniformly applied loads

NOTES:

1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

processor interface.

3. Please see socket manufacturer's force loading specification also to ensure compliance. Maximum static

loading listed here does not account for the maximum reaction forces on the socket tabs or pins.

Table 34. The Processor Package Dimensions

Symbol

Millimeters

Inches

Minimum

Maximum

Notes

Minimum

Maximum

Notes

2.266

2.690

0.089

0.106

0.980

1.180

0.038

0.047

30.800

31.200

1.212

1.229

30.800

31.200

1.212

1.229

33.000 max

1.299 max

33.000 max

1.299 max

49.428

49.632

1.946

1.954

45.466

45.974

1.790

1.810

0.000

17.780

0.000

0.700

0.000

17.780

0.000

0.700

0.000

0.889

0.000

0.035

2.540

Nominal

0.100

Nominal

3.048

3.302

0.120

0.130

0.431

0.483

0.017

0.019

Pin TP

0.508 Diametric True Position (Pin-to-Pin)

0.020 Diametric True Position (Pin-to-Pin)

Table 35. Processor Case Loading Parameters

Parameter

Dynamic (max)

Static (max)

2,3

Unit

IHS Surface

200

100

lbf

IHS Edge

125

N/A

lbf

IHS Corner

N/A

ibf

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

5.4

Processor Signal Listing

Table 36

and

Table 37

provide the processor pin definitions. The signal locations on the PGA370

socket are to be used for signal routing, simulation, and component placement on the baseboard.

Figure 27

provides a pin-side view of the processor pinout.

Figure 27. Processor Pinout

VSS

VCC

VSS

D35

D29

D33

D26

D28

D21

D23

D25

VSS

VCC

VSS

D31

VCC

D43

VCC

VSS

D34

D38

VCC

VSS

D39

D36

VCC

D37

D44

VCC

D32

D22

RSV

D27

VSS

D42

D45

D49

VSS

VCC

D63

VREF1

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSV

VTT

D62

SLEW

CTRL

DEP6

DEP4

VREF0

BPM1

BP3

D41

D52

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

D40

D59

D55

D54

D58

D50

D56

DEP5

DEP1

DEP0

BPM0

CPUPRES

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BINIT

D51

D47

D48

D57

D46

D53

D60

D61

DEP7

DEP3

DEP2

PRDY

VSS

BP2

VTT

VCC

VSS

VCC

PICCLK

PICD0

PREQ

VCC

VSS

RSV

PICD1

LINT1

VCC

VSS

LINT0

RSV

VSS

VCC

VSS

NCHCTRL

RSV

VCC

VSS

VCC

VTT

RTT

CTRL

VTT

VSS

VCC

VSS

PLL2

VTT

VCC

VSS

VCC

BCLK#/

CLKREF

VCC

VSS

VCC

VSS

RSV

VTT

VCC

VSS

VCC

VTT

VSS

FERR

RSP

VCC

VSS

VTT

A20M

IERR

FLUSH

VSS

VCC

DETECT

INIT

VSS

VTT

VSS

PLL1

RSV

BCLK

STPCLK

IGNNE

VSS

D16

D19

D30

VCC

VREF2

D24

D13

D20

VSS

D11

D14

VCC

D18

D12

D10

VSS

RSV

D17

VREF3

VCC

D15

VSS

BERR

VREF4

A34

VCC

RSV

VSS

A32

RSV

A26

VSS

A29

A18

A27

A30

VCC

A24

A23

A33

A20

VSS

A31

VREF5

A17

A22

VCC

A35

A25

VTT

A19

VSS

RESET

A10

BNR

REQ1

REQ2

VTT

RS1

VCC

RS0

THERM

TRIP

SLP

VCC

VSS

VCC

A21

RESET2#

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BSEL1

BSEL0

SMI

VID3

VCC

VttPWRGD A28

A11

VREF6

A14

VTT

REQ0

LOCK

CMOSREF

AERR

PWRGD

RS2

RSV

TMS

VCC

VID25m

RSV

VSS

A15

A13

AP0

VTT

REQ4

REQ3

VTT

HITM

HIT

DBSY

THRMDN

THRMDP

TCK

VID0

VID2

KEY

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VID1

DYN_OE

A12

A16

VTT

AP1

VTT

BPRI

DEFER

VTT

TRDY

DRDY

BR0

ADS

TRST

TDI

TDO

Pin Side View

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Table 36. Signal Listing in Order by

Signal Name

Pin
No.

Pin Name

Signal Group

AH6

A10#

AGTL I/O

AK10

A11#

AGTL I/O

AN5

A12#

AGTL I/O

AL7

A13#

AGTL I/O

AK14

A14#

AGTL I/O

AL5

A15#

AGTL I/O

AN7

A16#

AGTL I/O

AE1

A17#

AGTL I/O

A18#

AGTL I/O

AG3

A19#

AGTL I/O

AC3

A20#

AGTL I/O

AE33

A20M#

CMOS Input

AJ1

A21#

AGTL I/O

AE3

A22#

AGTL I/O

AB6

A23#

AGTL I/O

AB4

A24#

AGTL I/O

AF6

A25#

AGTL I/O

A26#

AGTL I/O

AA1

A27#

AGTL I/O

AK6

A28#

AGTL I/O

A29#

AGTL I/O

AK8

A3#

AGTL I/O

AA3

A30#

AGTL I/O

AD4

A31#

AGTL I/O

A32#

AGTL I/O

AC1

A33#

AGTL I/O

A34#

AGTL I/O

AF4

A35#

AGTL I/O

AH12

A4#

AGTL I/O

AH8

A5#

AGTL I/O

AN9

A6#

AGTL I/O

AL15

A7#

AGTL I/O

AH10

A8#

AGTL I/O

AL9

A9#

AGTL I/O

AN31

ADS#

AGTL I/O

AK24

AERR#

AGTL I/O

AL11

AP0#

AGTL I/O

AN13

AP1#

AGTL I/O

W37

BCLK

System Bus Clock

Y33

BCLK#/CLKREF

System Bus Clock

BERR#

AGTL I/O

B36

BINIT#

AGTL I/O

AH14

BNR#

AGTL I/O

G33

BP2#

AGTL I/O

E37

BP3#

AGTL I/O

C35

BPM0#

AGTL I/O

E35

BPM1#

AGTL I/O

AN17

BPRI#

AGTL Input

AN29

BR0#

AGTL I/O

Reserved

AGTL I/O

AJ33

BSEL0

3.3V Output

AJ31

BSEL1

3.3V Output

C37

CPUPRES#

Power/Other

D0#

AGTL I/O

D1#

AGTL I/O

D10#

AGTL I/O

D11#

AGTL I/O

D12#

AGTL I/O

D13#

AGTL I/O

D14#

AGTL I/O

D15#

AGTL I/O

D16#

AGTL I/O

D17#

AGTL I/O

D18#

AGTL I/O

D19#

AGTL I/O

D2#

AGTL I/O

D20#

AGTL I/O

D21#

AGTL I/O

D22#

AGTL I/O

D23#

AGTL I/O

D24#

AGTL I/O

D25#

AGTL I/O

D26#

AGTL I/O

F12

D27#

AGTL I/O

D28#

AGTL I/O

D29#

AGTL I/O

D3#

AGTL I/O

D30#

AGTL I/O

D31#

AGTL I/O

D32#

AGTL I/O

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

D33#

AGTL I/O

D34#

AGTL I/O

D35#

AGTL I/O

D36#

AGTL I/O

D37#

AGTL I/O

D38#

AGTL I/O

D10

D39#

AGTL I/O

D4#

AGTL I/O

C15

D40#

AGTL I/O

D14

D41#

AGTL I/O

D12

D42#

AGTL I/O

D43#

AGTL I/O

A11

D44#

AGTL I/O

C11

D45#

AGTL I/O

A21

D46#

AGTL I/O

A15

D47#

AGTL I/O

A17

D48#

AGTL I/O

C13

D49#

AGTL I/O

D5#

AGTL I/O

C25

D50#

AGTL I/O

A13

D51#

AGTL I/O

D16

D52#

AGTL I/O

A23

D53#

AGTL I/O

C21

D54#

AGTL I/O

C19

D55#

AGTL I/O

C27

D56#

AGTL I/O

A19

D57#

AGTL I/O

C23

D58#

AGTL I/O

C17

D59#

AGTL I/O

D6#

AGTL I/O

A25

D60#

AGTL I/O

A27

D61#

AGTL I/O

E25

D62#

AGTL I/O

F16

D63#

AGTL I/O

D7#

AGTL I/O

D8#

AGTL I/O

D9#

AGTL I/O

AL27

DBSY#

AGTL I/O

AN19

DEFER#

AGTL Input

C33

DEP0#

AGTL I/O

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

C31

DEP1#

AGTL I/O

A33

DEP2#

AGTL I/O

A31

DEP3#

AGTL I/O

E31

DEP4#

AGTL I/O

C29

DEP5#

AGTL I/O

E29

DEP6#

AGTL I/O

A29

DEP7#

AGTL I/O

AF36

DETECT

Power/Other

AN27

DRDY#

AGTL I/O

AN3

DYN_OE

Power/Other

AC35

FERR#

CMOS Output

AE37

FLUSH#

CMOS Input

AL25

HIT#

AGTL I/O

AL23

HITM#

AGTL I/O

AE35

IERR#

CMOS Output

AG37

IGNNE#

CMOS Input

AG33

INIT#

CMOS Input

AM2

KEY

Power/Other

M36

LINT0/INTR

CMOS Input

L37

LINT1/NMI

CMOS Input

AK20

LOCK#

AGTL I/O

N37

NCHCTRL

Power/Other

J33

PICCLK

APIC Clock Input

J35

PICD0

APIC I/O

L35

PICD1

APIC I/O

W33

PLL1

Power/Other

U33

PLL2

Power/Other

A35

PRDY#

AGTL Output

J37

PREQ#

CMOS Input

AK26

PWRGOOD

CMOS Input

AK18

REQ0#

AGTL I/O

AH16

REQ1#

AGTL I/O

AH18

REQ2#

AGTL I/O

AL19

REQ3#

AGTL I/O

AL17

REQ4#

AGTL I/O

AK30

Reserved

Reserved for future use

AL1

Reserved

Reserved for future use

F10

Reserved

Reserved for future use

E21

Reserved

Reserved for future use

L33

Reserved

Reserved for future use

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

N33

Reserved

Reserved for future use

N35

Reserved

Reserved for future use

Q33

Reserved

Reserved for future use

Q35

Reserved

Reserved for future use

Q37

Reserved

Reserved for future use

Reserved

Reserved for future use

W35

Reserved

Reserved for future use

Reserved

Reserved for future use

Z36

Reserved

Reserved for future use

AH4

RESET#

AGTL Input

AJ3

RESET2#

AGTL Input

AN23

RP#

AGTL I/O

AH26

RS0#

AGTL + Input

AH22

RS1#

AGTL Input

AK28

RS2#

AGTL Input

AC37

RSP#

AGTL Input

S35

RTTCTRL

Power/Other

E27

SLEWCTRL

Power/Other

AH30

SLP#

CMOS Input

AJ35

SMI#

CMOS Input

AG35

STPCLK#

CMOS Input

AL33

TCK

TAP Input

AN35

TDI

TAP Input

AN37

TDO

TAP Output

AL29

THERMDN

Power/Other

AL31

THERMDP

Power/Other

AH28

THERMTRIP# CMOS Output

AK32

TMS

TAP Input

AN25

TRDY#

AGTL Input

AN33

TRST#

TAP Input

AA37

CORE

Power/Other

AA5

CORE

Power/Other

AB2

CORE

Power/Other

AB34

CORE

Power/Other

AD32

CORE

Power/Other

AE5

CORE

Power/Other

AF2

CORE

Power/Other

AF34

CORE

Power/Other

AH24

CORE

Power/Other

AH32

CORE

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

AH36

CORE

Power/Other

AJ13

CORE

Power/Other

AJ17

CORE

Power/Other

AJ21

CORE

Power/Other

AJ25

CORE

Power/Other

AJ29

CORE

Power/Other

AJ5

CORE

Power/Other

AJ9

CORE

Power/Other

AK2

CORE

Power/Other

AK34

CORE

Power/Other

AM12

CORE

Power/Other

AM16

CORE

Power/Other

AM20

CORE

Power/Other

AM24

CORE

Power/Other

AM28

CORE

Power/Other

AM32

CORE

Power/Other

AM4

CORE

Power/Other

AM8

CORE

Power/Other

B10

CORE

Power/Other

B14

CORE

Power/Other

B18

CORE

Power/Other

B22

CORE

Power/Other

B26

CORE

Power/Other

B30

CORE

Power/Other

B34

CORE

Power/Other

CORE

Power/Other

CORE

Power/Other

D20

CORE

Power/Other

D24

CORE

Power/Other

D28

CORE

Power/Other

D32

CORE

Power/Other

D36

CORE

Power/Other

CORE

Power/Other

E13

CORE

Power/Other

E17

CORE

Power/Other

CORE

Power/Other

CORE

Power/Other

F14

CORE

Power/Other

CORE

Power/Other

F22

CORE

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

F26

CORE

Power/Other

F30

CORE

Power/Other

F34

CORE

Power/Other

CORE

Power/Other

H32

CORE

Power/Other

H36

CORE

Power/Other

CORE

Power/Other

CORE

Power/Other

K32

CORE

Power/Other

K34

CORE

Power/Other

M32

CORE

Power/Other

CORE

Power/Other

CORE

Power/Other

P34

CORE

Power/Other

R32

CORE

Power/Other

R36

CORE

Power/Other

CORE

Power/Other

CORE

Power/Other

T34

CORE

Power/Other

V32

CORE

Power/Other

V36

CORE

Power/Other

CORE

Power/Other

Y35

CORE

Power/Other

Z32

CORE

Power/Other

AK22

CMOS_REF

Power/Other

AK36

VID 25mV

3.3V Output

AL35

VID0

3.3V Output

AM36

VID1

3.3V Output

AL37

VID2

3.3V Output

AJ37

VID3

3.3V Output

E33

REF

Power/Other

F18

REF

Power/Other

REF

Power/Other

REF

Power/Other

REF

Power/Other

AD6

REF

Power/Other

AK12

REF

Power/Other

A37

Vss

Power/Other

AB32

Vss

Power/Other

AC33

Vss

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

AC5

Vss

Power/Other

AD2

Vss

Power/Other

AD34

Vss

Power/Other

AF32

Vss

Power/Other

AG5

Vss

Power/Other

AH2

Vss

Power/Other

AH34

Vss

Power/Other

AJ11

Vss

Power/Other

AJ15

Vss

Power/Other

AJ19

Vss

Power/Other

AJ23

Vss

Power/Other

AJ27

Vss

Power/Other

AJ7

Vss

Power/Other

AL3

Vss

Power/Other

AM10

Vss

Power/Other

AM14

Vss

Power/Other

AM18

Vss

Power/Other

AM22

Vss

Power/Other

AM26

Vss

Power/Other

AM30

Vss

Power/Other

AM34

Vss

Power/Other

AM6

Vss

Power/Other

B12

Vss

Power/Other

B16

Vss

Power/Other

B20

Vss

Power/Other

B24

Vss

Power/Other

B28

Vss

Power/Other

B32

Vss

Power/Other

Vss

Power/Other

Vss

Power/Other

D18

Vss

Power/Other

Vss

Power/Other

D22

Vss

Power/Other

D26

Vss

Power/Other

D30

Vss

Power/Other

D34

Vss

Power/Other

Vss

Power/Other

E11

Vss

Power/Other

E15

Vss

Power/Other

E19

Vss

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Vss

Power/Other

F20

Vss

Power/Other

F24

Vss

Power/Other

F28

Vss

Power/Other

F32

Vss

Power/Other

F36

Vss

Power/Other

Vss

Power/Other

Vss

Power/Other

H34

Vss

Power/Other

K36

Vss

Power/Other

Vss

Power/Other

Vss

Power/Other

M34

Vss

Power/Other

P32

Vss

Power/Other

P36

Vss

Power/Other

Vss

Power/Other

R34

Vss

Power/Other

T32

Vss

Power/Other

T36

Vss

Power/Other

Vss

Power/Other

Vss

Power/Other

V34

Vss

Power/Other

X32

Vss

Power/Other

X36

Vss

Power/Other

Vss

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Y37

Vss

Power/Other

Vss

Power/Other

Vss

Power/Other

Z34

Vss

Power/Other

AB36

Power/Other

AD36

Power/Other

AG1

Power/Other

AH20

Power/Other

AK16

Power/Other

AL13

Power/Other

AL21

Power/Other

AN11

Power/Other

AN15

Power/Other

E23

Power/Other

G35

Power/Other

G37

Power/Other

S33

Power/Other

X34

Power/Other

AA33

Power/Other

AA35

Power/Other

AN21

Power/Other

S37

Power/Other

U35

Power/Other

U37

Power/Other

AK4

_PWRGD

Power/Other

Table 36. Signal Listing in Order by

Signal Name (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

Table 37. Signal Listing in Order by Pin

Number

Pin
No.

Pin Name

Signal Group

D29#

AGTL I/O

D28#

AGTL I/O

D43#

AGTL I/O

D37#

AGTL I/O

A11

D44#

AGTL I/O

A13

D51#

AGTL I/O

A15

D47#

AGTL I/O

A17

D48#

AGTL I/O

A19

D57#

AGTL I/O

A21

D46#

AGTL I/O

A23

D53#

AGTL I/O

A25

D60#

AGTL I/O

A27

D61#

AGTL I/O

A29

DEP7#

AGTL I/O

A31

DEP3#

AGTL I/O

A33

DEP2#

AGTL I/O

A35

PRDY#

AGTL Output

A37

Vss

Power/Other

AA1

A27#

AGTL I/O

AA3

A30#

AGTL I/O

AA5

CORE

Power/Other

AA33

Power/Other

AA35

Power/Other

AA37

CORE

Power/Other

AB2

CORE

Power/Other

AB4

A24#

AGTL I/O

AB6

A23#

AGTL I/O

AB32

Vss

Power/Other

AB34

CORE

Power/Other

AB36

Power/Other

AC1

A33#

AGTL I/O

AC3

A20#

AGTL I/O

AC5

Vss

Power/Other

AC33

Vss

Power/Other

AC35

FERR#

CMOS Output

AC37

RSP#

AGTL Input

AD2

Vss

Power/Other

AD4

A31#

AGTL I/O

AD6

REF

Power/Other

AD32

CORE

Power/Other

AD34

Vss

Power/Other

AD36

Power/Other

AE1

A17#

AGTL I/O

AE3

A22#

AGTL I/O

AE5

CORE

Power/Other

AE33

A20M#

CMOS Input

AE35

IERR#

CMOS Output

AE37

FLUSH#

CMOS Input

AF2

CORE

Power/Other

AF4

A35#

AGTL I/O

AF6

A25#

AGTL I/O

AF32

Vss

Power/Other

AF34

CORE

Power/Other

AF36

DETECT

Power/Other

AG1

Power/Other

AG3

A19#

AGTL I/O

AG5

Vss

Power/Other

AG33

INIT#

CMOS Input

AG35

STPCLK#

CMOS Input

AG37

IGNNE#

CMOS Input

AH2

Vss

Power/Other

AH4

RESET# AGTL

Input

AH6

A10#

AGTL I/O

AH8

A5#

AGTL I/O

AH10

A8#

AGTL I/O

AH12

A4#

AGTL I/O

AH14

BNR#

AGTL I/O

AH16

REQ1#

AGTL I/O

AH18

REQ2#

AGTL I/O

AH20

Power/Other

AH22

RS1#

AGTL Input

AH24

CORE

Power/Other

AH26

RS0#

AGTL + Input

AH28

THERMTRIP# CMOS Output

AH30

SLP#

CMOS Input

AH32

CORE

Power/Other

AH34

Vss

Power/Other

AH36

CORE

Power/Other

AJ1

A21#

AGTL I/O

AJ3

RESET2#

AGTL Input

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

AJ5

CORE

Power/Other

AJ7

Vss

Power/Other

AJ9

CORE

Power/Other

AJ11

Vss

Power/Other

AJ13

CORE

Power/Other

AJ15

Vss

Power/Other

AJ17

CORE

Power/Other

AJ19

Vss

Power/Other

AJ21

CORE

Power/Other

AJ23

Vss

Power/Other

AJ25

CORE

Power/Other

AJ27

Vss

Power/Other

AJ29

CORE

Power/Other

AJ31

BSEL1

3.3V Output

AJ33

BSEL0

3.3V Output

AJ35

SMI#

CMOS Input

AJ37

VID3

3.3V Output

AK2

CORE

Power/Other

AK4

_PWRGD

Power/Other

AK6

A28#

AGTL I/O

AK8

A3#

AGTL I/O

AK10

A11#

AGTL I/O

AK12

REF

Power/Other

AK14

A14#

AGTL I/O

AK16

Power/Other

AK18

REQ0#

AGTL I/O

AK20

LOCK#

AGTL I/O

AK22

CMOS_REF

Power/Other

AK24

AERR#

AGTL I/O

AK26

PWRGOOD

CMOS Input

AK28

RS2#

AGTL Input

AK30

Reserved

Reserved for future use

AK32

TMS

TAP Input

AK34

CORE

Power/Other

AK36

VID 25mV

3.3V Output

AL1

Reserved

Reserved for future use

AL3

Vss

Power/Other

AL5

A15#

AGTL I/O

AL7

A13#

AGTL I/O

AL9

A9#

AGTL I/O

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

AL11

AP0#

AGTL I/O

AL13

Power/Other

AL15

A7#

AGTL I/O

AL17

REQ4#

AGTL I/O

AL19

REQ3#

AGTL I/O

AL21

Power/Other

AL23

HITM#

AGTL I/O

AL25

HIT#

AGTL I/O

AL27

DBSY#

AGTL I/O

AL29

THERMDN

Power/Other

AL31

THERMDP

Power/Other

AL33

TCK

TAP Input

AL35

VID0

3.3V Output

AL37

VID2

3.3V Output

AM2

KEY

Power/Other

AM4

CORE

Power/Other

AM6

Vss

Power/Other

AM8

CORE

Power/Other

AM10

Vss

Power/Other

AM12

CORE

Power/Other

AM14

Vss

Power/Other

AM16

CORE

Power/Other

AM18

Vss

Power/Other

AM20

CORE

Power/Other

AM22

Vss

Power/Other

AM24

CORE

Power/Other

AM26

Vss

Power/Other

AM28

CORE

Power/Other

AM30

Vss

Power/Other

AM32

CORE

Power/Other

AM34

Vss

Power/Other

AM36

VID1

3.3V Output

AN3

DYN_OE

Power/Other

AN5

A12#

AGTL I/O

AN7

A16#

AGTL I/O

AN9

A6#

AGTL I/O

AN11

Power/Other

AN13

AP1#

AGTL I/O

AN15

Power/Other

AN17

BPRI#

AGTL Input

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

AN19

DEFER#

AGTL Input

AN21

Power/Other

AN23

RP#

AGTL I/O

AN25

TRDY#

AGTL Input

AN27

DRDY#

AGTL I/O

AN29

BR0#

AGTL I/O

AN31

ADS#

AGTL I/O

AN33

TRST#

TAP Input

AN35

TDI

TAP Input

AN37

TDO

TAP Output

D35#

AGTL I/O

Vss

Power/Other

CORE

Power/Other

Vss

Power/Other

B10

CORE

Power/Other

B12

Vss

Power/Other

B14

CORE

Power/Other

B16

Vss

Power/Other

B18

CORE

Power/Other

B20

Vss

Power/Other

B22

CORE

Power/Other

B24

Vss

Power/Other

B26

CORE

Power/Other

B28

Vss

Power/Other

B30

CORE

Power/Other

B32

Vss

Power/Other

B34

CORE

Power/Other

B36

BINIT#

AGTL I/O

D33#

AGTL I/O

CORE

Power/Other

D31#

AGTL I/O

D34#

AGTL I/O

D36#

AGTL I/O

C11

D45#

AGTL I/O

C13

D49#

AGTL I/O

C15

D40#

AGTL I/O

C17

D59#

AGTL I/O

C19

D55#

AGTL I/O

C21

D54#

AGTL I/O

C23

D58#

AGTL I/O

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

C25

D50#

AGTL I/O

C27

D56#

AGTL I/O

C29

DEP5#

AGTL I/O

C31

DEP1#

AGTL I/O

C33

DEP0#

AGTL I/O

C35

BPM0#

AGTL I/O

C37

CPUPRES#

Power/Other

Vss

Power/Other

Vss

Power/Other

CORE

Power/Other

D38#

AGTL I/O

D10

D39#

AGTL I/O

D12

D42#

AGTL I/O

D14

D41#

AGTL I/O

D16

D52#

AGTL I/O

D18

Vss

Power/Other

D20

CORE

Power/Other

D22

Vss

Power/Other

D24

CORE

Power/Other

D26

Vss

Power/Other

D28

CORE

Power/Other

D30

Vss

Power/Other

D32

CORE

Power/Other

D34

Vss

Power/Other

D36

CORE

Power/Other

D26#

AGTL I/O

D25#

AGTL I/O

CORE

Power/Other

Vss

Power/Other

CORE

Power/Other

E11

Vss

Power/Other

E13

CORE

Power/Other

E15

Vss

Power/Other

E17

CORE

Power/Other

E19

Vss

Power/Other

E21

Reserved

Reserved for future use

E23

Power/Other

E25

D62#

AGTL I/O

E27

SLEWCTRL

Power/Other

E29

DEP6#

AGTL I/O

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

E31

DEP4#

AGTL I/O

E33

REF

Power/Other

E35

BPM1#

AGTL I/O

E37

BP3#

AGTL I/O

CORE

Power/Other

CORE

Power/Other

D32#

AGTL I/O

D22#

AGTL I/O

F10

Reserved

Reserved for future use

F12

D27#

AGTL I/O

F14

CORE

Power/Other

F16

D63#

AGTL I/O

F18

REF

Power/Other

F20

Vss

Power/Other

F22

CORE

Power/Other

F24

Vss

Power/Other

F26

CORE

Power/Other

F28

Vss

Power/Other

F30

CORE

Power/Other

F32

Vss

Power/Other

F34

CORE

Power/Other

F36

Vss

Power/Other

D21#

AGTL I/O

D23#

AGTL I/O

Vss

Power/Other

G33

BP2#

AGTL I/O

G35

Power/Other

G37

Power/Other

Vss

Power/Other

D16#

AGTL I/O

D19#

AGTL I/O

H32

CORE

Power/Other

H34

Vss

Power/Other

H36

CORE

Power/Other

D7#

AGTL I/O

D30#

AGTL I/O

CORE

Power/Other

J33

PICCLK

APIC Clock Input

J35

PICD0

APIC I/O

J37

PREQ#

CMOS Input

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

CORE

Power/Other

REF

Power/Other

D24#

AGTL I/O

K32

CORE

Power/Other

K34

CORE

Power/Other

K36

Vss

Power/Other

D13#

AGTL I/O

D20#

AGTL I/O

Vss

Power/Other

L33

Reserved

Reserved for future use

L35

PICD1

APIC I/O

L37

LINT1/NMI

CMOS Input

Vss

Power/Other

D11#

AGTL I/O

D3#

AGTL I/O

M32

CORE

Power/Other

M34

Vss

Power/Other

M36

LINT0/INTR

CMOS Input

D2#

AGTL I/O

D14#

AGTL I/O

CORE

Power/Other

N33

Reserved

Reserved for future use

N35

Reserved

Reserved for future use

Q33

Reserved

Reserved for future use

CORE

Power/Other

D18#

AGTL I/O

D9#

AGTL I/O

P32

Vss

Power/Other

P34

CORE

Power/Other

P36

Vss

Power/Other

D12#

AGTL I/O

D10#

AGTL I/O

Vss

Power/Other

N37

NCHCTRL

Power/Other

Q35

Reserved

Reserved for future use

Q37

Reserved

Reserved for future use

Reserved

Reserved for future use

D17#

AGTL I/O

REF

Power/Other

R32

CORE

Power/Other

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

R34

Vss

Power/Other

R36

CORE

Power/Other

D8#

AGTL I/O

D5#

AGTL I/O

CORE

Power/Other

S33

Power/Other

S35

RTTCTRL

Power/Other

S37

Power/Other

CORE

Power/Other

D1#

AGTL I/O

D6#

AGTL I/O

T32

Vss

Power/Other

T34

CORE

Power/Other

T36

Vss

Power/Other

D4#

AGTL I/O

D15#

AGTL I/O

Vss

Power/Other

U33

PLL2

Power/Other

U35

Power/Other

U37

Power/Other

Vss

Power/Other

BERR#

AGTL I/O

REF

Power/Other

V32

CORE

Power/Other

V34

Vss

Power/Other

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

V36

CORE

Power/Other

D0#

AGTL I/O

A34#

AGTL I/O

CORE

Power/Other

W33

PLL1

Power/Other

W35

Reserved

Reserved for future use

W37

BCLK

System Bus Clock

Reserved

AGTL I/O

Vss

Power/Other

A32#

AGTL I/O

X32

Vss

Power/Other

X34

Power/Other

X36

Vss

Power/Other

Reserved

Reserved for future use

A26#

AGTL I/O

Vss

Power/Other

Y33

BCLK#/CLKREF

System Bus Clock

Y35

CORE

Power/Other

Y37

Vss

Power/Other

Vss

Power/Other

A29#

AGTL I/O

A18#

AGTL I/O

Z32

CORE

Power/Other

Z34

Vss

Power/Other

Z36

Reserved

Reserved for future use

Table 37. Signal Listing in Order by Pin

Number (Continued)

Pin
No.

Pin Name

Signal Group

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

6.0

Boxed Processor Specifications

The processor for the PGA370 socket is also offered as an Intel boxed processor. Intel boxed
processors are intended for system integrators who build systems from motherboards and standard

components. The boxed processor will be supplied with an unattached fan heatsink.

This section documents motherboard and system requirements for the fan heatsink that will be
supplied with the boxed processor. This section is particularly important for OEMs that
manufacture motherboards for system integrators. Unless otherwise noted, all figures in this

section are dimensioned in inches.

Figure 28

shows a mechanical representation of the boxed Intel

processor in the Flip Chip Pin Grid Array 2 (FC-PGA2) package.

Note: Drawings in this section reflect only the specifications on the Intel Boxed Processor product. These

dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system

designer's responsibility to consider their proprietary solution when designing to the required keep-
out zone on their system platform and chassis. Refer to the Intel

Pentium

III

processor Thermal/

Mechanical Functional Specification for further guidance. Contact your local Intel Sales

Representative for this document.

6.1

Mechanical Specifications

6.1.1

Mechanical Specifications for the FC-PGA2 Package

This section documents the mechanical specifications of the boxed processor fan heatsink in the
FC-PGA2 Package. The boxed processor in the FC-PGA2 Package ships with an un-attached fan

heatsink.

Figure 28

shows a mechanical representation of the boxed processor for the PGA370

socket in the Flip Chip Pin Grid Array 2 (FC-PGA2) package.

The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature,

Figure 31

, must sit over the socket's cam. The step allows the heatsink to securely interface with

the processor in order to meet the processor's thermal requirements.

Figure 28. Conceptual Boxed Processor for the PGA370 Socket

Heatsink Clip

Heatsink

Fan

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

The dimensions for the boxed processor with the integrated fan heatsink are shown in

Figure 30

All dimensions are in inches.

The processor uses a new technology termed FC-PGA2. The FC-PGA2 package leverages the

previous FC-PGA package technology used on processors based on the 0.18 micron process. The
FC-PGA2 package adds an Integrated Heat Spreader (IHS) to improve heat conduction from the
processor die. This new solution prevent the need for exotic thermal solutions in the higher power

density processors. See section 5.0 of this document for the mechanical specifications of the
PGA370 socket.

Section 5.2 of this document also shows the recommended mechanical keepout zones for the boxed
processor fan heatink assembly.

Figure 24

and

Figure 25

show the REQUIRED keepout

dimensions for the boxed processor thermal solution. The cooling fin orientation on the heatsink
relative to the PGA370 socket is subject to change. Contact your local Intel Sales Representative
for documentation specific to the boxed fan heatsink orientation relative to the PGA370 socket.

Figure 31 shows the changes to the package mechanicals between the FC-PGA and FC-PGA2
designs. Note that the boxed fan heatsinks and associated clips are not compatible with earlier

boxed fan heatsinks for processors based on the 0.18 micron process.

Figure 29. Comparison between FC-PGA and FC-PGA2 package

Figure 30. Side View of Space Requirements for the Boxed Processor

3.2 mm

1.9 mm

49.5 mm square

FC-PGA

FC-PGA2

49.5 mm square

3.2 mm

3.5 mm

1.89

3.11

1.76

3.17

1.89

2.65

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

6.1.2

Boxed Processor Heatsink Weight

The boxed processor thermal cooling solution will not weigh more than 180 grams.

6.2

Thermal Specifications

This section describes the cooling requirements of the thermal cooling solution utilized by the
boxed processor.

6.2.1

Boxed Processor Cooling Requirements

The boxed processor is directly cooled with a fan heatsink. However, meeting the processor's
temperature specification is also a function of the thermal design of the entire system and
ultimately the responsibility of the system integrator. The processor temperature specification is

found in

Section 4.1

of this document. The boxed processor fan heatsink is able to keep the

processor temperature within the specifications (see

Table 30

Section 4.1

) in chassis that provide

good thermal management.

For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of

the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and
decreases fan life.

Figure 32

illustrate an acceptable airspace clearance for the fan heatsink. It is

Table 38. Boxed Processor Fan Heatsink Spatial Dimensions

Dimensions (Inches)

Min

Typ

Max

Units

Fan Heatsink Length

3.14

Inches

Fan Heatsink Height

1.81

Inches

Fan Heatsink Width

2.6

Inches

Fan Heatsink height above motherboard

0.29

0.30

0.33

Inches

Air Keepout Zones from end of Fan Heatsink

0.20

Inches

Figure 31. Dimensions of Mechanical Step Feature in Heatsink Base

0.043

0.472

Units = inches

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

also recommended that the air temperature entering the fan be kept below 45 degrees C. Again,
meeting the processor's temperature specification is the responsibility of the system integrator. The

processor temperature specification is found in

Section 4.1

of this document.

6.2.2

Boxed Processor Thermal Cooling Solution Clip

The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.

Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach

tabs in a way that interferes with the installation of the boxed processor thermal cooling solution

Figure 24

and

Figure 25

show the REQUIRED keepout dimensions for the boxed processor

thermal solution.

6.3

Electrical Requirements for the Boxed Processor

6.3.1

Electrical Requirements

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is attached
to the fan and will draw power from a power header on the motherboard. The power cable
connector and pinout are shown in

Figure 33

. Motherboards must provide a matched power header

to support the boxed processor.

Table 38

contains specifications for the input and output signals at

the fan heatsink connector. The fan heatsink outputs a SENSE signal (an open-collector output)
that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH

to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to
GND.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard.

Figure 34

shows the recommended location of the fan

power connector relative to the PGA370 socket. The motherboard power header should be

positioned within 4.00 inches (lateral) of the fan power connector for the FC-PGA2 package.

Figure 32. Thermal Airspace Requirement for all Boxed Processor Fan Heatsinks in the

PGA370 Socket

Measure ambient temperature
0.3 inches above center of fan inlet

Fan Heatsink

0.20 inches

min. air space

Processor PGA-370
Socket

0.20 inches min.
air space

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

7.0

Processor Signal Description

This section provides an alphabetical listing of all the processor signals. The tables at the end of
this section summarize the signals by direction: output, input, and I/O.

7.1

Alphabetical Signals Reference

Table 40. Signal Description (Sheet 1 of 8)

Name

Type

Description

A20M#

If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.

A[35:3]#

I/O

The A[35:3]# (Address) signals define a 2

-byte physical memory address space.

When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
pins to determine their power-on configuration. See the Intel

Pentium

Processor Developer's Manual

for details.

ADS#

I/O

The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.

AERR#

I/O

The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.

AP[1:0]#

I/O

The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are
low and low if an odd number of covered signals are low. This allows parity to be
high when all the covered signals are high. AP[1:0]# should connect the appropriate
pins of all processor system bus agents.

BCLK/BCLK#

The BCLK (Bus Clock) and BCLK# (for differential clock) signals determines the
bus frequency. All processor system bus agents must receive this signal to drive
their outputs and latch their inputs on the rising edge of BCLK. For differential
clocking, all processor system bus agents must receive this signal to drive their
outputs and latch their inputs on the BCLK and BCLK# crossing point.
All external timing parameters are specified with respect to the BCLK signal.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

BERR#

I/O

The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents, and must connect the appropriate pins of all such agents, if used. However,

the processor does not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:

· Enabled or disabled.
· Asserted optionally for internal errors along with IERR#.
· Asserted optionally by the request initiator of a bus transaction after it observes

an error.

· Asserted by any bus agent when it observes an error in a bus transaction.

BINIT#

I/O

The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not
affected.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.

BNR#

I/O

The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.

BP[3:2]#

I/O

The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.

BPM[1:0]#

I/O

The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.

BPRI#

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.

BR0#

I/O

The BR0# (Bus Request) pins drive the BREQ[0]# signal in the system. During
power-up configuration, the central agent asserts the BR0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
its BR0# pin on the active-to-inactive transition of the RESET# to obtain its
symmetric agent ID. The processor asserts the BR0# pin to request the system
bus. BR0# must be connected to a 10-56

resistor to V

. Refer to the platform

design guide for implementation detail and resistor tolerance.

Table 40. Signal Description (Sheet 2 of 8)

Name

Type

Description

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

BSEL[1:0]

The BSEL signals are CMOS signals which are used to select the system bus
frequency. A BSEL[1:0] = `01' selects a 100 MHz system bus frequency. The
frequency is determined by the processor(s), chipset, and frequency synthesizer
capabilities. All system bus agents must operate at the same frequency. The
processor operates at 100 MHz system bus frequency.
These signals must be pulled up to 3.3V power rail with 330

1 K

resistors and

provided as a frequency selection signal to the clock driver/synthesizer and chipset.
Refer to the platform design guide for implementation detail and resistor tolerance.

CLKREF

In Single-ended clock mode the CLKREF input is a filtered 1.25V supply voltage for
the processor PLL. A voltage divider and decoupling solution is provided by the
motherboard. See the design guide for implementation details.
When the processor operates in differential clock mode, this signal becomes
BCLK#.

CPUPRES#

The CPUPRES# signal is defined to allow a system design to detect the presence
of a processor in a PGA370 socket. Combined with the VID combination of
VID[25mV,3:0]= 11111 (see

Section 2.6

), a system can determine if a socket is

occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.

D[63:0]#

I/O

The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.

DBSY#

I/O

The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.

DEFER#

The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.

DEP[7:0]#

I/O

The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.

DETECT

A tri-state (high-impedance) output. Can be used for platforms that need to
differentiate the previous generation Intel Celeron processors for the PGA370
socket that support V

= 1.50 V from the new processors (AF36=VSS) that

support V

= 1.25 V . The output on this signal is stable when V

is stable. Refer

to the appropriate Platform Design Guide for implementation details.

DRDY#

I/O

The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.

Table 40. Signal Description (Sheet 3 of 8)

Name

Type

Description

PGA370 Socket Occupation Truth Table

Signal

Value

Status

CPUPRES#
VID[25mV,3:0]

0
Anything other
than `11111'

Processor core installed in the PGA370
socket.

CPUPRES#
VID[25mV,3:0]

1
Any value

PGA370 socket not occupied.

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

DYN_OE

The DYN_OE allows the BSEL and VID signals to be driven out from the processor.
When this signal is low (a condition that will occur if the processor is installed in a
non-supported platform), the VID and BSEL signals will be tri-stated and the
platform pull-up resistors will set the VID and BSEL to all 1s which is a safe setting.
This signal must be connected to a 1 k

resistor to V

. Refer to the platform

design guide for implementation detail and resistor tolerance.

FERR#

The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.

FLUSH#

When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH#
to determine its power-on configuration. See the P6 Family of Processors
Hardware Developer's Manual

for details.

This signal must be connected to a 150

resistor to V

CCCMOS1.5

. Refer to the

platform design guide for implementation detail and resistor tolerance.

HIT#
HITM#

I/O
I/O

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.

IERR#

The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.

IGNNE#

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.

INIT#

The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).

KEY

Can be used to prevent legacy processors from booting in incompatible platforms.
Legacy processors use this pin as a RESET and should be tied to ground for a 0.13
micron process processor only platform but for flexible platform implementations
this pin should be a No Connect. Please refer to the appropriate Platform Design
Guide for implementation details.

Table 40. Signal Description (Sheet 4 of 8)

Name

Type

Description

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

LINT[1:0]

The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of
all APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Intel

Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.

LOCK#

I/O

The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.

NCHCTRL I

The NCHCTRL input signal provides AGTL pull-down strength control. The
processor samples this input to determine the N-channel device strength for pull-
down when it is the driving agent. This signal must be connected to a 14ohm

resistor to V

. Refer to the platform design guide for implementation detail and

resistor tolerance.

PICCLK

The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.

PICD[1:0]

I/O

The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.

PLL1, PLL2

The processor has an internal analog PLL clock generator that requires a quiet
power supply. PLL1 and PLL2 are inputs to this PLL and must be connected to
V

CORE

through a low pass filter that minimizes jitter. See the platform design

guide for implementation details.

PRDY#

The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.

PREQ#

The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.

PWRGOOD

The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (V

CORE

etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in

Table 18

, and be followed by a 1 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.

REQ[4:0]#

I/O

The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.

Table 40. Signal Description (Sheet 5 of 8)

Name

Type

Description

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

RESET#

Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after V

CORE

and

CLK have reached their proper specifications. On observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer's Manual

for details.

The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the power on Reset vector
(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all
processor system bus agents.
RESET# is the only AGTL signal which does not have on-die termination.
Therefore, it is necessary to place a discrete 56

resistor to V

. Refer to the

platform design guide for implementation detail and resistor tolerance.

RESET2#

RESET2# pin is provided to differentiate the processor from the previous
generation Intel

Celeron processor. The 0.13 micron process based processor

does not use the RESET2# pin. Refer to the platform design guide for the proper
connections of this signal.

RP#

I/O

The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.

RS[2:0]#

I/O

The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.

RSP#

The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.

RTTCTRL

The RTTCTRL input signal provides AGTL termination control. The processor
samples this input to set the termination resistance value for the on-die AGTL
termination. This signal must be connected to a 56

resistor to V

on a uni-

processor platform or a 68

resistor to V

on a dual-processor platform. Refer to

the platform design guide for implementation detail and resistor tolerance.

SLEWCTRL

The SLEWCTRL input signal provides AGTL slew rate control. The processor
samples this input to determine the slew rate for AGTL signals when it is the driving
agent. This signal must be connected to a 110

resistor to V

. Refer to the

platform design guide for implementation detail and resistor tolerance.

SLP#

The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.

Table 40. Signal Description (Sheet 6 of 8)

Name

Type

Description

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

SMI#

The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.

STPCLK#

The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power state. The processor stops providing internal clock signals to all
processor core units except the bus and APIC units. The processor continues to
snoop bus transactions and latch interrupts. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts, and
resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.

TCK

The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).

TDI

The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.

TDO

The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.

THERMDN

Thermal Diode Cathode. This signal is used to calculate core (junction)
temperature. See

Section 4.1

THERMDP

Thermal Diode Anode. This signal is used to calculate core (junction) temperature.
See

Section 4.1

THERMTRIP#

The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active or core power is
removed. There is no hysteresis built into the thermal sensor itself; as long as the
die temperature drops below the trip level, a RESET# pulse will reset the processor
and execution will continue. If the temperature has not dropped below the trip level,
the processor will continue to drive THERMTRIP# and remain stopped.
In the event the processor drives the THERMTRIP# signal active during valid
operation, both the V

and V

supplies to the processor must be turned off to

prevent thermal runaway of the processor. Valid operation refers to the operating
conditions where the THERMTRIP# signal is guaranteed valid. The time required
from THERMTRIP# asserted to V

rail at 1/2 nominal is 5 seconds and

THERMTRIP# asserted to V

rail at 1/2 nominal is 5 seconds. Once Vcc and V

supplies are turned off the THERMTRIP# signal will be deactivated. System logic
should ensure no "unsafe" power cycling occurs due to this deassertion.

TMS

The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.

TRDY#

I/O

The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.

TRST#

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.

CMOS_REF

The V

CMOS_REF

input pin supplies non-AGTL reference voltage, which is typically

2/3 of V

CMOS

. V

CMOS_REF

is used by the non-AGTL receivers to determine if a

signal is a logical 0 or a logical 1.
The Thevenin equivalent impedance of the V

CMOS_REF

generation circuits must be

less than 0.5 k

/1 k

(i.e., top resistor 500

, bottom resistor 1 k

Table 40. Signal Description (Sheet 7 of 8)

Name

Type

Description

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

7.2

Signal Summaries

Table 41

through

Table 44

list attributes of the processor output, input, and I/O signals.

VID [3:0,25mV]

The VID[3:0, 25 mV] (Voltage ID) pins can be used to support automatic selection
of power supply voltages. These pins are CMOS signals that must be pulled up to
3.3 V power rail with 1 K

resistors. The VID pins are needed to cleanly support

voltage specification variations on processors. See

Table 3

for definitions of these

pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.

REF

The V

REF

input pins supply the AGTL reference voltage, which is typically 2/3 of

. V

REF

is used by the AGTL receivers to determine if a signal is a logical 0 or a

logical 1.

VTT_PWRGD

The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their
correct logic state. During Power-up, the VID signals will be in an indeterminate
state for a small period of time. The voltage regulator or the VRM should not sample
and/or latch the VID signals until the VTT_PWRGD signal is asserted. The
assertion of the VTT_PWRGD signal indicates the VID signals are stable and are
driven to the final state by the processor. Refer to

Figure 6

for power-up timing

sequence for the VTT_PWRGD and the VID signals

Table 40. Signal Description (Sheet 8 of 8)

Name

Type

Description

Table 41. Output Signals

Name

Active Level

Clock

Signal Group

BSEL[1:0]

High

Asynch

Power/Other

CPUPRES#

Low

Asynch

Power/Other

DETECT

High

Asynch

Power/Other

FERR#

Low

Asynch

CMOS Output

IERR#

Low

Asynch

CMOS Output

PRDY#

Low

BCLK

AGTL Output

TDO

High

TCK

TAP Output

THERMTRIP#

Low

Asynch

CMOS Output

VID[3:0, 25mV]

N/A

Asynch

Power/Other

Table 42. Input Signals (Sheet 1 of 2)

Name

Active Level

Clock

Signal Group

Qualified

A20M#

Low

Asynch

CMOS Input

Always

BCLK

High

System Bus Clock

Always

BPRI#

Low

BCLK

AGTL Input

Always

DEFER#

Low

BCLK

AGTL Input

Always

FLUSH#

Low

Asynch

CMOS Input

Always

IGNNE#

Low

Asynch

CMOS Input

Always

INIT#

Low

Asynch

CMOS Input

Always

INTR

High

Asynch

CMOS Input

APIC disabled mode

KEY

N/A

Asynch

Power/Other

Datasheet

Intel

Celeron

Processor for PGA370 up to 1.40 GHz on 0.13

Process

NOTE:

Synchronous assertion with active TDRY# ensures synchronization.

LINT[1:0]

High

Asynch

CMOS Input

APIC enabled mode

NMI

High

Asynch

CMOS Input

APIC disabled mode

NCHCTRL

N/A

Asynch

Power/Other

PICCLK

High

APIC Clock

Always

PREQ#

Low

Asynch

CMOS Input

Always

PWRGOOD

High

Asynch

CMOS Input

Always

RESET#

Low

BCLK

AGTL Input

Always

RESET2#

Low

BCLK

AGTL Input

RSP#

Low

BCLK

AGTL Input

Always

RTTCTRL

N/A

Asynch

Power/Other

SLEWCTRL

N/A

Asynch

Power/Other

SLP#

Low

Asynch

CMOS Input

During Stop-Grant state

SMI#

Low

Asynch

CMOS Input

STPCLK#

Low

Asynch

CMOS Input

TCK

High

TAP Input

TDI

High

TCK

TAP Input

TMS

High

TCK

TAP Input

TRST#

Low

Asynch

TAP Input

VTT_PWRGD

High

Asynch

Power/Other

Table 42. Input Signals (Sheet 2 of 2)

Name

Active Level

Clock

Signal Group

Qualified

Table 43. Input/Output Signals (Single Driver)

Name

Active Level

Clock

Signal Group

Qualified

A[35:3]#

Low

BCLK

AGTL I/O

ADS#, ADS#+1

ADS#

Low

BCLK

AGTL I/O

Always

AP[1:0]#

Low

BCLK

AGTL I/O

ADS#, ADS#+1

BP[3:2]#

Low

BCLK

AGTL I/O

Always

BPM[1:0]#

Low

BCLK

AGTL I/O

Always

BR0#

Low

BCLK

AGTL I/O

Always

D[63:0]#

Low

BCLK

AGTL I/O

DRDY#

DBSY#

Low

BCLK

AGTL I/O

Always

DEP[7:0]#

Low

BCLK

AGTL I/O

DRDY#

Low

BCLK

AGTL I/O

Always

LOCK#

Low

BCLK

AGTL I/O

Always

REQ[4:0]#

Low

BCLK

AGTL I/O

ADS#, ADS#+1

RP#

Low

BCLK

AGTL I/O

ADS#, ADS#+1

RS[2:0]#

Low

BCLK

AGTL Input

Always

TRDY#

Low

BCLK

AGTL Input

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IntelCeleron1.20GHz

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IntelCeleron1.20GHz