Document Outline

• Contents
  • 1.0 Introduction 1
  • 2.0 Electrical Specifications 5
  • 3.0 Signal Quality Specifications 37
  • 4.0 Thermal Specifications and Design Considerations 47
  • 5.0 Mechanical Specifications 49
  • 6.0 Boxed Processor Specifications 70
  • 7.0 Processor Signal Description 76
  • List of Figures
  • List of Tables
    • Information in this document is provided in connection with Intel products. No license, express o...
    • Intel may make changes to specifications and product descriptions at any time, without notice.
    • Designers must not rely on the absence or characteristics of any features or instructions marked ...
    • The Pentium� III Processor with 512KB L2 Cache may contain design defects or errors known as erra...
    • Contact your local Intel sales office or your distributor to obtain the latest specifications and...
    • Copies of documents which have an ordering number and are referenced in this document, or other I...
    • All rights reserved. Intel, the Intel Logo and Pentium are trademarks or registered trademarks of...
    • Copyright � Intel Corporation, 2002
    • * Other names and brands may be claimed as the property of others.
• Intel� Pentium� III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
  • Datasheet
  • Product Features
    • Available at 1.13, 1.26 and 1.40GHz
    • 512KB Advanced Transfer Cache (on-die, full speed Level 2 (L2) cache with Error Correcting Code (...
    • Dual Independent Bus (DIB) architecture: Separate dedicated external System Bus and dedicated int...
    • Internet Streaming SIMD Extensions for enhanced video, sound and 3D performance
    • Binary compatible with applications running on previous members of the Intel microprocessor line
    • Dynamic execution micro architecture
    • Power Management capabilities
      • � System Management mode
      • � Multiple low-power states
    • Optimized for 32-bit applications running on advanced 32-bit operating systems
    • Flip Chip Pin Grid Array (FC-PGA2) packaging technology; FC-PGA2 processors deliver high performa...
    • Integrated high performance 16KB instruction and 16KB data, nonblocking, level one cache
    • 512KB Integrated Full Speed level two cache allows for low latency on read/store operations
    • Quad Quadword Wide (256 bit) cache data bus provides extremely high throughput on read/ store ope...
    • 8-way cache associativity provides improved cache hit rate on reads/store operations.
    • Error-correcting code for System Bus data
    • Data Prefetch Logic
  • The Pentium� III processor with 512KB L2 Cache is designed for high-performance workstations and ...
  • FC-PGA2 370 Package
  • 1.0 Introduction
    • Figure 1. Integrated Heat Spreader (IHS)
    • 1.1 Terminology
      • 1.1.1 Package and Processor Terminology
      • 1.1.2 Processor Naming Convention
        • Table 1. Processor Identification
          • 1.13
          • 1.13
          • 133
          • 512
          • ATC
          • 06Bxh
          • 1.26
          • 1.26
          • 133
          • 512
          • ATC
          • 06Bxh
          • 1.40
          • 1.40
          • 133
          • 512
          • ATC
          • 06Bxh
            • 1. Refer to the Pentium III Processor Specification Update for the exact CPUID for each processor.
            • 2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor ...
    • 1.2 Related Documents
      • 241618
      • 243334
      • 243193
      • 243190
      • 243191
      • 243192
      • 244001
      • 243565
      • 244410
      • 245025
      • 249659
      • 249658
      • 249660
        • 1. Unless otherwise noted, this reference material can be found on the Intel Developer�s Website ...
        • 2. For a complete listing of Intel� Pentium� III processor reference material, please refer to th...
    • 1.3 Revision History
      • 1.0
      • June 2001
      • 1.5
      • January 2002
      • 2.0
      • June 2002
  • 2.0 Electrical Specifications
    • 2.1 Processor System Bus and VREF
      • Note: The RESET# signal requires a discrete external termination resistor on the system board.
      • Note: The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL si...
        • Figure 2. AGTL Bus Topology
      • Note: Please refer to the appropriate design guide for platform specific termination.
    • 2.2 Clock Control and Low Power States
      • Figure 3. Stop Clock State Machine
      • 2.2.1 Normal State�State 1
      • 2.2.2 AutoHALT Powerdown State�State 2
      • 2.2.3 Stop-Grant State�State 3
      • 2.2.4 HALT/Grant Snoop State�State 4
      • 2.2.5 Sleep State�State 5
      • 2.2.6 Deep Sleep State�State 6
        • Table 2. System Bus Clock in Deep Sleep Mode (Differential Mode only)1
          • 1. The values in this table are based on differential probe measurement of the Bclk.
          • 2. The DC voltage level specified must be maintained when the system bus clock is not active, e.g...
      • 2.2.7 Clock Control
    • 2.3 Power and Ground Pins
      • 2.3.1 Phase Lock Loop (PLL) Power
        • Figure 4. PLL Filter Specification
    • 2.4 Decoupling Guidelines
      • 2.4.1 Processor VCCCORE Decoupling
    • 2.5 Processor System Bus Clock and Processor Clocking
      • Figure 5. Differential/Single-Ended Clocking Example
    • 2.6 Voltage Identification
      • Table 3. Voltage Identification Definition 1
        • 0
        • 0
        • 1
        • 0
        • 0
        • 1.05
        • 1
        • 0
        • 1
        • 0
        • 0
        • 1.075
        • 0
        • 0
        • 0
        • 1
        • 1
        • 1.10
        • 1
        • 0
        • 0
        • 1
        • 1
        • 1.125
        • 0
        • 0
        • 0
        • 1
        • 0
        • 1.15
        • 1
        • 0
        • 0
        • 1
        • 0
        • 1.175
        • 0
        • 0
        • 0
        • 0
        • 1
        • 1.20
        • 1
        • 0
        • 0
        • 0
        • 1
        • 1.225
        • 0
        • 0
        • 0
        • 0
        • 0
        • 1.25
        • 1
        • 0
        • 0
        • 0
        • 0
        • 1.275
        • 0
        • 1
        • 1
        • 1
        • 1
        • 1.30
        • 1
        • 1
        • 1
        • 1
        • 1
        • 1.3252
        • 0
        • 1
        • 1
        • 1
        • 0
        • 1.35
        • 1
        • 1
        • 1
        • 1
        • 0
        • 1.375
        • 0
        • 1
        • 1
        • 0
        • 1
        • 1.40
        • 1
        • 1
        • 1
        • 0
        • 1
        • 1.425
        • 0
        • 1
        • 1
        • 0
        • 0
        • 1.45
        • 1
        • 1
        • 1
        • 0
        • 0
        • 1.475
        • 0
        • 1
        • 0
        • 1
        • 1
        • 1.50
        • 1
        • 1
        • 0
        • 1
        • 1
        • 1.525
        • 0
        • 1
        • 0
        • 1
        • 0
        • 1.55
        • 1
        • 1
        • 0
        • 1
        • 0
        • 1.575
        • 0
        • 1
        • 0
        • 0
        • 1
        • 1.60
        • 1
        • 1
        • 0
        • 0
        • 1
        • 1.625
        • 0
        • 1
        • 0
        • 0
        • 0
        • 1.65
        • 1
        • 1
        • 0
        • 0
        • 0
        • 1.675
        • 0
        • 0
        • 1
        • 1
        • 1
        • 1.70
        • 1
        • 0
        • 1
        • 1
        • 1
        • 1.725
        • 0
        • 0
        • 1
        • 1
        • 0
        • 1.75
        • 1
        • 0
        • 1
        • 1
        • 0
        • 1.775
        • 0
        • 0
        • 1
        • 0
        • 1
        • 1.80
        • 1
        • 0
        • 1
        • 0
        • 1
        • 1.825
          • 1. 0 = Processor pin connected to vss. and 1 = Open on processor; may be pulled up to TTL VIH (3....
          • 2. VID[25mV, 3:0] = �11111� can be used as a �No Core� setting for Pentium� III processor with 51...
      • Figure 6. VTT Power Good and Bus Select Interconnect Diagram
    • 2.7 Processor System Bus Unused Pins
    • 2.8 Processor System Bus Signal Groups
      • Table 4. System Bus Signal Groups 1
        • 1. See Section 7.0 for information on the these signals.
        • 2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more informat...
        • 3. This signal is 1.25V.
        • 4. These signals are 1.5V.
        • 5. This signal is 1.8V.
        • 6. VccCORE is the power supply for the processor core and is described in Section 2.6. VID[3:0,25...
        • 7. This signal is used to control the value of the processor on-die termination resistance. Refer...
        • 8. These signals are 3.3V.
        • 9. These signals are 2.0V.
        • 10. 1.25V signal for Differential clock application and 2.5V for Single-ended clock application.
      • 2.8.1 Asynchronous vs. Synchronous for System Bus Signals
      • 2.8.2 System Bus Frequency Select Signals
        • Figure 7. BSEL[1:0] Example for a System Design
    • 2.9 Maximum Ratings
      • Table 5. Frequency Select Truth Table for BSEL[1:0]
        • 0
        • 0
        • Reserved
        • 0
        • 1
        • Reserved
        • 1
        • 0
        • Reserved
        • 1
        • 1
        • 133MHz
      • Table 6. Absolute Maximum Ratings
        • -40
        • 85
        • C
        • 0.5
        • 1.75
        • V
        • -0.3
        • 1.78
        • V
        • -0.3
        • 2.08
        • V
        • -0.3
        • 3.6
        • V
          • 1. Input voltage can never exceed vss +1.78 volts.
          • 2. Input voltage can never exceed vss + 2.08 volts.
          • 3. Input voltage can never go below -0.3V
          • 4. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
    • 2.10 Processor Voltage Level Specifications
      • 1.13GHz
      • 1.26GHz
      • 1.40GHz
      • 1.45
      • 1.45
      • 1.45
      • V
      • V
      • V
      • 1.25
      • V
      • 1.25
      • V
      • 1.5
      • V
      • 1.8
      • V
      • Please refer to Figure 8 and Table 8 for Tolerance values
      • V
      • V
      • 1.13 GHz
      • 06B0
      • 06B1
      • 19.4
      • A
      • 06B4
      • 19.9
      • A
      • 1.26 GHz
      • 06B0
      • 06B1
      • 20.5
      • A
      • 06B4
      • 21.2
      • A
      • 1.40 GHz
      • 06B0
      • 06B1
      • 21.8
      • A
      • 06B4
      • 22.4
      • A
      • 250
      • mA
      • 1
      • mA
      • 35
      • mA
      • 2.3
      • A
      • 1.13GHz
      • 1.26GHz
      • 1.40GHz
      • 13.2
      • 14.0
      • 14.8
      • A
      • A
      • A
      • 10.2
      • A
      • Please refer to Table 7 for Slew Rate
      • A/ �s
      • Table 12
      • A/ �s
        • 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
        • 2. All specifications in this table apply only to the Intel� Pentium� III processor with 512KB L2...
        • 3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.
        • 4. Vtt must be held to 1.25V �9% while the AGTL bus is active. It is required that Vtt be held to...
        • 5. These are the tolerance requirements, across a 20MHz frequency bandwidth, measured at the pro...
        • 6. Maximum Icc is measured at Vcc typical voltage and under a maximum signal loading conditions.
        • 7. The current specified is also for AutoHALT state.
        • 8. Maximum values are specified by design/characterization at nominal VccCORE.
        • 9. Based on simulation and averaged over the duration of any change in current. Use to compute th...
        • 10. dIcc/dt specifications are measured and specified at the PGA370 socket pins.
        • 11. Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple...
        • 12. Pull ups only.
      • Table 7. Power Supply Current Slew Rate (dIcccore/dt)
      • Table 8. Vcc Static & Transient Tolerance
        • 0
        • 25
        • 65
        • 0
        • 90
        • 2
        • 19
        • 59
        • -6
        • 84
        • 4
        • 12
        • 52
        • -13
        • 77
        • 6
        • 6
        • 46
        • -19
        • 71
        • 8
        • -1
        • 39
        • -26
        • 64
        • 10
        • -7
        • 33
        • -32
        • 58
        • 12
        • -14
        • 26
        • -39
        • 51
        • 14
        • -20
        • 20
        • -45
        • 45
        • 16
        • -26
        • 14
        • -51
        • 39
        • 18
        • -33
        • 7
        • -58
        • 32
        • 20
        • -39
        • 1
        • -64
        • 26
        • 22
        • -46
        • -6
        • -71
        • 19
        • 24
        • -52
        • -12
        • -77
        • 13
        • 26
        • -59
        • -19
        • -84
        • 6
        • 28
        • -65
        • -25
        • -90
        • 0
      • Figure 8. Vcc Static & Transient Tolerance
      • Table 9. AGTL Signal Group Levels Specifications 1
        • VREF - 0.200
        • V
        • VREF + 0.200
        • V
        • 16.67
        • W
        • �100
        • �A
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. All inputs, outputs, and I/O pins must comply with the signal quality specifications in Sectio...
          • 3. Minimum and maximum Vtt are given in Table 12 on page24.
          • 4. (0 � Vin � 1.25V +3%) and (0�Vout�1.25V+3%).
          • 5. Refer to the processor I/O Buffer Models for I/V characteristics.
          • 6. Steady state input voltage must not be above vss + 1.65V or below Vtt - 1.65V.
          • 7. Does not apply to Vcc leakage current due to the presence of on die RTT.
      • Table 10. Non-AGTL Signal Group Levels Specifications 1
        • 0.4
        • V
        • �0.150
        • Vcmos_ref - 0.300
        • V
        • -0.36
        • 0.36
        • V
        • -0.40
        • 0.40
        • V
        • 1.08
        • V
        • Vcmos_ref + 0.250
        • VCC_CMOS1.5 + 10%
        • V
        • Vcmos_ref + 0.200
        • 2.0
        • V
        • 1.44
        • 2.16
        • V
        • 1.60
        • V
        • 30
        • W
        • 0.30
        • V
        • 10
        • mA
        • �100
        • �A
        • �100
        • �A
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. Parameter measured at 9 mA (for use with TTL inputs).
          • 3. (0 � Vin � 1.8V +10%).
          • 4. (0 � Vout � 1.8V +10%).
          • 5. For BCLK specifications, refer to Table 22 on page37.
          • 6. (0 � Vin � 1.5V +10%).
          • 7. (0 � Vout � 1.5V +10%).
          • 8. Applies to non-AGTL signal PWRGOOD.
          • 9. Applies to non-AGTL signal PICCLK.
          • 10. Applies to non-AGTL signals except BCLK, PICCLK, and PWRGOOD.
          • 11. Applies to non-AGTL signal VTT_PWRGD.
          • 12. Vcmos_ref = 2/3 Vcc_cmos1.5, refer to Table 7 on page27.
          • 13. Applies to PICD[1:0].
      • Table 11. 3.3 Volt CMOS Output Signal Group DC Specifications
        • 3.45
        • V
        • 3.3 + 5%
        • 0.9
        • V
        • 100
        • �A
    • 2.11 AGTL System Bus Specifications
      • Table 12. Processor AGTL Bus Specifications 1, 2
        • 1.1375
        • 1.25
        • V
        • 50
        • 56
        • 68
        • 115
        • W
        • 2/3VTT
        • V
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. Intel� Pentium� III processors with 512KB L2 cache for the PGA370 socket contain AGTL terminat...
          • 3. Vtt must be held to 1.25V �9%. It is required that Vtt be held to 1.25V �3% while the processo...
          • 4. Uni-processor platforms require a 56W resistor and dual-processor platforms require a 68W resi...
          • 5. VREF is generated on the motherboard and should be 2/3 Vtt �5% nominally. Ensure that there is...
    • 2.12 System Bus Timing Specifications
    • 7
      • Table 13. System Bus Timing Specifications (Single-Ended Clock)1,4
        • 7.5
        • 7.65
        • 10.0
        • 10.15
        • nS
        • 9
        • 7.25
        • 9.75
        • nS
        • 250
        • 250
        • pS
        • 0.4
        • 1.6
        • 0.4
        • 1.6
        • nS
        • 10
        • 0.4
        • 1.6
        • 0.4
        • 1.6
        • nS
        • 10
        • 1.4
        • 2.5
        • nS
        • 10
        • 1.4
        • 2.4
        • nS
        • 10
        • 2.2
        • 2.2
        • V
        • 0.3
        • 0.3
        • V
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. Period, jitter, offset and skew measured at 1.25V.
          • 3. Measured from 0.5 to 2.0V.
          • 4. CLKREF (BCLK#) = 1.25V with +/- 5% DC tolerance. CLKREF must be generated from a stable source...
          • 5. BCLK High Time is measured above 2.0V.
          • 6. BCLK Low Time is measured below 0.5V.
      • Table 14. System Bus Timing Specifications (Differential Clock)1, 2, 6
        • 7.5
        • 7.7
        • 10.0
        • 10.2
        • nS
        • 9
        • 7.30
        • 9.8
        • nS
        • 200
        • 200
        • pS
        • 0.51
        • 0.76
        • 0.51
        • 0.76
        • V
        • 9
        • 175
        • 550
        • 175
        • 550
        • pS
        • 10
        • 175
        • 550
        • 175
        • 550
        • pS
        • 10
        • 325
        • 325
        • pS
        • 45%
        • 55%
        • 45%
        • 55%
        • 0.92
        • 1.45
        • 0.92
        • 1.45
        • V
        • -0.2
        • 0.35
        • -0.2
        • 0.35
        • V
        • 0.35
        • 0.35
        • V
        • -0.35
        • -0.35
        • V
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. All timings for the AGTL signals are referenced at the rising edge of BCLK and the falling edg...
          • 3. The internal core clock frequency is derived from the processor system bus clock. The system b...
          • 4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that...
          • 5. The clock driver�s closed loop jitter bandwidth must be set low to allow any PLL-based device ...
          • 6. Measurement taken from differential waveform, defined as BCLK - BCLK#.
          • 7. Rise time is measured from -0.35 to +0.35V and fall time is measured from 0.35V to -0.35V.
          • 8. Measured at the socket pin.
      • Table 15. System Bus Timing Specifications (AGTL Signal Group)1, 2, 3
        • 0.40
        • 3.25
        • ns
        • 11
        • 0.95
        • ns
        • 12
        • 1.00
        • ns
        • 12
        • 1.00
        • ms
        • 13
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. These specifications are tested during manufacturing.
          • 3. All timings for the AGTL signals are referenced to the rising edge of BCLK and the falling edg...
          • 4. Valid delay timings for these signals are specified into 50W to 1.25V, VREF at 0.8V �2% and ...
          • 5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
          • 6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
          • 7. Specification is for a minimum 0.40V swing from VREF - 200mV to VREF + 200mV. This assumes ...
          • 8. Specification is for a maximum 0.8V swing from Vtt - 0.8V to Vtt. This assumes an edge rate o...
          • 9. This should be measured after VccCORE, Vtt, VccCMOS, and BCLK (and BCLK#) are stable
          • 10. BREQ signals observe a 1.2nS minimum setup time.
      • Table 16. System Bus Timing Specifications (CMOS Signal Group) 1, 2, 3, 4
        • 2
        • BCLKs
        • 11
        • 10
        • BCLKs
        • 15
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. These specifications are tested during manufacturing.
          • 3. These signals may be driven asynchronously.
          • 4. All CMOS outputs shall be asserted for at least 2 system bus clocks.
          • 5. When driven inactive or after VccCORE, Vtt, VccCMOS, and BCLK and BCLK# are stable.
      • Table 17. System Bus Timing Specifications (Reset Conditions) 1
        • 4
        • BCLKs
        • 13
        • 2
        • 20
        • BCLKs
        • 13
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
      • Table 18. System Bus Timing Specifications (APIC Clock and APIC I/O)1, 2, 3
        • 2.0
        • 33.3
        • MHz
        • 30.0
        • 500.0
        • ns
        • 10
        • 10.5
        • ns
        • 10
        • 10.5
        • ns
        • 10
        • 0.25
        • 3.0
        • ns
        • 10
        • 0.25
        • 3.0
        • ns
        • 10
        • 8.0
        • ns
        • 12
        • 2.5
        • ns
        • 12
        • 1.5
        • 8.7
        • ns
        • 11
        • 1.5
        • 12.0
        • ns
        • 10
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. These specifications are tested during manufacturing.
          • 3. All timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.9V at the ...
          • 4. Referenced to PICCLK rising edge.
          • 5. For open drain signals, valid delay is synonymous with float delay.
          • 6. Valid delay timings for these signals are specified into 150W load pulled up to 1.5V.
      • Table 19. System Bus Timing Specifications (TAP Connection)1, 2, 3
        • 16.667
        • MHz
        • 60.0
        • ns
        • 10
        • 25.0
        • ns
        • 10
        • 25.0
        • ns
        • 10
        • 5.0
        • ns
        • 10
        • 5.0
        • ns
        • 10
        • 40.0
        • ns
        • 17
        • 5.0
        • ns
        • 16
        • 14.0
        • ns
        • 16
        • 1.0
        • 10.0
        • ns
        • 16
        • 25.0
        • ns
        • 16
        • 2.0
        • 25.0
        • ns
        • 16
        • 25.0
        • ns
        • 16
        • 5.0
        • ns
        • 16
        • 13.0
        • ns
        • 16
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. All timings for the TAP signals are referenced to the TCK rising edge at 1.0V at the processo...
          • 3. These specifications are tested during manufacturing, unless otherwise noted.
          • 4. 1 ns can be added to the maximum TCK rise and fall times for every 1MHz below 16.667MHz.
          • 5. Referenced to TCK rising edge.
          • 6. Referenced to TCK falling edge.
          • 7. Valid delay timing for this signal is specified to 1.5V.
          • 8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, T...
          • 9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
          • 10. Not 100% tested. Specified by design characterization.
      • Table 20. Platform Power-On Timings2
        • 1.0
        • mS
        • 14
        • 2.0
        • mS
        • 14
        • 1
        • BCLK
        • 14
        • 4
        • BCLK
        • 14
          • 1. All signals, during their invalid states, must be guarded against spurious levels from effecti...
          • 2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, ...
      • Notes: For Figure 9 through Figure 19, the following apply:
        • 1. Figure 9 through Figure 19 are to be used in conjunction with Table 13 through Table 19.
        • 2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of BC...
        • 3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising...
        • 4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at...
        • Figure 9. Clock Waveform
        • Figure 10. BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform
        • Figure 11. System Bus Valid Delay Timings
        • Figure 12. System Bus Setup and Hold Timings
        • Figure 13. System Bus Reset and Configuration Timings
        • Figure 14. Platform Power-On Sequence and Timings
        • Figure 15. Power-On Reset and Configuration Timings
        • Figure 16. Test Timings (TAP Connection)
        • Figure 17. Test Reset Timings
  • 3.0 Signal Quality Specifications
    • 3.1 BCLK/BCLK# & PICCLK Signal Quality Specifications and Measurement Guidelines
      • Table 21. BCLK (Single-Ended Clock Mode) Signal Quality Specifications for Simulation at the Proc...
        • 0.3
        • V
        • 18
        • 2.2
        • V
        • 18
        • -0.5
        • 3.1
        • V
        • 18
        • 2.0
        • V
        • 18
        • 0.5
        • V
        • 18
      • Table 22. BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality Specifications for Simul...
        • -0.2
        • 0.35
        • V
        • 18
        • 0.40
        • V
        • 18
        • 0.92
        • 1.45
        • V
        • 18
        • 1.60
        • V
        • 18
        • -0.2
        • 1.45
        • V
        • 18
        • -0.4
        • 2.4
        • V
        • 18
        • 0.35
        • V
        • 18
        • 1.60
        • V
        • 18
        • -0.35
        • V
        • 18
        • 0.40
        • V
        • 18
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (fal...
      • Figure 18. BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins
    • 3.2 AGTL Signal Quality Specifications and Measurement Guidelines
      • Table 23. AGTL Signal Groups Ringback Tolerance Specifications at the Processor Pins 1, 2, 3
        • 100
        • mV
        • 19
        • 0.50
        • ns
        • 19
        • �200
        • mV
        • 19
        • 200
        • mV
        • 19
        • N/A
        • ns
        • 19
          • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
          • 2. Specifications are for the edge rate of 0.3 - 3V/ns. See Figure 19 for the generic waveform.
          • 3. All values specified by design characterization.
          • 4. Please see Table 22 for maximum allowable overshoot.
          • 5. Ringback between VREF + 100mV and VREF + 200 mV or VREF - 300mV and VREF - 100 mVs requires ...
          • 6. Intel recommends simulations not exceed a ringback value of VREF �200mV to allow margin for o...
          • 7. A negative value for r indicates that the amplitude of ringback is above VREF. (i.e., f = -100...
          • 8. f and r: are measured relative to VREF. a: is measured relative to VREF + 200 mV.
      • Figure 19. Low to High AGTL Receiver Ringback Tolerance
    • 3.3 AGTL Signal Quality Specifications and Measurement Guidelines
      • 3.3.1 Overshoot/Undershoot Guidelines
      • 3.3.2 Overshoot/Undershoot Magnitude
        • Note: The converted undershoot waveform appears as a positive (overshoot) signal.
        • Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their imp...
      • 3.3.3 Overshoot/Undershoot Pulse Duration
        • Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/und...
        • Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be consider...
      • 3.3.4 Activity Factor
        • Note: Activity factor for AGTL signals is referenced to system bus clock frequency.
        • Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
      • 3.3.5 Reading Overshoot/Undershoot Specification Tables
        • 1. Determine the signal group that particular signal falls into. If the signal is an AGTL signal ...
        • 2. Determine the maximum case temperature (Tcase) for the range of processors that the system wil...
        • 3. Determine the Magnitude of the overshoot (relative to Vss)
        • 4. Determine the Activity Factor (how often this overshoot occurs?)
        • 5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns) allowed.
        • 6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse Durati...
        • Table 24. Example Platform Information
          • 133MHz AGTL
          • 69 C
          • 1.78 V
          • 0.1
      • 3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications
        • 1. Ensure no AGTL signal ever exceeds 1.78V and no CMOS signal ever exceeds 2.08V. OR
        • 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot s...
        • 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duratio...
          • 1. Overshoot/Undershoot Magnitude = 1.78V(AGTL), 2.08V(CMOS) is an absolute value and should neve...
          • 2. Overshoot is measured relative to vss.
          • 3. Undershoot is measured relative to Vtt
          • 4. Overshoot/Undershoot Pulse Duration is measured relative to 1.32V for AGTL and 1.80V for CMOS.
          • 5. Rinbacks below Vtt can not be subtracted from Overshoots/Undershoots
          • 6. Lesser Undershoot does not allocate longer or larger Overshoot
          • 7. OEM's are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines...
          • 8. All values specified by design characterization
        • Table 25. 133 MHz AGTL Signal Group Overshoot/Undershoot Tolerance 1, 2, 3
          • 1.78
          • 15
          • 1.5
          • 0.153
          • 8.7
          • 0.87
          • 0.087
          • 1.73
          • 15
          • 3.1
          • 0.31
          • 15
          • 2.0
          • 0.20
          • 1.68
          • 15
          • 6.8
          • 0.68
          • 15
          • 4.6
          • 0.46
          • 1.63
          • 15
          • 14
          • 1.42
          • 15
          • 10
          • 1.0
          • 1.58
          • 15
          • 15
          • 2.95
          • 15
          • 15
          • 2.3
          • 1.53
          • 15
          • 15
          • 6.2
          • 15
          • 15
          • 5.0
          • 1.48
          • 15
          • 15
          • 13.2
          • 15
          • 15
          • 15
        • Notes: 1. Measurements taken at the processor socket pins on the solder-side of the motherboard. ...
          • Figure 20. Maximum Acceptable AGTL Overshoot/Undershoot Waveform
    • 3.4 Non-AGTL Signal Quality Specifications and Measurement Guidelines
      • Figure 21. Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback 1
        • 1. VHI = 1.80 V for all non-AGTL signals except for BCLK, PICCLK, and PWRGOOD. VHI =2.0 V for PIC...
      • 3.4.1 Overshoot/Undershoot Guidelines
        • Table 26. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance
          • 2.38
          • 35
          • 3.5
          • 0.35
          • 2.33
          • 60
          • 8.0
          • 0.8
          • 2.28
          • 60
          • 18
          • 1.8
          • 2.23
          • 60
          • 41
          • 4.1
          • 2.18
          • 60
          • 60
          • 9.0
          • 2.13
          • 60
          • 60
          • 21
          • 2.08
          • 60
          • 60
          • 60
        • Note: The undershoot guideline limits transitions exactly as described for the AGTL signals. See ...
      • 3.4.2 Ringback Specification
        • Table 27. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor Pins 1
          • 0 � 1
          • Vcmos_ref + 0.200
          • V
          • 21
          • 1 � 0
          • Vcmos_ref - 0.300
          • V
          • 21
          • 0 � 1
          • 1.44
          • V
          • 21
            • 1. Unless otherwise noted, all specifications in this table apply to Intel� Pentium� III processo...
            • 2. Non-AGTL signals except PWRGOOD.
      • 3.4.3 Settling Limit Guideline
  • 4.0 Thermal Specifications and Design Considerations
    • 4.1 Thermal Specifications
      • 1.13
      • 1.13
      • 512
      • 06B0
      • 06B1
      • 27.9
      • 69
      • 0
      • 06B4
      • 28.7
      • 1.26
      • 1.26
      • 512
      • 06B0
      • 06B1
      • 29.5
      • 69
      • 0
      • 06B4
      • 30.4
      • 1.40
      • 1.40
      • 512
      • 06B0
      • 06B1
      • 31.2
      • 69
      • 0
      • 06B4
      • 32.2
        • 1. These values are specified at nominal VccCORE for the processor pins.
        • 2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGT...
        • 3. Processor core power includes only the power dissipated by the core die.
      • 4.1.1 THERMTRIP# Requirement
        • Table 28. THERMTRIP# Time Requirement
          • VCC
          • 1/2 Nominal VCC
          • 5 seconds
          • VTT
          • 1/2 Nominal VTT
          • 5 seconds
      • 4.1.2 Thermal Diode
        • Table 29. Thermal Diode Parameters1
          • Ifw
          • Forward Bias Current
          • 5
          • N/A
          • 150
          • �A
          • n
          • Diode Ideality Factor
          • 1.001452
          • 1.007152
          • 1.012852
          • Ifw
          • Forward Bias Current
          • 5
          • N/A
          • 300
          • �A
          • n
          • Diode Ideality Factor
          • 1.000807
          • 1.009528
          • 1.018249
            • 1. Intel does not support or recommend operation of the thermal diode under reverse bias.
            • 2. Characterized at 75�� C with a forward bias current of 5 - 150 mA.
            • 3. Characterized at 75�� C with a forward bias current of 5 - 300 mA.
            • 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by t...
            • 5. Not 100% tested. Specified by design characterization.
        • Table 30. Thermal Diode Interface
          • THERMDP
          • AL31
          • diode anode (p_junction)
          • THERMDN
          • AL29
          • diode cathode (n_junction)
    • 4.2 Thermal Metrology
  • 5.0 Mechanical Specifications
    • Note: For Figure 22, the following apply:
      • 1. Unless otherwise specified, the following drawings are dimensioned in inches.
      • 2. All dimensions provided with tolerances are guaranteed to be met for all normal production pro...
      • 3. Figures and drawings labeled as �Reference Dimensions� are provided for informational purposes...
      • 4. Drawings are not to scale.
    • 5.1 FC-PGA2 Mechanical Specifications
      • Figure 22. Package Dimensions
      • Table 31. Intel� Pentium� III processor with 512KB L2 Cache Package Dimensions
        • A1
        • 2.266
        • 2.690
        • 0.089
        • 0.106
        • A2
        • 0.980
        • 1.180
        • 0.038
        • 0.047
        • B1
        • 30.800
        • 31.200
        • 1.212
        • 1.229
        • B2
        • 30.800
        • 31.200
        • 1.212
        • 1.229
        • C1
        • 33.000 max
        • 1.299 max
        • C2
        • 33.000 max
        • 1.299 max
        • D
        • 49.428
        • 49.632
        • 1.946
        • 1.954
        • D1
        • 45.466
        • 45.974
        • 1.790
        • 1.810
        • G1
        • 0.000
        • 17.780
        • 0.000
        • 0.700
        • G2
        • 0.000
        • 17.780
        • 0.000
        • 0.700
        • G3
        • 0.000
        • 0.889
        • 0.000
        • 0.035
        • H
        • 2.540
        • Nominal
        • 0.100
        • Nominal
        • L
        • 3.048
        • 3.302
        • 0.120
        • 0.130
        • FP
        • 0.431
        • 0.483
        • 0.017
        • 0.019
        • Pin TP
        • 0.508 Diametric True Position (Pin-to-Pin)
        • 0.020 Diametric True Position (Pin-to-Pin)
          • 1. It is not recommended to use any portion of the processor substrate as a mechanical reference ...
          • 2. Parameters assume uniformly applied loads
      • Table 32. Processor Case Loading Parameters
        • 200
        • 100
        • lbf
        • 125
        • N/A
        • lbf
        • 75
        • N/A
        • Ibf
          • 1. This specification applies to a uniform and a non-uniform load.
          • 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the ...
          • 3. Please see socket manufacturer�s force loading specification also to ensure compliance. Maximu...
      • Figure 23. FC-PGA2 IHS Flatness Specification
    • 5.2 Recommended Mechanical Keep-Out Zones
      • Figure 24. Volumetric Keep-Out
      • Figure 25. Component Keep-Out
    • 5.3 Processor Markings
      • Figure 26. Top Side Processor Markings
    • 5.4 Processor Signal Listing
      • Figure 27. Intel� Pentium� III processor with 512KB L2 Cache Pinout
      • Table 33. Signal Listing in Order by Signal Name
      • Table 34. Signal Listing in Order by Pin Number
  • 6.0 Boxed Processor Specifications
    • Note: Drawings in this section reflect only the specifications on the Intel� Boxed Processor prod...
      • Figure 28. Conceptual Boxed Intel� Pentium� III Processor with 512KB L2 Cache for the PGA370 Socket
    • 6.1 Mechanical Specifications
      • 6.1.1 Mechanical Specifications for the FC-PGA2 Package
        • Figure 29. Comparison between FC-PGA and FC-PGA2 package
        • Figure 30. Side View of Space Requirements for the Boxed Processor
        • Table 35. Boxed Processor Fan Heatsink Spatial Dimensions
          • 3.14
          • Inches
          • 1.81
          • Inches
          • 2.6
          • Inches
          • .29
          • .30
          • .33
          • Inches
          • .20
          • Inches
        • Figure 31. Dimensions of Mechanical Step Feature in Heatsink Base
      • 6.1.2 Boxed Processor Heatsink Weight
    • 6.2 Thermal Specifications
      • 6.2.1 Boxed Processor Cooling Requirements
        • Figure 32. Thermal Airspace Requirement for all Boxed Intel� Pentium� III Processor with 512KB L2...
      • 6.2.2 Boxed Processor Thermal Cooling Solution Clip
    • 6.3 Electrical Requirements for the Boxed Intel� Pentium� III Processor with 512KB L2 Cache
      • 6.3.1 Electrical Requirements
        • Figure 33. Boxed Processor Fan Heatsink Power Cable Connector Description
        • Table 36. Fan Heatsink Power and Signal Specifications
          • 10.8V
          • 12V
          • 13.2V
          • 100 mA
          • 2 pulses per fan revolution
        • Figure 34. Motherboard Power Header Placement Relative to the Boxed Intel� Pentium� III Processor...
  • 7.0 Processor Signal Description
    • 7.1 Alphabetical Signals Reference
      • Table 37. Signal Description (Sheet 1 of 9)
        • I
        • I/O
        • I/O
        • I/O
        • I/O
        • I
        • I/O
        • I/O
        • I/O
        • I/O
        • I/O
        • I
        • I/O
        • O
        • I
        • O
        • I/O
        • I/O
        • I
        • I/O
        • O
        • I/O
        • I
        • O
        • I
        • I/O
        • I/O
        • O
        • I
        • I
        • I
        • I
        • I/O
        • I
        • I
        • I/O
        • I
        • O
        • I
        • I
        • I/O
        • I
        • I
        • I/O
        • I/O
        • I
        • I
        • I
        • I
        • I
        • I
        • I
        • I
        • O
        • O
        • I
        • O
        • I
        • I/O
        • I
        • I
        • O
        • I
        • I
    • 7.2 Signal Summaries
      • Table 38. Output Signals 
        • BSEL[1:0]
        • High
        • Asynch
        • Power/Other
        • CPUPRES#
        • Low
        • Asynch
        • Power/Other
        • DETECT
        • High
        • Asynch
        • Power/Other
        • FERR#
        • Low
        • Asynch
        • CMOS Output
        • IERR#
        • Low
        • Asynch
        • CMOS Output
        • PRDY#
        • Low
        • BCLK
        • AGTL Output
        • TDO
        • High
        • TCK
        • TAP Output
        • THERMTRIP#
        • Low
        • Asynch
        • CMOS Output
        • VID[3:0, 25mV]
        • N/A
        • Asynch
        • Power/Other
      • Table 39. Input Signals (Sheet 1 of 2)
        • A20M#
        • Low
        • Asynch
        • CMOS Input
        • Always1
        • BCLK
        • High
        • �
        • System Bus Clock
        • Always
        • BPRI#
        • Low
        • BCLK
        • AGTL Input
        • Always
        • DEFER#
        • Low
        • BCLK
        • AGTL Input
        • Always
        • FLUSH#
        • Low
        • Asynch
        • CMOS Input
        • Always1
        • IGNNE#
        • Low
        • Asynch
        • CMOS Input
        • Always1
        • INIT#
        • Low
        • Asynch
        • CMOS Input
        • Always1
        • INTR
        • High
        • Asynch
        • CMOS Input
        • APIC disabled mode
        • KEY
        • N/A
        • Asynch
        • Power/Other
        • LINT[1:0]
        • High
        • Asynch
        • CMOS Input
        • APIC enabled mode
        • NMI
        • High
        • Asynch
        • CMOS Input
        • APIC disabled mode
        • NCHCTRL
        • N/A
        • Asynch
        • Power/Other
        • PICCLK
        • High
        • �
        • APIC Clock
        • Always
        • PREQ#
        • Low
        • Asynch
        • CMOS Input
        • Always
        • PWRGOOD
        • High
        • Asynch
        • CMOS Input
        • Always
        • RESET#
        • Low
        • BCLK
        • AGTL Input
        • Always
        • RESET2#
        • Low
        • BCLK
        • AGTL Input
        • RSP#
        • Low
        • BCLK
        • AGTL Input
        • Always
        • RTTCTRL
        • N/A
        • Asynch
        • Power/Other
        • SLEWCTRL
        • N/A
        • Asynch
        • Power/Other
        • SLP#
        • Low
        • Asynch
        • CMOS Input
        • During Stop-Grant state
        • SMI#
        • Low
        • Asynch
        • CMOS Input
        • STPCLK#
        • Low
        • Asynch
        • CMOS Input
        • TCK
        • High
        • �
        • TAP Input
        • TDI
        • High
        • TCK
        • TAP Input
        • TMS
        • High
        • TCK
        • TAP Input
        • TRST#
        • Low
        • Asynch
        • TAP Input
        • VTT_PWRGD
        • High
        • Asynch
        • Power/Other
      • Table 40. Input/Output Signals (Single Driver)
        • A[35:3]#
        • Low
        • BCLK
        • AGTL I/O
        • ADS#, ADS#+1
        • ADS#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • AP[1:0]#
        • Low
        • BCLK
        • AGTL I/O
        • ADS#, ADS#+1
        • BP[3:2]#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • BPM[1:0]#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • BR[1:0]#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • D[63:0]#
        • Low
        • BCLK
        • AGTL I/O
        • DRDY#
        • DBSY#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • DEP[7:0]#
        • Low
        • BCLK
        • AGTL I/O
        • DRDY#
        • DRDY#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • LOCK#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • REQ[4:0]#
        • Low
        • BCLK
        • AGTL I/O
        • ADS#, ADS#+1
        • RP#
        • Low
        • BCLK
        • AGTL I/O
        • ADS#, ADS#+1
        • RS[2:0]#
        • Low
        • BCLK
        • AGTL Input
        • Always
        • TRDY#
        • Low
        • BCLK
        • AGTL Input
      • Table 41. Input/Output Signals (Multiple Driver)
        • AERR#
        • Low
        • BCLK
        • AGTL I/O
        • ADS#+3
        • BERR#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • BINIT#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • BNR#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • HIT#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • HITM#
        • Low
        • BCLK
        • AGTL I/O
        • Always
        • PICD[1:0]
        • High
        • PICCLK
        • APIC I/O
        • Always
      • 1.0 Introduction 1
      • 2.0 Electrical Specifications 5
      • 3.0 Signal Quality Specifications 37
      • 4.0 Thermal Specifications and Design Considerations 47
      • 5.0 Mechanical Specifications 49
      • 6.0 Boxed Processor Specifications 70
      • 7.0 Processor Signal Description 76