Order Number: 306666, Revision: 001
April 2005
Intel StrataFlash
Embedded Memory
(P30)
1-Gbit P30 Family
Datasheet
Product Features
The Intel StrataFlash
Embedded Memory (P30) product is the latest generation of Intel
StrataFlash
memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device
brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.
Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR
device, and support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options, and three
industry standard package choices.
The P30 product family is manufactured using Intel
130 nm ETOXTM VIII process technology.
High performance
-- 85/88 ns initial access
-- 40 MHz with zero wait states, 20 ns clock-to-
data output synchronous-burst read mode
-- 25 ns asynchronous-page read mode
-- 4-, 8-, 16-, and continuous-word burst mode
-- Buffered Enhanced Factory Programming
(BEFP) at 5 s/byte (Typ)
-- 1.8 V buffered programming at 7 s/byte (Typ)
Architecture
-- Multi-Level Cell Technology: Highest Density
at Lowest Cost
-- Asymmetrically-blocked architecture
-- Four 32-KByte parameter blocks: top or
bottom configuration
-- 128-KByte main blocks
Voltage and Power
-- V
CC
(core) voltage: 1.7 V 2.0 V
-- V
CCQ
(I/O) voltage: 1.7 V 3.6 V
-- Standby current: 55 A (Typ) for 256-Mbit
-- 4-Word synchronous read current:
13 mA (Typ) at 40 MHz
Quality and Reliability
-- Operating temperature: 40 C to +85 C
1-Gbit in SCSP is 30 C to +85 C
-- Minimum 100,000 erase cycles per block
-- ETOXTM VIII process technology (130 nm)
Security
-- One-Time Programmable Registers:
64 unique factory device identifier bits
64 user-programmable OTP bits
Additional 2048 user-programmable OTP bits
-- Selectable OTP Space in Main Array:
4x32KB parameter blocks + 3x128KB main
blocks (top or bottom configuration)
-- Absolute write protection: V
PP
= V
SS
-- Power-transition erase/program lockout
-- Individual zero-latency block locking
-- Individual block lock-down
Software
-- 20 s (Typ) program suspend
-- 20 s (Typ) erase suspend
-- Intel
Flash Data Integrator optimized
-- Basic Command Set and Extended Command
Set compatible
-- Common Flash Interface capable
Density and Packaging
-- 64/128/256-Mbit densities in 56-Lead TSOP
package
-- 64/128/256/512-Mbit densities in 64-Ball
Intel
Easy BGA package
-- 64/128/256/512-Mbit and 1-Gbit densities in
Intel
QUAD+ SCSP
-- 16-bit wide data bus
April 2005
Intel StrataFlash
Embedded Memory (P30)
Datasheet
2
Order Number: 306666, Revision: 001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
StrataFlash Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing
your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at
http://www.intel.com
.
Copyright 2005, Intel Corporation
* Other names and brands may be claimed as the property of others.
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
April 2005
Order Number: 306666, Revision: 001
3
Contents
1.0 Introduction
...............................................................................................................................7
1.1
Nomenclature .......................................................................................................................7
1.2
Acronyms..............................................................................................................................7
1.3
Conventions..........................................................................................................................8
2.0 Functional Overview
..............................................................................................................9
3.0 Package Information
............................................................................................................10
3.1
56-Lead TSOP Package .....................................................................................................10
3.2
64-Ball Easy BGA Package ................................................................................................12
3.3
QUAD+ SCSP Packages....................................................................................................13
4.0 Ballout and Signal Descriptions
......................................................................................17
4.1
Signal Ballout......................................................................................................................17
4.2
Signal Descriptions .............................................................................................................20
4.3
SCSP Configurations..........................................................................................................22
4.4
Memory Maps .....................................................................................................................24
5.0 Maximum Ratings and Operating Conditions
...........................................................29
5.1
Absolute Maximum Ratings ................................................................................................29
5.2
Operating Conditions ..........................................................................................................30
6.0 Electrical Specifications
.....................................................................................................31
6.1
DC Current Characteristics.................................................................................................31
6.2
DC Voltage Characteristics.................................................................................................32
7.0 AC Characteristics
................................................................................................................33
7.1
AC Test Conditions.............................................................................................................33
7.2
Capacitance........................................................................................................................34
7.3
AC Read Specifications ......................................................................................................35
7.4
AC Write Specifications ......................................................................................................41
7.5
Program and Erase Characteristics....................................................................................45
8.0 Power and Reset Specifications
.....................................................................................46
8.1
Power Up and Down...........................................................................................................46
8.2
Reset Specifications ...........................................................................................................46
8.3
Power Supply Decoupling...................................................................................................47
9.0 Device Operations
.................................................................................................................48
9.1
Bus Operations ...................................................................................................................48
9.1.1
Reads ....................................................................................................................48
9.1.2
Writes.....................................................................................................................49
9.1.3
Output Disable .......................................................................................................49
9.1.4
Standby..................................................................................................................49
9.1.5
Reset .....................................................................................................................49
9.2
Device Commands .............................................................................................................50
9.3
Command Definitions .........................................................................................................51
1-Gbit P30 Family
April 2005
Intel StrataFlash
Embedded Memory (P30)
Datasheet
4
Order Number: 306666, Revision: 001
10.0 Read Operations
.................................................................................................................... 53
10.1 Asynchronous Page-Mode Read........................................................................................ 53
10.2 Synchronous Burst-Mode Read.......................................................................................... 53
10.3 Read Configuration Register .............................................................................................. 54
10.3.1 Read Mode ............................................................................................................ 55
10.3.2 Latency Count........................................................................................................ 55
10.3.3 WAIT Polarity......................................................................................................... 57
10.3.4 Data Hold............................................................................................................... 58
10.3.5 WAIT Delay............................................................................................................ 59
10.3.6 Burst Sequence ..................................................................................................... 59
10.3.7 Clock Edge ............................................................................................................ 59
10.3.8 Burst Wrap............................................................................................................. 59
10.3.9 Burst Length .......................................................................................................... 60
11.0 Programming Operations
.................................................................................................. 61
11.1 Word Programming............................................................................................................. 61
11.1.1 Factory Word Programming................................................................................... 62
11.2 Buffered Programming........................................................................................................ 62
11.3 Buffered Enhanced Factory Programming ......................................................................... 63
11.3.1 BEFP Requirements and Considerations .............................................................. 64
11.3.2 BEFP Setup Phase................................................................................................ 64
11.3.3 BEFP Program/Verify Phase ................................................................................. 64
11.3.4 BEFP Exit Phase ................................................................................................... 65
11.4 Program Suspend............................................................................................................... 65
11.5 Program Resume................................................................................................................ 66
11.6 Program Protection............................................................................................................. 66
12.0 Erase Operations
................................................................................................................... 67
12.1 Block Erase......................................................................................................................... 67
12.2 Erase Suspend ................................................................................................................... 67
12.3 Erase Resume .................................................................................................................... 68
12.4 Erase Protection ................................................................................................................. 68
13.0 Security Modes
....................................................................................................................... 69
13.1 Block Locking...................................................................................................................... 69
13.1.1 Lock Block ............................................................................................................. 69
13.1.2 Unlock Block .......................................................................................................... 69
13.1.3 Lock-Down Block ................................................................................................... 69
13.1.4 Block Lock Status .................................................................................................. 70
13.1.5 Block Locking During Suspend.............................................................................. 70
13.2 Selectable One-Time Programmable Blocks...................................................................... 71
13.3 Protection Registers ........................................................................................................... 72
13.3.1 Reading the Protection Registers .......................................................................... 73
13.3.2 Programming the Protection Registers.................................................................. 73
13.3.3 Locking the Protection Registers ........................................................................... 74
14.0 Special Read States
............................................................................................................. 75
14.1 Read Status Register.......................................................................................................... 75
14.1.1 Clear Status Register............................................................................................. 76
14.2 Read Device Identifier ........................................................................................................ 76
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
April 2005
Order Number: 306666, Revision: 001
5
14.3 CFI Query ...........................................................................................................................77
Appendix A Write State Machine
..........................................................................................78
Appendix B Flowcharts
............................................................................................................85
Appendix C Common Flash Interface
................................................................................93
Appendix D Additional Information
................................................................................... 100
Appendix E Ordering Information for Discrete Products
........................................ 101
Appendix F Ordering Information for SCSP Products
..............................................102
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