Introduction
In today's connected world, network integrity
is critically important. Built-in system redun-
dancy prevents catastrophic data loss in the
quest to achieve or beat 99.999 percent
uptime. Today's T1/E1/J1 N+1 redundancy
protection is implemented through the use
of multiple mechanical relays. But design
requirements frequently dictate adding more
ports to boards already loaded with mechanical
relays, challenging designers to provide high
port-density solutions.
Intel innovated in 1999 by introducing
Intel
Hitless Protection Switching (Intel
HPS)
with its award winning LX38x family of Line
Interface Units (LIU), providing a more reliable
solution to 1+1 protection without mechanical
relays. Today, Intel has developed an N+1
protection solution known as Intel
Protection
Interface Unit that performs the function of
an analog T1/E1/J1 multiplexing element.
Product Description
Eight short-haul T1/E1/J1 selectable ports per
PIU, scalable to various architectures, provide
a simplified analog interface that can operate
without a microprocessor. By combining
several PIU chips in a protection-switching
matrix board that effectively routes any back
plane signal to a back-up protection board,
designers can achieve significant space,
power savings as well as increasing
system reliability.
Intel
LXT3008
Protection Interface Unit
Silicon Solution for N+1 Protection in T1/E1/J1 Short-Haul Applications
product brief
Increased Performance and Reliability
Because it is silicon-based, the switching
time is considerably faster than mechanical
relays and reduces downtime. The LXT3008
PIU can be controlled through hardware pins
for fast data switching, or through a simple
four-wire serial interface. Each LXT3008 PIU
includes a tri-stateable analog short-haul inter-
face and a tri-stateable digital data interface.
Reduced Board Space
Increased bandwidth and limited available
space in service providers installation push
designers toward increased port density
on line cards. The LXT3008 helps replace
as many as 32 relays.
Reduced Time-to-Market
Through extensive support tools, Intel
provides designers detailed guidelines on
how to implement N+1 Protection with the
LXT3008.
Intel
Internet Exchange
Architecture
Digital Tx
Interface
Digital Rx
Interface
Analog
Driver
x8
Analog
Receiver
x8
Timing
Hardware or
Serial Control
Interface
Intel
LXT3008 Block Diagram
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Intel Access
Developer's Site
http://developer.intel.com
Intel
Internet Exchange Architecture Home Page
http://www.intel.com/IXA
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http://developer.intel.com/design/network
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2001 Intel Corporation
Order Number: 249383-001 Printed in the USA/0201/7K/MS/DC
Supervisory
LXT3008
Control
TDM
System
T1/E1
Protection
T1/E1
Primary
T1/E1
Line Card
T1/E1
Line Card
T1/E1
Line Card
Line Transition
T1/E1
Back-in
Protection
Matrix
LXT3008
LXT3008
LXT3008
LXT3008
System Architecture
Support Collateral
s
LXT3008 Data Sheet
s
Intel
N+1 Redundancy Solution Application Notes
s
Intel
Hitless Protection Switching Application Note
s
LXT384 Design Assistant
s
Demo Board for 1+1 and N+1 Applications
Key Applications
s
SONET/SDH Add Drop Multiplexers (ADMs)
s
Digital Access Cross Connect Systems (DACS)
s
Digital Loop Carriers (DLCs)
s
Base Station Controllers
s
Central Office Switches
s
E1-E3, T1-T3 Multiplexers
s
Access Concentrator
Intel
Internet Exchange Architecture
Intel
Internet Exchange Architecture is an end-to-end
family of high-performance, flexible and scalable
hardware and software development building blocks
designed to meet the growing performance requirements
of today's networks. Based on programmable silicon and
software building blocks, Intel
IXA solutions enable faster
development, more cost-effective deployment and future
upgradability of network and communications systems.
Additional information can be found
at www.intel.com/IXA
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