LXT300Z/LXT301Z

Advanced T1/E1 Short-Haul Transceivers

Datasheet

The LXT300Z and LXT301Z are fully integrated transceivers for both North American 1.544
Mbps (T1) and International 2.048 Mbps (E1) applications. They are pin and functionally
compatible with standard LXT300/301 devices, with some circuit enhancements.

The LXT300Z provides receive jitter attenuation starting at 3 Hz, and is microprocessor
controllable through a serial interface. The LXT301Z is pin compatible, but does not provide
jitter attenuation or a serial interface. An advanced transmit driver architecture provides constant
low output impedance for both marks and spaces, for improved Bit Error Rate performance over
various cable network configurations. Both transceivers offer a variety of diagnostic features
including transmit and receive monitoring. Clock inputs may be derived from an on-chip crystal
oscillator or from digital inputs. They use an advanced double-poly, double-metal CMOS
process and require only a single 5-volt power supply.

Applications

Product Features

PCM/Voice Channel Banks

Data Channel Bank/Concentrator

T1/E1 multiplexers

Digital Access and Cross-connect Systems
(DACS)

Computer to PBX interfaces (CPI & DMI)

High-speed data transmission lines

Interfacing Customer Premises Equipment
to a CSU

Digital Loop Carrier (DLC) terminals

Data recovery and clock recovery functions

Receive jitter attenuation starting at 3 Hz
exceeds AT&T Pub 62411, Pub 43801, Pub
43802, ITU G.703, and ITU G.823
(LXT300Z only)

Line driver with constant low mark and
space impedance (3

typical)

Minimum receive signal of 500 mV

Adaptive and selectable (E1/DSX-1) slicer
levels for improved SNR

Programmable transmit equalizer shapes
pulses to meet DSX-1 pulse template from
0 to 655 feet or drive 120

twisted pair or

coax cable for E1

Local and remote loopback functions

Digital Transmit Driver Monitor

Digital Receive Monitor with Loss of
Signal (LOS) output and first mark reset

Receiver jitter tolerance 0.4 UI from 40
kHz to 100 kHz

Microprocessor controllable (LXT300Z
only)

Compatible with most popular PCM
framers

Available in 28-pin DIP or PLCC

As of January 15, 2001, this document replaces the Level One document

Order Number: 249066-001

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers.

January 2001

Datasheet

Information in this document is provided in connection with Intel

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The LXT300Z/LXT301Z may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Datasheet

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Contents

1.0

Pin Assignments and Signal Descriptions

...................................................... 6

2.0

Functional Description

............................................................................................. 9

2.1

Power Requirements............................................................................................. 9
2.1.1

Reset Operation (LXT300Z and LXT301Z) .............................................. 9

2.2

Receiver .............................................................................................................. 10
2.2.1

Receive (Loss of Signal) Monitor ........................................................... 11

2.2.2

Jitter Attenuation (LXT300Z Only).......................................................... 11

2.3

Transmitter .......................................................................................................... 11
2.3.1

Driver Performance Monitor ................................................................... 11

2.3.2

Line Code ...............................................................................................12

2.4

Operating Modes................................................................................................. 12
2.4.1

Host Mode Operation (LXT300Z Only)................................................... 12

2.4.2

Hardware Mode Operation (LXT300Z and LXT301Z) ............................ 12

2.4.3

Diagnostic Mode Operation .................................................................... 14
2.4.3.1 Transmit All Ones ...................................................................... 14
2.4.3.2 Remote Loopback .....................................................................14
2.4.3.3 Local Loopback ......................................................................... 14

3.0

Application Information

.........................................................................................16

3.1

LXT300Z Host Mode 1.544 Mbps T1 Interface ................................................... 16

3.2

LXT300Z Hardware Mode E1 Interface Application ............................................17
3.2.1

LXT301Z 1.544 Mbps T1 Interface Application ...................................... 19

3.2.2

LXT301Z 2.048 Mbps E1 Interface Application...................................... 20

4.0

Test Specifications

.................................................................................................. 21

5.0

Mechanical Specifications

.................................................................................... 29

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

Figures

LXT300Z/LXT301Z Block Diagram ....................................................................... 5

LXT300 Pin Assignments and Package Markings ................................................ 6

LXT301Z Block Diagram ..................................................................................... 10

50% AMI Coding ................................................................................................. 13

LXT300Z Serial Interface Data Structure ............................................................ 15

Typical LXT300Z 1.544 Mbps T1 Application (Host Mode)................................. 17

Typical LXT300Z 75 W E1 Application (Hardware Mode)................................... 18

Typical LXT301Z 1.544 Mbps T1 Application ..................................................... 19

Typical LXT301Z 75 W E1 Application................................................................ 20

LXT300Z Typical Receive Jitter Tolerance ......................................................... 23

LXT300Z Typical Receive Jitter Transfer Performance ...................................... 24

LXT300Z Receive Clock Timing Diagram ........................................................... 25

LXT301Z Receive Clock Timing Diagram ........................................................... 26

LXT300Z/301Z Transmit Clock Timing Diagram ................................................. 26

LXT300Z Serial Data Input Timing Diagram ....................................................... 27

LXT300Z Serial Data Output Timing Diagram .................................................... 28

Package Specifications ....................................................................................... 29

Tables

Pin Descriptions .................................................................................................... 7

LXT300Z Serial Data Output Bits (See

Figure 5

) ................................................ 13

Valid CLKE Settings............................................................................................ 13

Equalizer Control Inputs...................................................................................... 14

LXT300Z Crystal Specifications (External) ......................................................... 18

Absolute Maximum Ratings ................................................................................ 21

Recommended Operating Conditions ................................................................. 21

Electrical Characteristics..................................................................................... 21

Analog Characteristics ........................................................................................ 22

LXT300Z Receiver Timing Characteristics (See

Figure 12

)................................ 24

LXT301Z Receive Timing Characteristics (See

Figure 13

) ................................. 25

LXT300Z/301Z Master Clock and Transmit Timing Characteristics
(See Figure 14) ................................................................................................... 26

LXT300Z Serial I/O Timing Characteristics (See

Figure 15

and

Figure 16

)........ 27

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

1.0

Pin Assignments and Signal Descriptions

Figure 2. LXT300 Pin Assignments and Package Markings

Package Topside Markings

Marking

Definition

Part #

Unique identifier for this product family.

Rev #

Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information.

Lot #

Identifies the batch.

FPO #

Identifies the Finish Process Order.

MCLK

TCLK

TPOS

TNEG

MODE

RNEG

RPOS

RCLK

XTALIN

XTALOUT

DPM

LOS

TTIP

TGND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

CLKE / TAOS
SCLK / LLOOP
CS / RLOOP
SDO / EC3
SDI / EC2
INT / EC1
RGND
RV+
RRING
RTIP
MRING
MTIP
TRING
TV+

LXT30

ZNE

MCLK

TCLK

TPOS

TNEG

GND

RNEG

RPOS

RCLK

N/C

DPM

LOS

TTIP

TGND

TAOS
LLOOP
RLOOP
EC3
EC2
EC1
RGND
RV+
RRING
RTIP
MRING
MTIP
TRING
TV+

MODE

RNEG

RPOS

RCLK

XTALIN

XTALOUT

DPM

25
24
23
22
21
20
19

5
6
7
8
9
10
11

SDO / EC3
SDI / EC2
INT / EC1
RGND
RV+
RRING
RTIP

MCLK

/ TA

/ L

OOP

TRI

I
P

I
N

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

LXT30

ZNE

GND

RNEG

RPOS

RCLK

N/C

DPM

25
24
23
22
21
20
19

5
6
7
8
9
10
11

EC3
EC2
EC1
RGND
RV+
RRING
RTIP

TNE

TCL

OOP

TGND

I
N

I
P

MRI

LXT301ZPE XX
XXXXXX
XXXXXXXX

LXT300ZPE XX
XXXXXX
XXXXXXXX

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

Table 1. Pin Descriptions

Pin #

Sym

I/O

Description

MCLK

Master Clock. A 1.544 or 2.048 MHz clock input used to generate internal clocks. Upon
Loss of Signal (LOS), RCLK is derived from MCLK.

LXT300Z Only: If MCLK is not applied, this pin must be grounded.

TCLK

Transmit Clock. Transmit clock input. TPOS and TNEG are sampled on the falling edge of
TCLK. If TCLK is grounded, the output drivers enter a high-Z state, except during Remote
Loopback.

TPOS

Transmit Positive Data. Input for positive pulse to be transmitted on the twisted-pair line or
coax.

TNEG

Transmit Negative Data. Input for negative pulse to be transmitted on the twisted-pair line.

MODE

Mode Select (LXT300Z). Setting MODE High puts the LXT300Z in the Host mode. In the Host
mode, the serial interface is used to control the LXT300Z and determine its status. Setting
MODE Low puts the LXT300Z in the Hardware (H/W) mode. In the Hardware mode, the serial
interface is disabled and hard-wired pins are used to control configuration and report status.

GND

Ground (LXT301Z). Tie to Ground.

RNEG

Receive Negative Data; Receive Positive Data. Received data outputs. A signal on RNEG
corresponds to receipt of a negative pulse on RTIP and RRING. A signal on RPOS
corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and RPOS outputs are
Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the rising edge of RCLK.

LXT300Z only: In the Host mode, CLKE determines the clock edge at which these outputs are
stable and valid. In the Hardware mode both outputs are stable and valid on the rising edge of
RCLK.

RPOS

RCLK

Recovered Clock. This is the clock recovered from the signal received at RTIP and RRING.

Receive Termination (LXT301Z). Connect to RV+ through a 1 k

resistor.

XTALIN

Crystal Input; Crystal Output (LXT300Z). An external crystal operating at four times the bit
rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an
18.7 pF load) is required to enable the jitter attenuation function of the LXT300Z. These pins
may also be used to disable the jitter attenuator by connecting the XTALIN pin to the positive
supply through a resistor, and floating the XTALOUT pin.

XTALOUT

N/C

No Connection (LXT301Z).

DPM

Driver Performance Monitor. DPM goes High when the transmit monitor loop (MTIP and
MRING) does not detect a signal for 63 ±2 clock periods. DPM remains High until a signal is
detected.

LOS

Loss of Signal. LOS goes High when 175 consecutive spaces have been detected from
receive. LOS returns Low when a mark is detected from the receiver.

TTIP

Transmit Tip; Transmit Ring. Differential Driver Outputs. These outputs are designed to
drive a 25

load. The transmitter will drive 100

shielded twisted-pair cable through a 1:2

step-up transformer without additional components. To drive
75

coaxial cable, two 2.2

resistors are required in series with the transformer.

TRING

TGND

Transmit Ground. Ground return for the transmit driver power supply TV+.

TV+

Transmit Driver Power Supply. +5 VDC power supply input for the transmit drivers. TV+
must not vary from RV+ by more than ±0.3 V.

MTIP

Monitor Tip; Monitor Ring. These pins are used to monitor the tip and ring transmit outputs.
The transceiver can be connected to monitor its own output or the output of another LXT300Z
or LXT301Z on the board.

MRING

1. DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output; S = Supply.

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

RTIP

Receive Tip; Receive Ring. The AMI signal received from the line is applied at these pins. A
center-tapped, center-grounded, 2:1 step-up transformer is required on these pins. Data and
clock from the signal applied at these pins are recovered and output on the RPOS/RNEG and
RCLK pins.

RRING

RV+

Receive Power Supply. +5 VDC power supply for all circuits except the transmit drivers.
(Transmit drivers are supplied by TV+.)

RGND

Receive Ground. Ground return for power supply RV+.

INT

Interrupt (LXT300Z - Host Mode). This output goes Low to flag the host processor when
LOS or DPM go active. INT is an open-drain output and should be tied to power supply RV+
through a resistor. INT is reset by clearing the respective register bit (LOS and/or DPM).

EC1

Equalizer Control 1 (LXT301Z and LXT300Z - H/W Mode). The signal applied at this pin is
used in conjunction with EC2 and EC3 inputs to determine shape and amplitude of AMI output
transmit pulses.

SDI

Serial Data In (LXT300Z - Host Mode). The serial data input stream is applied to this pin. SDI
is sampled on the rising edge of SCLK.

EC2

Equalizer Control 2 (LXT301Z and LXT300Z - H/W Mode). The signal applied at this pin is
used in conjunction with EC1 and EC3 inputs to determine shape and amplitude of AMI output
transmit pulses.

SDO

Serial Data Out (LXT300Z - Host Mode). The serial data from the on-chip register is output
on this pin. If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low SDO is
valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial
port is being written to and when CS is High.

EC3

Equalizer Control 3 (LXT301Z and LXT300Z - H/W Mode). The signal applied at this pin is
used in conjunction with EC1 and EC2 inputs to determine shape and amplitude of AMI output
transmit pulses.

CS DI

Chip Select (LXT300Z - Host Mode). This input is used to access the serial interface. For
each read or write operation, CS must transition from High to Low, and remain Low.

RLOOP

Remote Loopback (LXT301Z and LXT300Z - H/W Mode). Setting RLOOP High enables the
Remote Loopback mode. Setting both RLOOP and LLOOP High causes a Reset.

SCLK

Serial Clock (LXT300Z - Host Mode). This clock is used to write data to or read data from the
serial interface registers.

LLOOP

Local Loopback (LXT301Z and LXT300Z - H/W Mode). This input controls loopback
functions. Setting LLOOP High enables the Local Loopback mode.

CLKE

Clock Edge (LXT300Z - Host Mode). Setting CLKE High causes RPOS and RNEG to be
valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. When
CLKE is Low, RPOS and RNEG are valid on the rising edge of RCLK, and SDO is valid on the
falling edge of SCLK.

TAOS

Transmit All Ones (LXT301Z and LXT300Z - H/W Mode). When High, a continuous stream
of marks is transmitted at the TCLK frequency. Activating TAOS causes TPOS and TNEG
inputs to be ignored. TAOS is inhibited during Remote Loopback.

Table 1. Pin Descriptions (Continued)

Pin #

Sym

I/O

Description

1. DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output; S = Supply.

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

2.0

Functional Description

The LXT300Z and LXT301Z are fully integrated PCM transceivers for both 1.544 Mbps (DSX-1)
and 2.048 Mbps (E1) applications. Both transceivers allow full-duplex transmission of digital data
over existing twisted-pair or coax installations. The first page of this data sheet shows a simplified
block diagram of the LXT300Z and

Figure 3

shows the LXT301Z. The LXT301Z is similar to the

LXT300Z, but does not incorporate the Jitter Attenuator and associated Elastic Store, nor the serial
interface port.

The LXT300Z and LXT301Z transceivers each interface with two twisted-pair or coax lines (one
pair or coax for transmit, one pair or coax for receive) through standard pulse transformers and
appropriate resistors.

2.1

Power Requirements

The LXT300Z and LXT301Z are low-power CMOS devices. Each operates from a single +5 V
power supply which can be connected externally to both the transmitter and receiver. However, the
two inputs must be within

0.3V of each other, and decoupled to their respective grounds

separately. Refer to

"Application Information" on page 16

for typical decoupling circuitry.

Isolation between the transmit and receive circuits is provided internally.

2.1.1

Reset Operation (LXT300Z and LXT301Z)

Upon power up, the transceiver is held static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and
receive delay lines and lock the Phase Lock Loop (PLL) to the receive line. A reference clock is
required to calibrate the delay lines. The transmitter reference is provided by TCLK. MCLK
provides the receiver reference for the LXT301Z. The crystal oscillator provides the receiver
reference in the LXT300Z. If the LXT300Z crystal oscillator is grounded, MCLK is used as the
receiver reference clock.

The transceiver can also be reset from the Host mode or Hardware mode. In Host mode, reset is
commanded by simultaneously writing RLOOP and LLOOP to the register. In Hardware mode,
reset is commanded by holding RLOOP and LLOOP High simultaneously for 200 ns. Reset is
initiated on the falling edge of the reset request. In either mode, the reset clears and sets all registers
to 0 and then calibration begins.

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

2.2

Receiver

The LXT300Z and LXT301Z receivers are identical except for the Jitter Attenuator and Elastic
Store. The following discussion applies to both transceivers except where noted.

The signal is received from one twisted-pair line on each side of a center-grounded transformer.
Positive pulses are received at RTIP and negative pulses are received at RRING. Recovered data is
output at RPOS and RNEG, and the recovered clock is output at RCLK. Refer to the "Test
Specifications" section of this data sheet for receiver timing.

The signal received at RPOS and RNEG is processed through the peak detector and data slicers.
The peak detector samples the inputs and determines the maximum value of the received signal. A
percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum
signal-to-noise ratio. For DSX-1 applications (determined by Equalizer Control inputs EC1~EC3

000) the threshold is set to 70% of the peak value. This threshold is maintained above 65% for up
to 15 successive zeros over the range of specified operating conditions. For E1 applications (EC
inputs = 000) the threshold is set to 50%.

The receiver is capable of accurately recovering signals with up to -13.6 dB of attenuation (from
2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is
1500 feet of ABAM cable (approximately 6 dB). Regardless of received signal level, the peak
detectors are held above a minimum level of 300 mV to provide immunity from impulsive noise.
Note that during a Loss of Signal (LOS) condition, RPOS and RNEG are squelched if the received
input signal drops below 300 mV.

After processing through the data slicers, the received signal is routed to the data and clock
recovery sections, and to the receive monitor. In the LXT300Z only, recovered clock signals are
supplied to the jitter attenuator and the data latch. The recovered data is passed to the elastic store
where it is buffered and synchronized with the dejittered recovered clock (RCLK). The data and
clock recovery circuits have an input jitter tolerance significantly better than required by Pub
62411.

Figure 3. LXT301Z Block Diagram

Control

Equalizer

Synchronizer

TPOS

TNEG

TCLK

Internal Clock

Generator

Timing

Recovery

Peak

Detector

TTIP

TRING

RTIP

RRING

Data

Latch

Receive

Monitor

Transmit

Driver

Monitor

MTIP

MRING

MCLK

RPOS

LOS

RNEG

DPM

Constant Impedance

Line Driver

Data Slicers

EC1, EC2, EC3

RCLK

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

2.2.1

Receive (Loss of Signal) Monitor

The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175 consecutive zeros
(spaces). The receiver monitor loads a digital counter at the RCLK frequency. The count is
incremented each time a zero is received, and reset to zero each time a one (mark) is received.
Upon receipt of 175 consecutive zeros the LOS pin goes High, and the RCLK output is replaced
with MCLK. LOS is reset when the first mark is received.

(In the LXT300Z only, if MCLK is not supplied, the RCLK output will be replaced with the centered
crystal clock.)

2.2.2

Jitter Attenuation (LXT300Z Only)

In the LXT300Z, recovered clock signals are supplied to the jitter attenuator and the data latch. The
recovered data is passed to the elastic store where it is buffered and synchronized with the
dejittered recovered clock (RCLK). Jitter attenuation of the LXT300Z clock and data outputs (see

Figure 5

) is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external

crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to

page 18

for crystal

specifications. The ES is a 32 x 2-bit register. Recovered data is clocked into the ES with the
recovered clock signal, and clocked out of the ES with the dejittered clock from the JAL. When the
bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output
clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path.

2.3

Transmitter

The transmitter circuits in the LXT300Z and LXT301Z are identical. The following discussion
applies to both devices. Data received for transmission onto the line is clocked serially into the
device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The
transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in

Table 4

. Refer to the "Test Specifications" section of this data sheet for master and transmit clock

timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the
line at TTIP and TRING. Equalizer Control signals are hard-wired in the LXT301Z.

LXT300Z Only: Equalizer Control signals may be hardwired in the Hardware mode, or input as
part of the serial data stream (SDI) in the Host mode.

Pulses can be shaped for either 1.544 or 2.048 Mbps applications. DSX-1 applications with 1.544
Mbps pulses can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The
LXT300Z and LXT301Z also match FCC specifications for CSU applications. Pulses at 2.048
Mbps can drive coaxial or shielded twisted-pair lines using appropriate resistors in line with the
output transformer.

2.3.1

Driver Performance Monitor

The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the
TTIP and TRING at the output transformer. The DPM circuitry uses four comparators and a 150 ns
pulse discriminator to filter glitches. The DPM output level goes High upon detection of 63
consecutive zeros, and is cleared when a one is detected on the transmit line, or when a reset
command is received. The DPM output also goes High to indicate a ground on TTIP or TRING. A
ground fault induced DPM flag is automatically cleared when the ground condition is corrected
(chip reset is not required).

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

2.3.2

Line Code

The LXT300Z and LXT301Z transmit data as a 50% AMI line code as shown in

Figure 4

. Power

consumption is reduced by activating the AMI line driver only to transmit a mark. The output
driver is disabled during transmission of a space.

2.4

Operating Modes

The LXT300Z and LXT301Z transceivers can be controlled through hard-wired pins (Hardware
mode). Both transceivers can also be commanded to operate in one of several diagnostic modes.

LXT300Z Only: The LXT300Z can be controlled by a microprocessor through a serial interface
(Host mode). The mode of operation is set by the MODE pin logic level.

2.4.1

Host Mode Operation (LXT300Z Only)

To allow a host microprocessor to access and control the LXT300Z through the serial interface,
MODE is set to 1. The serial interface (SDI/SDO) uses a 16-bit word consisting of an 8-bit
Command/Address byte and an 8-bit Data byte.

Figure 5

shows the serial interface data structure

and relative timing.

The Host mode provides a latched Interrupt output (INT) which is triggered by a change in the
Loss of Signal (LOS) and/or Driver Performance Monitor (DPM) bits. The Interrupt is cleared
when the interrupt condition no longer exists, and the host processor enables the respective bit in
the serial input data byte. Host mode also allows control of the serial data and receive data output
timing. The Clock Edge (CLKE) signal determines when these outputs are valid, relative to the
Serial Clock (SCLK) or RCLK as listed in

Table 3

The LXT300Z serial port is addressed by setting bit A4 in the Address/Command byte,
corresponding to address 16. The LXT300Z contains only a single output data register so no
complex chip addressing scheme is required. The register is accessed by causing the Chip Select
(CS) input to transition from High to Low. Bit 1 of the serial Address/Command byte provides
Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0
indicates a write operation.

Table 4

lists serial data output bit combinations for each status. Serial

data I/O timing characteristics are shown in the Test Specifications section.

2.4.2

Hardware Mode Operation (LXT300Z and LXT301Z)

In Hardware mode the transceiver is accessed and controlled through individual pins. With the
exception of the INT and CLKE functions, Hardware mode provides all the functions provided in
the Host mode. In the Hardware mode RPOS and RNEG outputs are valid on the rising edge of
RCLK. The LXT301Z operates in Hardware mode at all times.

LXT300Z Only: To operate in Hardware mode, MODE must be set Low. Equalizer Control signals
(EC1 through EC3) are input on the Interrupt, Serial Data In and Serial Data Out pins respectively.
Diagnostic control for Remote Loopback (RLOOP), Local Loopback (LLOOP), and Transmit All
Ones (TAOS) modes is provided through the individual pins used to control serial interface timing
in the Host mode.

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

Figure 4. 50% AMI Coding

Table 2. LXT300Z Serial Data Output Bits (See Figure 5)

Bit
D5

Bit
D6

Bit
D7

Status

Reset has occurred, or no program input.

TAOS is active.

Local Loopback is active.

TAOS and Local Loopback are active.

Remote Loopback is active.

DPM has changed state since last Clear DPM occurred.

LOS has changed state since last Clear LOS occurred.

LOS and DPM have both changed state since last Clear DPM and Clear LOS
occurred.

Table 3. Valid CLKE Settings

CLKE

Output

Clock

Valid Edge

Low

RPOS

RNEG

SDO

RCLK

SCLK

Rising

Falling

High

RPOS

RNEG

SDO

RCLK

SCLK

Falling

Rising

TTIP

Bit Cell

TRING

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

2.4.3

Diagnostic Mode Operation

2.4.3.1

Transmit All Ones

In Transmit All Ones (TAOS) mode, the TPOS and TNEG inputs to the transceiver are ignored.
The transceiver transmits a continuous stream of ones. TAOS can be commanded simultaneously
with Local Loopback, but is inhibited during Remote Loopback.

2.4.3.2

Remote Loopback

In Remote Loopback (RLOOP) mode, the transmit data and clock inputs (TPOS, TNEG and
TCLK) are ignored. The RPOS and RNEG outputs are looped back through the transmit circuits
and output on TTIP and TRING at the RCLK frequency. Receiver circuits are unaffected by the
RLOOP command and continue to output the RPOS, RNEG and RCLK signals received from the
twisted-pair line.

2.4.3.3

Local Loopback

In Local Loopback (LLOOP) mode, the receiver circuits are inhibited. The transmit data and clock
inputs (TPOS, TNEG and TCLK) are looped back onto the receive data and clock outputs (RPOS,
RNEG and RCLK) through the receive jitter attenuator. The transmitter circuits are unaffected by
the LLOOP command. The TPOS and TNEG inputs (or a stream of ones if the TAOS command is
active) will be transmitted normally.

LXT300Z Only: When used in this mode with a crystal, the transceiver can be used as a stand-alone
jitter attenuator.

Table 4. Equalizer Control Inputs

EC3

EC2

EC1

Line Length

Cable Loss

Application

Bit Rate

0 ~ 133 ft ABAM

133 ~ 266 ft ABAM

266 ~ 399 ft ABAM

399 ~ 533 ft ABAM

533 ~ 655 ft ABAM

0.6 dB

1.2 dB

1.8 dB

2.4 dB

3.0 dB

DSX-1

1.544 Mbps

ITU Recommendation G.703

2.048 Mbps

FCC Part 68, Option A

CSU

1.544 Mbps

1. Line length from transceiver to DSX-1 cross-connect point.
2. Maximum cable loss at 772 kHz.

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

3.2

LXT300Z Hardware Mode E1 Interface Application

Figure 7

shows a typical 2.048 Mbps E1 application. The LXT300Z is configured in Hardware

mode with a typical E1/CRC4 framer. Resistors are installed in line with the transmit transformer
for loading a 75

coaxial cable. The in-line resistors are not required for transmission on 120

shielded twisted-pair lines. As in the T1 application shown in

Figure 6

, this configuration is

illustrated with a crystal in place to enable the LXT300Z Jitter Attenuation Loop, and a single

Figure 6. Typical LXT300Z 1.544 Mbps T1 Application (Host Mode)

TO HOST CONTROLLER

T1 ESF

FRAMER

1.544 MHz

CLOCK

V+

LXP600A/602

CLAD

CLKI

FSI

CLKO

2.048 MHz

6.176 MHz

22 K

0 V

T1 LINE

RECEIVE

1 : 1 :1

1 : 2

1.544 MHz

T1 LINE

TRANSMIT

0.47

NON-

POLARIZED

CLKE

SCLK

SDO

SDI

INT

RGND

RV+

RRING

RTIP

MRING

MTIP

TRING

TV+

LXT300Z

TRANSCEIVER

200

TMSYNC

SDO

INT

SCLK

SDI

TFSYNC

TCLK

TPOS

TNEG

SPS

RNEG

RPOS

RCLK

MCLK

TCLK

TPOS

TNEG

MODE

RNEG

RPOS

RCLK

XTALIN

XTALOUT

DPM

LOS

TTIP

TGND

0.1

NOTE 1

NOTE 2

NOTE 1

THE LXT300Z IS COMPATIBLE WITH A WIDE
VARIETY OF DIGITAL FRAMING AND
SIGNALING DEVICES.

NOTE 2

WHEN LXT300Z IS CONNECTED TO THE
CROSS-CONNECT FRAME THROUGH A LOW
LEVEL MONITOR JACK, RECEIVE
TRANSFORMER SHOULD BE 1 : 2 : 2 TO
BOOST THE INPUT SIGNAL.

1.544 MHz

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

power supply bus. The hard-wired control lines for TAOS, LLOOP and RLOOP are individually
controllable, and the LLOOP and RLOOP lines are also tied to a single control for the Reset
function

Figure 7. Typical LXT300Z 75

E1 Application (Hardware Mode)

Table 5. LXT300Z Crystal Specifications (External)

Parameter

Frequency

6.176 MHz

8.192 MHz

Frequency stability

± 20 ppm @ 25 °C
± 25 ppm from -40 °C to 85 °C
(Ref 25 °C reading)

± 20 ppm @ 25 °C
± 25 ppm from -40 °C to +85 °C
(Ref 25 °C reading)

Pullability

CL = 11 pF to 18.7 pF, +

F = 175 to 195 ppm

CL = 18.7 pF to 34 pF, -

F = 175 to 195 ppm

CL = 11 pF to 18.7 pF, +

F = 95 to 115 ppm

CL = 18.7 pF to 34 pF, -

F = 95 to 115 ppm

Effective series
resistance

Maximum

Crystal cut

Resonance

Parallel

Maximum drive level

2.0 mW

Mode of operation

Fundamental

Crystal holder

HC49 (R3W),

= 7 pF maximum

= 17 fF typical

HC49 (R3W),

= 7 pF maximum

= 17 fF typical

V+

0 V

2.048 Mbps

RECEIVE

1:1:1

150

LXT300Z

TRANSCEIVER

220 k

E1/CRC4
FRAMER

100 k

10 k

+ 1

0.1

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

MCLK

TCLK

TPOS

TNEG

MODE

RNEG

RPOS

RCLK

XTALOUT

DPM

LOS

TTIP

TGND

TAOS

LLOOP

RLOOP

EC1

RGND

RV+

RRING

RTIP

MRING

MTIP

TRING

TV+

+ 68

150

XTALIN

2.048 MHz

Clock

V+

10 k

2.2

1:2

2.048 Mbps
TRANSMIT

0.47

NOTE 2

NOTE 1

NON-POLARIZED

EC2

EC3

NOTE 1

2.2

RESISTORS REQUIRED

ONLY FOR 75

COAXIAL CABLE.

NOT REQUIRED FOR
TRANSMISSION ONTO 120

CABLE.

NOTE 2

THE LXT300Z IS COMPATIBLE
WITH A WIDE VARIETY OF
FRAMING AND SIGNALING
DEVICES, INCLUDING THE
DS2181A, MT8979, AND R8070.

8.192 MHz

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

3.2.1

LXT301Z 1.544 Mbps T1 Interface Application

Figure 8

shows a typical 1.544 Mbps T1 application of the LXT301Z. The LXT301Z is shown with

a typical T1/ESF framer. The LXP600A Clock Adapter (CLAD) provides the 2.048 MHz system
backplane clock, locked to the recovered 1.544 MHz clock signal. The power supply inputs are tied
to a common bus with appropriate decoupling capacitors installed (68 µF on the transmit side, 1.0
µF and 0.1 µF on the receive side).

Figure 8. Typical LXT301Z 1.544 Mbps T1 Application

V+

0 V

T1 LINE

RECEIVE

1:1:1

200

LXT301Z

TRANSCEIVER

220 k

T1/ESF

FRAMER

100 k

10 k

0.1

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

MCLK

TCLK

TPOS

TNEG

GND

RNEG

RPOS

RCLK

N/C

DPM

LOS

TTIP

TGND

TAOS

LLOOP

RLOOP

EC1

RGND

RV+

RRING

RTIP

MRING

MTIP

TRING

TV+

+ 68

200

1 k

1.544 MHz

Clock

V+

10 k

1:2

1.544 Mbps
TRANSMIT

0.47

NOTE 1

NON-POLARIZED

EC2

EC3

LX600A / 602

CLAD

CLKI

FSI

CLKO

2.048 MHz

1.544 MHz

NOTE 1

THE LXT300Z IS COMPATIBLE
WITH A WIDE VARIETY OF
FRAMING AND SIGNALING
DEVICES.

E1.5i

V+

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

3.2.2

LXT301Z 2.048 Mbps E1 Interface Application

Figure 9

shows a typical 2.048 Mbps E1 application of the LXT301Z. The LXT301Z is shown with

a typical E1/CRC4 framer. Resistors are installed in line with the transmit transformer for loading a
75

coaxial cable. The in-line resistors are not required for transmission on 120

shielded

twisted-pair lines. As in the T1 application shown in

Figure 8

, this configuration is illustrated with

a single power supply bus. The hard-wired control lines for TAOS, LLOOP and RLOOP are
individually controllable, and the LLOOP and RLOOP lines are also tied to a single control for the
Reset function.

Figure 9. Typical LXT301Z 75

E1 Application

V+

0 V

2.048 Mbps

RECEIVE

1:1:1

150

LXT301Z

TRANSCEIVER

220 k

E1/CRC4
FRAMER

100 k

10 k

+ 1

0.1

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

MCLK

TCLK

TPOS

TNEG

GND

RNEG

RPOS

RCLK

N/C

DPM

LOS

TTIP

TGND

TAOS

LLOOP

RLOOP

EC1

RGND

RV+

RRING

RTIP

MRING

MTIP

TRING

TV+

+ 68

150

2.048 MHz

Clock

V+

10 k

2.2

1:2

2.048 Mbps

TRANSMIT

0.47

NOTE 1

NON-POLARIZED

EC2

EC3

NOTE 1

THE LXT301Z IS COMPATIBLE
WITH A WIDE VARIETY OF
FRAMING AND SIGNALING
DEVICES.

300zf08.vsd

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

4.0

Test Specifications

Note:

Table 6

through

Table 13

and

Figure 10

through

Figure 16

represent the performance specifications

of the LXT300Z/301Z and are guaranteed by test except, where noted, by design. The minimum
and maximum values listed in

Table 8

through

Table 13

are guaranteed over the recommended

operating conditions specified in

Table 7

Table 6. Absolute Maximum Ratings

Parameter

Sym

Min

Max

Units

DC supply (referenced to GND)

RV+, TV+

-0.3

6.0

Input voltage, any pin

RGND - 0.3

RV+ + 0.3

Input current, any pin

Iin

-10

Storage temperature

STG

-65

150

°C

Caution: Exceeding these values may cause permanent damage.

Caution: Functional operation under these conditions is not implied.

Caution: Exposure to maximum rating conditions for extended periods may affect device reliability.

1. Excluding RTIP and RRING which must stay between -6V and (RV+ + 0.3) V.
2. Transient currents of up to 100 mA will not cause SCR latch up. TTIP, TRING, TV+ and TGND can withstand a continuous

current of 100 mA.

Table 7. Recommended Operating Conditions

Parameter

Sym

Min

Typ

Max

Units

DC supply

RV+, TV+

4.75

5.0

5.25

Ambient operating temperature

-40

° C

1. TV+ must not exceed RV+ by more than 0.3 V.

Table 8. Electrical Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

High level input voltage

1,2

(pins 1-5, 10, 23-28)

2.0

Low level input voltage

1,2

(pins 1-5, 10, 23-28)

Vil

0.8

High level output voltage

1,2

(pins 6-8, 11, 12, 23, 25)

2.4

OUT

= -400

Low level output voltage

1,2

(pins 6-8, 11, 12, 23, 25)

0.4

OUT

= 1.6 mA

Input leakage current (pins 1-5, and 23-28)

-10

+10

Input leakage current (pins 9, 17, and 18)

-50

+50

Three-state leakage current

(pin 25)

-10

+10

Total power dissipation

700

100% ones density &
maximum line length
@ 5.25 V

1. Functionality of pins 23 through 28 depends on mode. See Host and Hardware mode functional descriptions.
2. Output drivers will output CMOS logic levels into CMOS loads.
3. Power dissipation while driving a 25

load over operating temperature range. Includes device and load. Digital input levels

are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

Table 9. Analog Characteristics

Parameter

Min

Typ

Max

Units

Test Conditions

AMI output pulse amplitudes

DSX-1

2.4

3.0

3.6

measured at the DSX

E1 (120

)

2.7

3.0

3.3

measured at line side

E1 (75

)

2.14

2.37

2.6

@ 772 kHz

Transmit amplitude variation with supply

2.5

Recommended output load at TTIP and TRING

RTIP to RRING

Driver output impedance

@ 10 kHz

Jitter added by the transmitter

10 Hz - 8 kHz

0.02

8 kHz - 40 kHz

0.025

10 Hz - 40 kHz

0.025

Broad Band

0.05

Output power levels

DS1 2 kHz BW

@ 772 kHz

12.6

17.9

dBm

@ 1544 kHz

-29.0

Positive to negative pulse imbalance

0.5

Sensitivity below DSX

(0 dB = 2.4 V)

13.6

500

Receiver input impedance

Loss of Signal threshold

0.3

Data decision threshold

DSX-1

% peak

Allowable consecutive zeros before LOS

160

175

190

Input jitter tolerance

10 Hz

1200

775 Hz

10 kHz - 100 kHz

0.4

Jitter attenuation curve corner frequency

Jitter attenuation

Jitter attenuation tolerance before FIFO Overflow

1. Typical values are measured at 25

C and are for design aid only; not guaranteed and not subject to production testing.

2. Not production tested but guaranteed by design and other correlation methods.
3. Input signal to TCLK is jitter-free.
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
5. Referenced to power in 2 kHz band.
6. With a maximum of 6 dB of cable attenuation.

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

Figure 11. LXT300Z Typical Receive Jitter Transfer Performance

Table 10. LXT300Z Receiver Timing Characteristics (See Figure 12)

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Receive clock duty cycle

RCLKd

Receive clock pulse width

DSX-1

324

244

RPOS/RNEG to RCLK rising
setup time

DSX-1

SUR

274

SUR

194

RCLK rising to RPOS/RNEG
hold time

DSX-1

274

194

1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.

20 dB

1 Hz

Typical LXT300Z Performance

0 dB

-10 dB

-20 dB

-30 dB

-40 dB

-60 dB

10 Hz

100 Hz

1 kHz

10 kHz

100 kHz

1450 Hz

20 Hz

0.5 dB / 3 Hz

0.5 dB / 40 Hz

AT&T 62411 Template Slope
equivalent to 20 dB per decade

ITU G.735 Template Slope
equivalent to 20 dB per decade

AT&T 62411 Template Slope
equivalent to 40 dB per decade

Frequency

i
n

19.5 dB /
100 Hz

19.5 dB /
400 Hz

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

Figure 12. LXT300Z Receive Clock Timing Diagram

Table 11. LXT301Z Receive Timing Characteristics (See Figure 13)

Parameter

Sym

Min

Typ

Max

Units

Test

Conditions

Receive clock duty cycle

DSX-1

RCLKd

Receive clock pulse width

DSX-1

594

648

702

447

488

529

Receive clock pulse width High

DSX-1

PWH

324

PWH

244

Receive clock pulse width Low

DSX-1

PWL

270

324

378

PWL

203

244

285

RPOS/RNEG to RCLK rising
setup time

DSX-1

SUR

270

SUR

203

RCLK rising to RPOS/RNEG hold
time

DSX-1

270

203

1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Max and Min RCLK duty cycles

are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz, 0.2 UI clock displacement for 2.048 MHz).

PWH

PWL

SUR

RCLK

RPOS

RNEG

RPOS

RNEG

SUR

Host mode

CLKE = 1

Host mode

CLKE = 0, &

H/W mode

LXT300Z/LXT301Z -- Advanced T1/E1 Short-Haul Transceivers

Datasheet

Figure 13. LXT301Z Receive Clock Timing Diagram

Table 12. LXT300Z/301Z Master Clock and Transmit Timing Characteristics

(See Figure 14)

Parameter

Sym

Min

Typ

Max

Units

Master clock frequency

DSX-1

MCLK

1.544

MHz

MCLK

2.048

MHz

Master clock tolerance

MCLKt

±100

ppm

Master clock duty cycle

MCLKd

Crystal frequency
(LXT300Z only)

DSX-1

6.176

MHz

8.192

MHz

Transmit clock frequency

DSX-1

TCLK

1.544

MHz

TCLK

2.048

MHz

Transmit clock tolerance

TCLKt

±50

ppm

Transmit clock duty cycle

TCLKd

TPOS/TNEG to TCLK setup time

SUT

TCLK to TPOS/TNEG hold time

1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
2. Not production tested but guaranteed by design and other correlation methods.

Figure 14. LXT300Z/301Z Transmit Clock Timing Diagram

PWL

PWH

SUR

RCLK

RPOS

RNEG

SUT

TCLK

TPOS

TNEG

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

Table 13. LXT300Z Serial I/O Timing Characteristics (See Figure 15 and Figure 16)

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Rise/fall time - any digital output

100

Load 1.6 mA, 50 pF

SDI to SCLK setup time

SCLK to SDI hold time

CDH

SCLK Low time

240

SCLK High time

240

SCLK rise and fall time

, t

CS to SCLK setup time

SCLK to CS hold time

CCH

CS inactive time

CWH

250

SCLK to SDO valid

CDV

200

SCLK falling edge or CS rising edge to SDO
high Z

CDZ

100

1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.

Figure 15. LXT300Z Serial Data Input Timing Diagram

CWH

CCH

SCLK

SDI

LSB

CDH

LSB

CDH

MSB

CONTROL BYTE

DATA BYTE

Advanced T1/E1 Short-Haul Transceivers -- LXT300Z/LXT301Z

Datasheet

5.0

Mechanical Specifications

Figure 17. Package Specifications

28-pin Plastic Dual In-Line Package

Extended Temperature Range (-40 °C to 85 °C)

Part Number LXT300ZNE

Part Number LXT301ZNE

28-pin Plastic Leaded Chip Carrier

Extended Temperature Range (-40 °C to 85 °C)

Part Number LXT300ZPE

Part Number LXT301ZPE

Dim

Inches

Millimeters

Min

Max

Min

Max

0.250

6.350

0.125

0.195

3.175

4.953

0.014

0.022

0.356

0.559

0.030

0.070

0.762

1.778

1.380

1.565

35.052

39.751

0.600

0.625

15.240

15.875

0.485

0.580

12.319

14.732

0.100

BSC

(nominal)

2.540

BSC

(nominal)

0.600

BSC

(nominal)

15.240

BSC

(nominal)

0.700

17.780

0.115

0.200

2.921

5.080

1. BSC--Basic Spacing between Centers.

Dim

Inches

Millimeters

Min

Max

Min

Max

0.165

0.180

4.191

4.572

0.090

0.120

2.286

3.048

0.062

0.083

1.575

2.108

.050

BSC

(nominal)

1.27

BSC

(nominal)

0.026

0.032

0.660

0.813

0.485

0.495

12.319

12.573

0.450

0.456

11.430

11.582

0.013

0.021

0.330

0.533

1. BSC--Basic Spacing between Centers.

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