Untitled Document
LXT351
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Datasheet
The LXT351 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul
applications. The LXT351 is software switchable between T1 and E1 operation, and offers pulse
equalization settings for all short-haul T1 and E1 line interface (LIU) applications.
The LXT351 offers an Intel/Motorola compatible parallel port for microprocessor control. The
device incorporates advanced crystal-less digital jitter attenuation in either the transmit or
receive data path starting at 3 Hz. B8ZS/HDB3 encoding/decoding and unipolar or bipolar data
I/O are selectable. Loss of signal monitoring and a variety of diagnostic loopback modes can
also be selected.
Applications
Product Features
s
SONET/SDH tributary interfaces
s
Digital cross connects
s
Public/private switching trunk line
interfaces
s
Microwave transmission systems
s
Fully integrated transceivers for Short-Haul
T1 or E1 interfaces
s
Crystal-less digital jitter attenuation
-- Select either transmit or receive path
-- No crystal or high speed external clock
required
s
Meet or exceed specifications in ANSI
T1.403 and T1.408; ITU I.431, G.703,
G.736, G.775 and G.823; ETSI 300-166
and 300-233; and AT&T Pub 62411
s
Supports 75
(E1 coax), 100
(T1
twisted-pair) and 120
(E1 twisted-pair)
applications
s
Fully restores the received signal after
transmission through a cable with
attenuation of 18dB, at 1024 kHz
s
Five pulse equalization settings for T1
short-haul applications
s
Transmit/receive performance monitors
with Driver Fail Monitor Open (DFM) and
Loss of Signal (LOS) outputs
s
Selectable unipolar or bipolar data I/O and
B8ZS/HDB3 encoding/decoding
s
QRSS generator/detector for testing or
monitoring
s
Output short circuit current limit protection
s
Local, remote and analog loopback
capability
s
Compatible with Intel's LXT360/361 T1/
E1 long haul/short haul transceiver
(Universal LIU)
s
Multiple register parallel interface
compatible with both Intel and Motorola
microprocessors
s
Available in 28-pin PLCC and 44-pin
PQFP packages
As of January 15, 2001, this document replaces the Level One document
Order Number: 249030-001
LXT351 -- Integrated T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation.
January 2001
Datasheet
Information in this document is provided in connection with Intel
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT351 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
3
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Contents
1.0
Pin Assignments and Signal Descriptions
...................................................... 8
1.1
Mode Dependent Signals ...................................................................................... 9
2.0
Functional Description
........................................................................................... 13
2.1
Initialization.......................................................................................................... 13
2.1.1
Reset Operation ..................................................................................... 13
2.2
Transmitter .......................................................................................................... 13
2.2.1
Transmit Digital Data Interface ...............................................................13
2.2.2
Transmit Monitoring................................................................................ 14
2.2.3
Transmit Drivers ..................................................................................... 14
2.2.4
Transmit Idle Mode................................................................................. 14
2.2.5
Transmit Pulse Shape ............................................................................14
2.3
Receiver .............................................................................................................. 15
2.3.1
Receive Data Recovery.......................................................................... 15
2.4
Jitter Attenuation ................................................................................................. 15
2.5
Diagnostic Mode Operation................................................................................. 16
2.5.1
Loopback Modes .................................................................................... 16
2.5.1.1 Local Loopback ......................................................................... 16
2.5.1.2 Analog Loopback....................................................................... 18
2.5.1.3 Remote Loopback .....................................................................18
2.5.1.4 Dual Loopback .......................................................................... 19
2.5.2
Internal Pattern Generation .................................................................... 19
2.5.2.1 Transmit All Ones ...................................................................... 19
2.5.2.2 Quasi-Random Signal Source (QRSS) .....................................20
2.5.3
Error Insertion and Detection ................................................................. 21
2.5.3.1 Bipolar Violation Insertion (INSBPV) ......................................... 21
2.5.3.2 Logic Error Insertion (INSLER)..................................................21
2.5.3.3 Bipolar Violation Detection (BPV).............................................. 21
2.5.3.4 HDB3 Code Violation Detection (CODEV) ................................ 21
2.5.3.5 HDB3 Zero Substitution Violation Detection (ZEROV) .............. 21
2.5.4
Alarm Condition Monitoring .................................................................... 22
2.5.4.1 Loss of Signal ............................................................................22
2.5.4.2 Alarm Indication Signal Detection ............................................. 22
2.5.4.3 Driver Failure Open Mode ......................................................... 22
2.5.4.4 Elastic Store Overflow/Underflow .............................................. 22
2.5.4.5 Built-In Self Test ........................................................................ 23
2.6
Parallel Microprocessor Interface........................................................................ 23
2.6.1
Interrupt Handling................................................................................... 23
3.0
Register Definitions
................................................................................................. 24
4.0
Application Information
.........................................................................................29
4.1
Transmit Return Loss .......................................................................................... 29
4.2
Transformer Data ................................................................................................ 29
4.3
Application Circuit................................................................................................ 29
4.4
Line Protection .................................................................................................... 29
4.4.1
LXT351 Application Circuit .....................................................................31
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
4
Datasheet
5.0
Test Specifications
.................................................................................................. 33
6.0
Mechanical Specifications
................................................................................... 45
Figures
1
LXT351 Block Diagram ......................................................................................... 7
2
LXT351 Pin Assignments...................................................................................... 8
3
50% Duty Cycle Coding ...................................................................................... 14
4
Local Loopback ................................................................................................... 16
5
TAOS with LLOOP .............................................................................................. 17
6
Analog Loopback ................................................................................................ 18
7
Remote Loopback ............................................................................................... 19
8
Dual Loopback .................................................................................................... 19
9
TAOS Data Path ................................................................................................. 20
10
QRSS Mode ........................................................................................................ 20
11
Typical T1/E1 LXT351 Application ...................................................................... 32
12
2.048 Mbps E1 Pulse (See
Table 24
)................................................................. 35
13
1.544 Mbps T1 Pulse, DSX-1 (See
Table 25
) ..................................................... 36
14
Transmit Clock Timing ........................................................................................ 37
15
Receive Clock Timing ......................................................................................... 38
16
Intel Address/Data Bus Timing............................................................................ 40
17
Motorola Address/Data Bus Timing .................................................................... 41
18
Typical T1 Jitter Tolerance at 36 dB ................................................................... 41
19
Typical E1 Jitter Tolerance at 43 dB ................................................................... 42
20
Typical E1 Jitter Attenuation ............................................................................... 43
21
Typical T1 Jitter Attenuation................................................................................ 44
22
Plastic Leaded Chip Carrier Package Specifications .......................................... 45
23
Plastic Quad Flat Package Specifications........................................................... 46
Datasheet
5
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Tables
1
LXT351 Clock and Data Pin Assignments by Mode1............................................ 9
2
LXT351 Processor Interface Pins.......................................................................... 9
3
LXT351 Signal Descriptions ................................................................................ 10
4
Diagnostic Mode Summary ................................................................................. 16
5
Register Addresses ............................................................................................. 24
6
Register and Bit Summary ..................................................................................24
7
Control Register #1 Read/Write, Address (A7-A0) = x010000x .......................... 25
8
Equalizer Control Input Settings......................................................................... 25
9
Control Register #2 Read/Write, Address (A7-A0) = x010001x .......................... 25
10
Control Register #3 Read/Write, Address (A7-A0) = x010010x .......................... 26
11
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x.................... 26
12
Transition Status Register Read Only, Address (A7-A0) = x010100x................. 27
13
Performance Status Register Read Only, Address (A7-A0) = x010101x ............ 27
14
Control Register #4 Read/Write, Address (A7-A0) = x010111x .......................... 28
15
E1 Transmit Return Loss Requirements ............................................................. 29
16
Transmit Return Loss (2.048 Mbps).................................................................... 30
17
Transmit Return Loss (1.544 Mbps).................................................................... 30
18
Transformer Specifications..................................................................................30
19
Recommended Transformers.............................................................................. 31
20
Absolute Maximum Ratings................................................................................. 33
21
Recommended Operating Conditions ................................................................. 33
22
DC Electrical Characteristics............................................................................... 34
23
Analog Characteristics ........................................................................................ 34
24
2.048 Mbps E1 Pulse Mask Specifications ........................................................ 35
25
1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications........................36
26
Master and Transmit Clock Timing Characteristics for T1 Operation
(See
Figure 14
) ................................................................................................... 37
27
Master and Transmit Clock Timing Characteristics for E1 Operation
(See
Figure 14
) ................................................................................................... 37
28
Receive Timing Characteristics for T1 Operation (See
Figure 15
)...................... 38
29
Receive Timing Characteristics for E1 Operation (See
Figure 15
) ..................... 38
30
20 MHz Intel Bus Parallel I/O Timing Characteristics (See
Figure 16
)................ 39
31
16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See
Figure 17
) ... 40
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