Document Outline
- 1.0 Features
- 2.0 Pin Assignments and Signal Description
- 3.0 Functional Description
- 4.0 Register Descriptions
- Table 6. Serial and Parallel Port Register Addresses
- Table 7. Register Bit Names
- Table 8. ID Register, ID (00H)
- Table 9. Analog Loopback Register, ALOOP (01H)
- Table 10. Remote Loopback Register, RLOOP (02H)
- Table 11. TAOS Enable Register, TAOS (03H)
- Table 12. LOS Status Monitor Register, LOS (04H)
- Table 13. DFM Status Monitor Register, DFM (05H)
- Table 14. LOS Interrupt Enable Register, LIE (06H)
- Table 15. DFM Interrupt Enable Register, DIE (07H)
- Table 16. LOS Interrupt Status Register, LIS (08H)
- Table 17. DFM Interrupt Status Register, DIS (09H)
- Table 18. Software Reset Register, RES (0AH)
- Table 19. Performance Monitoring Register, MON (0BH)
- Table 20. Digital Loopback Register, DL (0CH)
- Table 21. LOS/AIS Criteria Register, LCS (0DH)
- Table 22. Automatic TAOS Select Register, ATS (0EH)
- Table 23. Global Control Register, GCR (0FH)
- Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H)
- Table 25. Pulse Shaping Data Register, PSDAT (11H)
- Table 26. Output Enable Register, OER (12H)
- Table 27. AIS Status Monitor Register, AIS (13H)
- Table 28. AIS Interrupt Enable Register, AISIE (14H)
- Table 29. AIS Interrupt Status Register, AISIS (15H)
- 5.0 JTAG Boundary Scan
- 6.0 Test Specifications
- 7.0 Mechanical Specifications
LXT386
QUAD T1/E1/J1 Transceiver
Datasheet
The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both
1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers
and four independent transmitters in a single PBGA-160 or LQFP-100 package.
The transmit drivers provide low impedance independent of the transmit pattern and supply
voltage variations.The LXT386 transmits shaped waveforms meeting G.703 and T1.102
specifications. The LXT386 exceeds the latest transmit return loss specifications, such as ETSI
ETS-300166.
The LXT386's differential receiver architecture provides high noise interference margin and is
able to work with up to 12 dB of cable attenuation. The digital clock recovery PLL and jitter
attenuator are referenced to a low frequency 1.544 MHz or 2.048 MHz clock.
The LXT386 incorporates an advanced crystal-less jitter attenuator switchable between the
receive and transmit path. The jitter attenuation performance meets the latest international
specifications such as CTR12/13. The jitter attenuation performance was optimized for
Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/SDH) applications.
The LXT386 can be configured as a 3 channel transceiver with G.772 compliant non intrusive
protected monitoring points. It uses a single 3.3V supply for low power consumption.
The constant delay characteristic of the LXT386 JA as well as a power down mode of all
transmitters allows the implementation of Hitless Protection Switching (HPS) applications
without the use of relays.
Applications
s
SONET/SDH tributary interfaces
s
Digital cross connects
s
Public/private switching trunk line
interfaces
s
Microwave transmission systems
s
M13, E1-E3 MUX
As of January 15, 2001, this document replaces the Level One document
Order Number:
249253-001
LXT386 -- QUAD T1/E1/J1 Transceiver Font>.
January 2001
Datasheet
Information in this document is provided in connection with Intel
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT386 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
3
QUAD T1/E1/J1 Transceiver -- LXT386
Contents
1.0
Features
......................................................................................................................... 7
2.0
Pin Assignments and Signal Description
........................................................ 9
3.0
Functional Description
........................................................................................... 22
3.1
Initialization.......................................................................................................... 22
3.1.1
Reset Operation ..................................................................................... 22
3.2
Receiver .............................................................................................................. 23
3.2.1
Loss of Signal Detector .......................................................................... 24
3.2.1.1 E1 Mode .................................................................................... 24
3.2.1.2 T1 Mode .................................................................................... 24
3.2.1.3 Data Recovery Mode................................................................. 24
3.2.2
Alarm Indication Signal (AIS) Detection ................................................. 24
3.2.2.1 E1 Mode .................................................................................... 25
3.2.2.2 T1 Mode .................................................................................... 25
3.2.3
In Service Code Violation Monitoring ..................................................... 25
3.3
Transmitter .......................................................................................................... 25
3.3.1
Transmit Pulse Shaping ......................................................................... 26
3.3.1.1 Hardware Mode ......................................................................... 26
3.3.1.2 Host Mode ................................................................................. 26
3.3.2
Transmit Pulse Shaping ......................................................................... 27
3.3.2.1 Output Driver Power Supply ...................................................... 27
3.3.2.2 Power Sequencing .................................................................... 27
3.4
Driver Failure Monitor.......................................................................................... 27
3.5
Line Protection .................................................................................................... 28
3.6
Jitter Attenuation ................................................................................................. 30
3.7
Loopbacks ........................................................................................................... 31
3.7.1
Analog Loopback.................................................................................... 31
3.7.2
Digital Loopback..................................................................................... 32
3.7.3
Remote Loopback ..................................................................................32
3.7.4
Transmit All Ones (TAOS)...................................................................... 32
3.8
G.772 Performance Monitoring ........................................................................... 33
3.9
Hitless Protection Switching (HPS) .....................................................................34
3.10
Operation Mode Summary ..................................................................................34
3.11
Interfacing with 5V logic ...................................................................................... 35
3.12
Parallel Host Interface .........................................................................................35
3.12.1 Motorola Interface ..................................................................................35
3.12.2 Intel Interface.......................................................................................... 36
3.13
Interrupt Handling................................................................................................ 36
3.13.1 Interrupt Enable ...................................................................................... 36
3.13.2 Interrupt Clear ........................................................................................ 37
3.14
Serial Host Mode................................................................................................. 37
4.0
Register Descriptions
............................................................................................. 38
5.0
JTAG Boundary Scan
............................................................................................. 45
5.1
Overview ............................................................................................................. 45
5.2
Architecture ......................................................................................................... 45
LXT386 -- QUAD T1/E1/J1 Transceiver
4
Datasheet
5.3
TAP Controller..................................................................................................... 45
5.4
JTAG Register Description.................................................................................. 47
5.4.1
Boundary Scan Register (BSR).............................................................. 48
5.5
Device Identification Register (IDR) .................................................................... 50
5.5.1
Bypass Register (BYR) .......................................................................... 50
5.5.2
Analog Port Scan Register (ASR) .......................................................... 50
5.5.3
Instruction Register (IR) ......................................................................... 51
6.0
Test Specifications
.................................................................................................. 53
6.1
Recommendations and Specifications ................................................................ 75
7.0
Mechanical Specifications
................................................................................... 76
Figures
1
LXT386 Block Diagram ......................................................................................... 7
2
LXT386 Detailed Block Diagram ........................................................................... 8
3
LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Pack-
age Markings......................................................................................................... 9
4
LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments........................... 10
5
Pullup Resistor to RESET ................................................................................... 23
6
50% AMI Encoding.............................................................................................. 26
7
External Transmit/Receive Line Circuitry ............................................................ 29
8
Jitter Attenuator Loop.......................................................................................... 31
9
Analog Loopback ................................................................................................ 31
10
Digital Loopback.................................................................................................. 32
11
Remote Loopback ............................................................................................... 32
12
TAOS Data Path ................................................................................................. 33
13
TAOS with Analog Loopback .............................................................................. 33
14
Serial Host Mode Timing ..................................................................................... 37
15
LXT386 JTAG Architecture ................................................................................. 45
16
JTAG State Diagram ........................................................................................... 47
17
Analog Test Port Application ............................................................................... 52
18
Transmit Clock Timing Diagram .......................................................................... 59
19
Receive Clock Timing Diagram ........................................................................... 60
20
JTAG Timing ....................................................................................................... 61
21
Non-Multiplexed Intel Mode Read Timing ........................................................... 62
22
Multiplexed Intel Read Timing ............................................................................. 63
23
Non-Multiplexed Intel Mode Write Timing ........................................................... 64
24
Multiplexed Intel Mode Write Timing ................................................................... 65
25
Non-Multiplexed Motorola Mode Read Timing .................................................... 66
26
Multiplexed Motorola Mode Read Timing............................................................ 67
27
Non-Multiplexed Motorola Mode Write Timing .................................................... 68
28
Multiplexed Motorola Mode Write Timin .............................................................. 69
29
Serial Input Timing .............................................................................................. 70
30
Serial Output Timing ........................................................................................... 70
31
E1, G.703 Mask Templates................................................................................. 71
32
T1, T1.102 Mask Templates ............................................................................... 72
33
LXT386 Jitter Tolerance Performance ................................................................ 73
34
Jitter Transfer Performance ................................................................................ 74
Datasheet
5
QUAD T1/E1/J1 Transceiver -- LXT386
35
Output Jitter for CTR12/13 applications .............................................................. 75
36
60 Plastic Ball Grid Array (PBGA) Package Dimensions .................................... 76
37
100 Pin Low Quad Flat Packages (LQFP) Dimensions ...................................... 77
Tables
1
Pin Assignments and Signal Descriptions........................................................... 11
2
Line Length Equalizer Inputs............................................................................... 27
3
Jitter Attenuation Specifications .......................................................................... 30
4
Operation Mode Summary ..................................................................................34
5
Microprocessor Parallel Interface Selection ........................................................ 35
6
Serial and Parallel Port Register Addresses ....................................................... 38
7
Register Bit Names ............................................................................................. 38
8
ID Register, ID (00H)........................................................................................... 39
9
Analog Loopback Register, ALOOP (01H).......................................................... 39
10
Remote Loopback Register, RLOOP (02H) ........................................................ 40
11
TAOS Enable Register, TAOS (03H) .................................................................. 40
12
LOS Status Monitor Register, LOS (04H) ........................................................... 40
13
DFM Status Monitor Register, DFM (05H) .......................................................... 40
14
LOS Interrupt Enable Register, LIE (06H)........................................................... 40
15
DFM Interrupt Enable Register, DIE (07H).......................................................... 40
16
LOS Interrupt Status Register, LIS (08H)............................................................ 41
17
DFM Interrupt Status Register, DIS (09H)........................................................... 41
18
Software Reset Register, RES (0AH).................................................................. 41
19
Performance Monitoring Register, MON (0BH)................................................... 41
20
Digital Loopback Register, DL (0CH) .................................................................. 41
21
LOS/AIS Criteria Register, LCS (0DH)................................................................ 41
22
Automatic TAOS Select Register, ATS (0EH)..................................................... 42
23
Global Control Register, GCR (0FH)................................................................... 42
24
Pulse Shaping Indirect Address Register, PSIAD (10H) .....................................43
25
Pulse Shaping Data Register, PSDAT (11H) ...................................................... 43
26
Output Enable Register, OER (12H) ................................................................... 43
27
AIS Status Monitor Register, AIS (13H) .............................................................. 43
28
AIS Interrupt Enable Register, AISIE (14H) ........................................................ 44
29
AIS Interrupt Status Register, AISIS (15H) ......................................................... 44
30
TAP State Description .........................................................................................46
31
Device Identification Register (IDR) .................................................................... 50
32
Analog Port Scan Register (ASR) ....................................................................... 51
33
Instruction Register (IR) ...................................................................................... 51
34
Absolute Maximum Ratings................................................................................. 53
35
Recommended Operating Conditions ................................................................. 53
36
DC Characteristics .............................................................................................. 54
37
E1 Transmit Transmission Characteristics.......................................................... 55
38
E1 Receive Transmission Characteristics........................................................... 55
39
T1 Transmit Transmission Characteristics .......................................................... 56
40
T1 Receive Transmission Characteristics ........................................................... 57
41
Jitter Attenuator Characteristics .......................................................................... 58
42
Analog Test Port Characteristics......................................................................... 59
43
Transmit Timing Characteristics.......................................................................... 59
44
Receive Timing Characteristics........................................................................... 60
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