LXT6251A
21 E1 SDH Mapper
Datasheet
The LXT6251A 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH
signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data,
while the SDH side uses a standard Telecom bus interface. Further processing by the companion
LXT6051 Overhead Terminator chip creates the final STM-0 or STM-1 signal. One mapper
provides complete processing of 21 E1s in STM-0, while three mappers can process 63 E1s in
STM-1.
The LXT6251A is compliant with the latest releases of ITU-T G.703 and G.707. It provides all
the alarm and control features to easily implement the multiplexer specified in ITU-T G.783.
Applications
Product Features
n
21 or 63 E1 Terminal or ADM SDH
Multiplexer
n
Digital Cross Connect System
n
Digital Loop Carrier Systems (NGDLC)
n
Microwave Radio System
n
Maps and Demaps 21 E1 signals between
PDH and SDH networks via VC-12
asynchronous mapping.
n
Multiplexes the 21 VC-12 signals into
seven interleaved TUG-2 structures for
STM-0 or a TUG-3 structure for STM-1
applications.
n
Configurable as a flexible Add/Drop
Multiplexer for up to 21 E1 tributaries, with
each E1 I/O port assignable to any TU time
slot within an AU-3 or TUG-3.
n
Performs VC-12 path overhead processing
for all 21 VC-12s, including V5, J2 Path
Trace, and K4 Enhanced RDI.
n
Records TU pointer alarms (TU-AIS, TU-
LOP), BIP-2 and REI error counts, TIM
and PLM alarms, and all other V5 POH
alarms for all 21 tributaries.
n
NRZ Data and Clock interface for E1
tributary access.
n
Microprocessor/SEMF interface to set
Signal Label, J2 Path Trace, access alarms
and counters
n
Low power CMOS technology with 3.3V
core and 5V I/O, available in PQFP-208
package.
n
IEEE 1149.1 (JTAG) support.
As of January 15, 2001, this document replaces the Level One document
Order Number: 249300-001
LXT6251 21 E1 SDH Mapper Datasheet.
January 2001
Datasheet
Information in this document is provided in connection with Intel
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT6251A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
3
21 E1 SDH Mapper -- LXT6251A
Contents
1.0
Block Diagram
............................................................................................................. 7
2.0
Pin Assignments and Signal Descriptions
...................................................... 8
3.0
Functional Description
........................................................................................... 16
3.1
Introduction.......................................................................................................... 16
3.2
Receive Section, Terminal Mode ........................................................................ 16
3.2.1
Receive Alarms ...................................................................................... 17
3.2.1.1 Parity Alarm ............................................................................... 17
3.2.1.2 Loss of Multiframe .....................................................................17
3.3
High Order Path Adaptation ................................................................................ 18
3.3.1
Alarms and Status ..................................................................................18
3.3.1.1 TU-AIS....................................................................................... 18
3.3.1.2 TU Loss of Pointer (LOP) .......................................................... 19
3.4
Low Order Path Termination ............................................................................... 19
3.4.1
V5 Processing ........................................................................................ 19
3.4.1.1 BIP-2 Errors (V5, bits 1,2) ......................................................... 19
3.4.1.2 REI Detection (V5, bit 3)............................................................ 20
3.4.1.3 RFI Detection (V5, bit 4) ............................................................ 20
3.4.1.4 Signal Label Mismatch (V5, bits 5-7)......................................... 20
3.4.1.5 Unequipped Detection (V5, bits 5-7) ......................................... 21
3.4.1.6 VC-AIS Detection (V5, bits 5-7)................................................. 21
3.4.1.7 RDI Detection (V5, bit 8) ........................................................... 21
3.4.2
J2 Processing .........................................................................................21
3.4.2.1 J2 Memory Access .................................................................... 22
3.4.2.2 CRC-7 Error .............................................................................. 22
3.4.2.3 Trace Identifier Mismatch .......................................................... 23
3.4.3
N2 Processing ........................................................................................ 23
3.4.4
K4 Processing ........................................................................................ 23
3.4.4.1 Enhanced RDI ........................................................................... 23
3.4.5
Summary of Alarms causing E1 AIS ...................................................... 23
3.4.5.1 TU-AIS Alarm ............................................................................24
3.4.5.2 TU-LOP Alarm ........................................................................... 24
3.4.5.3 Signal Label Mismatch .............................................................. 24
3.4.5.4 Unequipped Alarm.....................................................................24
3.4.5.5 J2 Path Label Mismatch ............................................................ 24
3.5
Low Order Path Adaptation ................................................................................. 24
3.5.1
Desynchronizer ...................................................................................... 24
4.0
Transmit Section, Terminal Mode
.....................................................................26
4.1
Low Order Path Adaptation ................................................................................. 26
4.2
Low Order Path Termination ............................................................................... 26
4.2.1
V5 Processing ........................................................................................ 26
4.2.1.1 BIP-2 .........................................................................................26
4.2.1.2 REI Bit ....................................................................................... 26
4.2.1.3 RFI Bit ....................................................................................... 27
4.2.1.4 Signal Label............................................................................... 27
4.2.1.5 RDI Bit ....................................................................................... 27
LXT6251A -- 21 E1 SDH Mapper
4
Datasheet
4.2.2
J2 Processing......................................................................................... 27
4.2.2.1 J2 Memory Access .................................................................... 28
4.2.3
K4 Processing ........................................................................................ 28
4.2.4
N2 Processing ........................................................................................ 28
4.3
High Order Path Adaptation ................................................................................ 29
5.0
Add/Drop Configuration
........................................................................................ 30
5.1
ADM Receive ...................................................................................................... 30
5.2
ADM Transmit ..................................................................................................... 30
5.2.1
Data Pass-Through ................................................................................ 31
5.2.1.1 PTSOH ...................................................................................... 31
5.2.1.2 PTTUGx .................................................................................... 32
5.2.2
MTBDATA Drive Enable......................................................................... 32
6.0
Application Information
......................................................................................... 34
6.1
Port Mapping Configuration ................................................................................ 34
6.2
Telecom Bus Interface ........................................................................................ 35
6.2.1
Multiplexer Telecom Bus, Terminal Mode .............................................. 35
6.2.2
Multiplexer Telecom Bus, ADM Mode .................................................... 36
6.2.3
MTBDATA Output Enable ...................................................................... 36
6.2.4
Demultiplexer Telecom Bus ................................................................... 37
6.2.5
Telecom Bus Timing .............................................................................. 37
6.3
Serial/Remote Alarm Processing Port................................................................. 40
7.0
Test Specifications
.................................................................................................. 42
8.0
Microprocessor Interface & Register Definitions
....................................... 50
8.1
Microprocessor Interface..................................................................................... 50
8.1.1
Intel Interface ......................................................................................... 50
8.1.2
Motorola Interface .................................................................................. 50
8.2
Interrupt Handling................................................................................................ 51
8.2.1
Interrupt Sources.................................................................................... 51
8.2.1.1 Interrupt Identification................................................................ 51
8.2.2
Interrupt Enables .................................................................................... 51
8.2.3
Interrupt Clearing ................................................................................... 52
8.2.4
UpdateEn Configuration Bit.................................................................... 52
8.3
Register Address Map......................................................................................... 52
8.3.1
Counter Access ...................................................................................... 53
8.3.2
Register Notations and Definitions ......................................................... 53
8.4
Configuration Registers....................................................................................... 55
8.4.1
GLOB_CONF--Global Configuration (000H)......................................... 55
8.4.2
TADD_CONF--Transmit Add Configuration (003001H) ...................... 56
8.4.3
TU_TS_CONF--TU Time Slot Configuration (161175H)..................... 57
8.4.4
SIGLA_SET--Signal Label Setting (xEH) .............................................. 57
8.4.5
J2_MRST--J2 Memory Reset (008H).................................................... 57
8.4.6
J2_ESDATA--J2 Expected String Data (xCH) ...................................... 58
8.4.7
J2_TSDATA--J2 Transmit String Data (xFH) ........................................ 58
8.4.8
ERRI_CONF--Error Insert Configuration (xDH) .................................... 58
8.4.9
INT_CONF--Interrupt Configuration Register (00BH) ........................... 59
8.4.10 CHIP_ID--Chip Identification Number (00AH)....................................... 59
8.5
Interrupt Registers............................................................................................... 60
Datasheet
5
21 E1 SDH Mapper -- LXT6251A
8.5.1
GLOB_INTS--Global Interrupt Source (00CH)...................................... 60
8.5.2
TRIB_ISRC--Tributary Interrupt Source Identification (00F00DH) ...... 60
8.5.3
TRIB_INT--Tributary Interrupt (x1x0H)................................................ 61
8.5.4
TRIB_INTE--Tributary Interrupt Enable (x5x4H) ................................. 62
8.6
Status and Control Registers .............................................................................. 63
8.6.1
TRIB_STA--Tributary Status (x3x2H)..................................................63
8.6.2
BIP2_ERRCNT--BIP2 Error Counter (x7x6H) .....................................63
8.6.3
REI_CNT--Remote Error Indication (REI) Counter (x9x8H)................ 64
8.6.4
K4_STA--K4 Status (xAH).....................................................................64
8.6.5
V5_STA--V5 Status Register (xBH) ...................................................... 64
9.0
Testability Modes
..................................................................................................... 66
9.1
IEEE 1149.1 Boundary Scan Description............................................................ 66
9.1.1
Instruction Register and Definitions........................................................ 67
9.1.1.1 EXTEST (`b00) .......................................................................... 67
9.1.1.2 SAMPLE/PRELOAD (`b01) ....................................................... 68
9.1.1.3 BYPASS (`b11) .......................................................................... 68
9.1.1.4 IDCODE (`b10) .......................................................................... 68
9.1.2
Boundary Scan Register ........................................................................ 68
10.0
Package Specification
............................................................................................ 75
11.0
Glossary
....................................................................................................................... 76
Figures
1
LXT6251A Block Diagram ..................................................................................... 7
2
LXT6251A Pin Assignments.................................................................................. 8
3
LXT6251A Block Diagram ................................................................................... 17
4
V1/V2 Pointer Diagram........................................................................................ 18
5
V5 Byte................................................................................................................ 19
6
Add/Drop Configuration Data Flow...................................................................... 31
7
ADM Multi-chip Configuration.............................................................................. 33
8
STM-0 Telecom Bus Timing................................................................................ 38
9
Terminal STM-1 Telecom Bus Timing (...............................................................39
10
ADM STM-1 Telecom Bus Timing w/ PTSOH=1................................................. 39
11
ADM STM-1 Telecom Bus Timing w/ PTSOH = 0............................................... 40
12
SAP Bus Connections for Terminal & ADM ........................................................ 41
13
SAP Bus Frame Format ...................................................................................... 41
14
Tributary Timing .................................................................................................. 43
15
Receive Telecom Bus Timing.............................................................................. 44
16
Transmit Telecom Bus Timing - Terminal ........................................................... 45
17
Transmit Telecom Bus Timing - ADM Parameters.............................................. 46
18
Microprocessor Data Read Timing...................................................................... 47
19
Microprocessor Data Write Timing ...................................................................... 48
20
Test Access Port ................................................................................................. 67
21
Instruction Register ............................................................................................. 67
22
Boundary Scan Cells........................................................................................... 69
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