Intel

LXT972A

3.3V Dual-Speed Fast Ethernet Transceiver Datasheet

Datasheet

The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for

easy attachment to 10/100 Media Access Controllers (MACs).

This document also supports the LXT972.

The LXT972A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition

can be set using auto-negotiation, parallel detection, or manual control.

The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3 V
power supply.

Applications

Product Features

Combination 10BASE-T/100BASE-TX

Network Interface Cards (NICs)

10/100 PCMCIA Cards

Cable Modems and Set-Top Boxes

3.3 V Operation.

Low power consumption (300 mW

typical).

10BASE-T and 100BASE-TX using a

single RJ-45 connection.

Supports auto-negotiation and parallel

detection.

MII interface with extended register

capability.

Robust baseline wander correction

performance.

Supports JTAG Boundary Scan

Standard CSMA/CD or full-duplex

operation.

Configurable via MDIO serial port or

hardware control pins.

Integrated, programmable LED drivers.

64-pin Low-profile Quad Flat Package

(LQFP).

--LXT972ALC - Commercial (0

to 70

ambient).

Order Number: 249186-003

August 2002

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S
TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY
EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The LXT972A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Contents

1.0

Pin Assignments .............................................................................................................................10

2.0

Signal Descriptions ........................................................................................................................13

3.0

Functional Description ..................................................................................................................17
3.1

Introduction .......................................................................................................................17
3.1.1

Comprehensive Functionality .............................................................................17

3.1.2

OSPTM Architecture ............................................................................................17

3.2

Network Media / Protocol Support....................................................................................18
3.2.1

10/100 Network Interface ...................................................................................18
3.2.1.1 Twisted-Pair Interface ..........................................................................18
3.2.1.2 Fault Detection and Reporting..............................................................18

3.2.2

MII Data Interface...............................................................................................19
3.2.2.1 Increased MII Drive Strength ...............................................................19

3.2.3

Configuration Management Interface .................................................................19
3.2.3.1 MDIO Management Interface ..............................................................19

3.2.3.2 MII Interrupts .......................................................................................20
3.2.3.3 Hardware Control Interface ..................................................................20

3.3

Operating Requirements....................................................................................................21
3.3.1

Power Requirements ...........................................................................................21

3.3.2

Clock Requirements............................................................................................21
3.3.2.1 External Crystal/Oscillator ...................................................................21

3.3.2.2 MDIO Clock .........................................................................................21

3.4

Initialization.......................................................................................................................22
3.4.1

MDIO Control Mode ..........................................................................................22

3.4.2

Hardware Control Mode .....................................................................................22

3.4.3

Reduced Power Modes........................................................................................23
3.4.3.1 Hardware Power Down ........................................................................23

3.4.3.2 Software Power Down..........................................................................24

3.4.4

Reset....................................................................................................................24

3.4.5

Hardware Configuration Settings........................................................................24

3.5

Establishing Link...............................................................................................................25
3.5.1

Auto-Negotiation ................................................................................................25
3.5.1.1 Base Page Exchange.............................................................................25
3.5.1.2 Next Page Exchange.............................................................................25

3.5.1.3 Controlling Auto-Negotiation...............................................................26

3.5.2

Parallel Detection................................................................................................26

3.6

MII Operation....................................................................................................................26
3.6.1

MII Clocks ..........................................................................................................27

3.6.2

Transmit Enable ..................................................................................................27

3.6.3

Receive Data Valid .............................................................................................27

3.6.4

Carrier Sense .......................................................................................................27

3.6.5

Error Signals .......................................................................................................27

3.6.6

Collision ..............................................................................................................27

3.6.7

Loopback.............................................................................................................29
3.6.7.1 Operational Loopback ..........................................................................29

3.6.7.2 Test Loopback ......................................................................................29

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

3.7

100 Mbps Operation ......................................................................................................... 30
3.7.1

100BASE-X Network Operations...................................................................... 30

3.7.2

Collision Indication ............................................................................................ 32

3.7.3

100BASE-X Protocol Sublayer Operations ....................................................... 32
3.7.3.1 PCS Sublayer ....................................................................................... 33
3.7.3.2 PMA Sublayer...................................................................................... 35

3.7.3.3 Twisted-Pair PMD Sublayer................................................................ 36

3.8

10 Mbps Operation ........................................................................................................... 36
3.8.1

10BASE-T Preamble Handling.......................................................................... 37

3.8.2

10BASE-T Carrier Sense ................................................................................... 37

3.8.3

10BASE-T Dribble Bits ..................................................................................... 37

3.8.4

10BASE-T Link Integrity Test........................................................................... 37
3.8.4.1 Link Failure.......................................................................................... 37

3.8.5

10T SQE (Heartbeat).......................................................................................... 38

3.8.6

10T Jabber .......................................................................................................... 38

3.8.7

10T Polarity Correction...................................................................................... 38

3.9

Monitoring Operations ..................................................................................................... 38
3.9.1

Monitoring Auto-Negotiation ............................................................................ 38
3.9.1.1 Monitoring Next Page Exchange......................................................... 38

3.9.2

LED Functions ................................................................................................... 39
3.9.2.1 LED Pulse Stretching........................................................................... 39

3.10

Boundary Scan (JTAG1149.1) Functions ........................................................................ 40
3.10.1

Boundary Scan Interface .................................................................................... 40

3.10.2

State Machine.................................................................................................... 40

3.10.3

Instruction Register ............................................................................................ 40

3.10.4

Boundary Scan Register (BSR).......................................................................... 40

4.0

Application Information............................................................................................................... 42
4.1

Magnetics Information ..................................................................................................... 42

4.2

Typical Twisted-Pair Interface ......................................................................................... 42

5.0

Test Specifications......................................................................................................................... 45
5.1

Electrical Parameters ........................................................................................................ 45

5.2

Timing Diagrams .............................................................................................................. 49

6.0

Register Definitions....................................................................................................................... 57

7.0

Package Specification ................................................................................................................... 73

8.0

Product Ordering Information .................................................................................................... 74

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Figures

LXT972A Block Diagram...................................................................................................9

LXT972A 64-Pin LQFP Assignments ..............................................................................10

Management Interface Read Frame Structure ..................................................................20

Management Interface Write Frame Structure .................................................................20

Interrupt Logic ..................................................................................................................21

Initialization Sequence .....................................................................................................23

Hardware Configuration Settings .....................................................................................24

Link Establishment Overview ..........................................................................................26

10BASE-T Clocking ........................................................................................................28

100BASE-X Clocking ......................................................................................................28

Link Down Clock Transition ............................................................................................28

Loopback Paths ................................................................................................................29

100BASE-X Frame Format ..............................................................................................30

100BASE-TX Data Path ...................................................................................................31

100BASE-TX Reception with no Errors ..........................................................................31

100BASE-TX Reception with Invalid Symbol ................................................................32

100BASE-TX Transmission with no Errors .....................................................................32

100BASE-TX Transmission with Collision .....................................................................32

Protocol Sublayers ............................................................................................................33

LED Pulse Stretching .......................................................................................................40

Typical Twisted-Pair Interface - Switch............................................................................43

Typical Twisted-Pair Interface - NIC ...............................................................................44

Typical MII Interface .......................................................................................................44

100BASE-TX Receive Timing - 4B Mode ......................................................................49

100BASE-TX Transmit Timing - 4B Mode .....................................................................50

10BASE-T Receive Timing .............................................................................................51

10BASE-T Transmit Timing ............................................................................................52

10BASE-T Jabber and Unjabber Timing .........................................................................53

10BASE-T SQE (Heartbeat) Timing ................................................................................53

Auto Negotiation and Fast Link Pulse Timing .................................................................54

Fast Link Pulse Timing ....................................................................................................54

MDIO Input Timing .........................................................................................................55

MDIO Output Timing .......................................................................................................55

Power-Up Timing .............................................................................................................56

RESET Pulse Width and Recovery Timing .....................................................................56

PHY Identifier Bit Mapping .............................................................................................62

LXT972A LQFP Package Specifications .........................................................................73

Ordering Information - Sample .........................................................................................74

Tables

LQFP Numeric Pin List....................................................................................................11

LXT972A MII Signal Descriptions...................................................................................13

LXT972A Network Interface Signal Descriptions............................................................14

LXT972A Miscellaneous Signal Descriptions..................................................................14

LXT972A Power Supply Signal Descriptions ..................................................................15

LXT972A JTAG Test Signal Descriptions .......................................................................15

LXT972A LED Signal Descriptions .................................................................................16

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

LXT972A Pin Types and Modes...................................................................................... 16

Hardware Configuration Settings ..................................................................................... 25

Carrier Sense, Loopback, and Collision Conditions......................................................... 29

4B/5B Coding ................................................................................................................... 34

BSR Mode of Operation ................................................................................................... 41

Supported JTAG Instructions ........................................................................................... 41

Device ID Register ........................................................................................................... 41

Magnetics Requirements .................................................................................................. 42

RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces ................................ 42

Absolute Maximum Ratings ............................................................................................. 45

Operating Conditions........................................................................................................ 45

Digital I/O Characteristics1 .............................................................................................. 46

Digital I/O Characteristics - MII Pins............................................................................... 46

I/O Characteristics - REFCLK/XI and XO Pins............................................................... 46

I/O Characteristics - LED/CFG Pins ................................................................................ 47

100BASE-TX Transceiver Characteristics....................................................................... 47

10BASE-T Transceiver Characteristics............................................................................ 47

10BASE-T Link Integrity Timing Characteristics ........................................................... 48

LXT972A Thermal Characteristics .................................................................................. 48

100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 49

100BASE-TX Transmit Timing Parameters - 4B Mode .................................................. 50

10BASE-T Receive Timing Parameters........................................................................... 51

10BASE-T Transmit Timing Parameters ......................................................................... 52

10BASE-T Jabber and Unjabber Timing Parameters....................................................... 53

10BASE-T SQE Timing Parameters ................................................................................ 53

Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 54

MDIO Timing Parameters ................................................................................................ 55

Power-Up Timing Parameters ......................................................................................... 56

RESET Pulse Width and Recovery Timing Parameters.................................................. 56

Register Set....................................................................................................................... 57

Register Bit Map............................................................................................................... 58

Control Register (Address 0) ............................................................................................ 60

MII Status Register #1 (Address 1) .................................................................................. 61

PHY Identification Register 1 (Address 2)....................................................................... 62

PHY Identification Register 2 (Address 3)....................................................................... 62

Auto Negotiation Advertisement Register (Address 4).................................................... 63

Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 64

Auto Negotiation Expansion (Address 6)......................................................................... 65

Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 65

Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 66

Configuration Register (Address 16, Hex 10) .................................................................. 66

Status Register #2 (Address 17) ....................................................................................... 67

Interrupt Enable Register (Address 18) ............................................................................ 68

Interrupt Status Register (Address 19, Hex 13)................................................................ 68

LED Configuration Register (Address 20, Hex 14) ......................................................... 70

Digital Config Register (Address 26) ............................................................................... 71

Transmit Control Register #2 (Address 30) ..................................................................... 72

Product Information.......................................................................................................... 74

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Revision History

Revision 003

Revision Date: August 6, 2002

Page #

Description

Added "JTAG Boundary Scan" to Product Features on front page.

Modified

Figure 2 "LXT972A 64-Pin LQFP Assignments"

(replaced TEST1 and TEST0 with

GND).

Modified

Table 1 "LQFP Numeric Pin List"

(replaced TEST1 and TEST0 with GND).

Added note under

Section 2.0, "Signal Descriptions"

: "Intel recommends that all inputs and

multi-function pins be tied to the inactive states and all outputs be left floating, if unused."

Modified

Table 4 "LXT972A Miscellaneous Signal Descriptions"

Modified

Table 5 "LXT972A Power Supply Signal Descriptions"

Added

Table 8 "LXT972A Pin Types and Modes"

Added

Section 3.2.2.1, "Increased MII Drive Strength"

Modified

Figure 7 "Hardware Configuration Settings"

Modified

Table 13 "Supported JTAG Instructions"

Modified

Table 14 "Device ID Register"

Modified

Table 17 "Absolute Maximum Ratings"

Modified

Table 18 "Operating Conditions"

: Added Typ values to Vcc current.

Modified

Table 20 "Digital I/O Characteristics - MII Pins"

Modified

Table 22 "I/O Characteristics - LED/CFG Pins"

Added

Table 26 "LXT972A Thermal Characteristics"

Modified

Table 29 "10BASE-T Receive Timing Parameters"

Modified

Table 38 "Register Bit Map"

(added Address 26 information).

Added

Table 53 "Digital Config Register (Address 26)"

Modified

Table 54 "Transmit Control Register #2 (Address 30)"

Added

Section 8.0, "Product Ordering Information"

Revision 002

Revision Date: January 2001

Page #

Description

N/A

Clock Requirements: Modified language under Clock Requirements heading.

I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from 40

to 35 and under Max from 60 to 65.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

1.0

Pin Assignments

Figure 2. LXT972A 64-Pin LQFP Assignments

Package Topside Markings

Marking

Definition

Part #

LXT972A is the unique identifier for this product family.

Rev #

Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping
information.)

Lot #

Identifies the batch.

FPO #

Identifies the Finish Process Order.

RXD0

RBIAS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

REFCLK/XI

MDDIS

RESET

TXSLEW0
TXSLEW1

GND

VCCIO

N/C
N/C

GND

ADDR0

GND
GND
GND
GND

GND

VCCA

TPI

GND

TDI

TDO

TMS

TCK

TRS

GND

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RXD1
RXD2
RXD3
N/C
MDC
MDIO
GND
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
GND
GND
PAUSE

MDINT

CRS

COL

GND

_EN

_CL

_ER

RX_ER

RX_CLK

VCCD

GND

RX_DV

LXT972A XX
XXXXXX
XXXXXXXX

Part #

LOT #

FPO #

Rev #

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Table 1. LQFP Numeric Pin List

Pin

Symbol

Type

Reference for

Full Description

REFCLK/XI

Input

Table 4 on page 14

Output

Table 4 on page 14

MDDIS

Input

Table 2 on page 13

RESET Input

Table 4 on page 14

TxSLEW0

Input

Table 4 on page 14

TxSLEW1

Input

Table 4 on page 14

GND

Table 5 on page 15

VCCIO

Table 5 on page 15

N/C

Table 4 on page 14

N/C

Table 4 on page 14

GND

Table 5 on page 15

ADDR0

Input

Table 4 on page 14

GND

Table 5 on page 15

GND

Table 5 on page 15

GND

Table 5 on page 15

GND

Table 5 on page 15

RBIAS

Analog Input

Table 4 on page 14

GND

Table 5 on page 15

TPOP

Output

Table 3 on page 14

TPON

Output

Table 3 on page 14

VCCA

Table 5 on page 15

VCCA

Table 5 on page 15

TPIP

Input

Table 3 on page 14

TPIN

Input

Table 3 on page 14

GND

Table 5 on page 15

GND

Table 5 on page 15

TDI

Input

Table 6 on page 15

TDO

Output

Table 6 on page 15

TMS

Input

Table 6 on page 15

TCK

Input

Table 6 on page 15

TRST Input

Table 6 on page 15

GND

Table 5 on page 15

PAUSE

Input

Table 4 on page 14

GND

Table 4 on page 14

GND

Table 4 on page 14

LED/CFG3

I/O

Table 7 on page 16

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

LED/CFG2

I/O

Table 7 on page 16

LED/CFG1

I/O

Table 7 on page 16

PWRDWN

Input

Table 4 on page 14

VCCIO

Table 5 on page 15

GND

Table 5 on page 15

MDIO

I/O

Table 2 on page 13

MDC

Input

Table 2 on page 13

N/C

Table 4 on page 14

RXD3

Output

Table 2 on page 13

RXD2

Output

Table 2 on page 13

RXD1

Output

Table 2 on page 13

RXD0

Output

Table 2 on page 13

RX_DV

Output

Table 2 on page 13

GND

Table 5 on page 15

VCCD

Table 5 on page 15

RX_CLK

Output

Table 2 on page 13

RX_ER

Output

Table 2 on page 13

TX_ER

Input

Table 2 on page 13

TX_CLK

Output

Table 2 on page 13

TX_EN

Input

Table 2 on page 13

TXD0

Input

Table 2 on page 13

TXD1

Input

Table 2 on page 13

TXD2

Input

Table 2 on page 13

TXD3

Input

Table 2 on page 13

GND

Table 5 on page 15

COL

Output

Table 2 on page 13

CRS

Output

Table 2 on page 13

MDINT Open

Drain

Table 2 on page 13

Table 1. LQFP Numeric Pin List (Continued)

Pin

Symbol

Type

Reference for

Full Description

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

2.0

Signal Descriptions

Intel recommends that all inputs and multi-function pins be tied to the inactive states and all
outputs be left floating, if unused.

Table 2. LXT972A MII Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

Data Interface Pins

60
59
58
57

TXD3
TXD2
TXD1
TXD0

Transmit Data. TXD is a bundle of parallel data signals that are driven by the
MAC. TXD<3:0> shall transition synchronously with respect to the TX_CLK.
TXD<0> is the least significant bit.

TX_EN

Transmit Enable. The MAC asserts this signal when it drives valid data on
TXD. This signal must be synchronized to TX_CLK.

TX_CLK

Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.

45
46
47
48

RXD3
RXD2
RXD1
RXD0

Receive Data. RXD is a bundle of parallel signals that transition synchronously
with respect to the RX_CLK. RXD<0> is the least significant bit.

RX_DV

Receive Data Valid. The LXT972A asserts this signal when it drives valid data
on RXD. This output is synchronous to RX_CLK.

RX_ER

Receive Error. Signals a receive error condition has occurred. This output is
synchronous to RX_CLK.

TX_ER

Transmit Error. Signals a transmit error condition. This signal must be
synchronized to TX_CLK.

RX_CLK

Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. Refer to

"Clock Requirements" on page 21

in the Functional

Description section.

COL

Collision Detected. The LXT972A asserts this output when a collision is
detected. This output remains High for the duration of the collision. This signal
is asynchronous and is inactive during full-duplex operation.

CRS

Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts
this output when either transmitting or receiving data packets. During full-
duplex operation (bit 0.8 = 1), CRS is asserted during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier,
synchronous to RX_CLK.

MII Control Interface Pins

MDDIS

Management Disable. When MDDIS is High, the MDIO is disabled from read
and write operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins
control only the initial or "default" values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts to the MDIO serial
channel.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

MDC

Management Data Clock. Clock for the MDIO serial data channel. Maximum
frequency is 8 MHz.

MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel for PHY/
STA communication.

MDINT OD

Management Data Interrupt. When bit 18.1 = 1, an active Low output on this
pin indicates status change. Interrupt is cleared by reading Register 19.

Table 3.

LXT972A Network Interface Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

19
20

TPOP
TPON

Twisted-Pair Outputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive 802.3
compliant pulses onto the line.

23
24

TPIP
TPIN

Twisted-Pair Inputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPIP/N pins receive
differential 100BASE-TX or 10BASE-T signals from the line.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

Table 4.

LXT972A Miscellaneous Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

5
6

TxSLEW0
TxSLEW1

Tx Output Slew Controls 0 and 1. These pins select the TX output slew
rate (rise and fall time) as follows:

TxSLEW1

TxSLEW0

Slew Rate (Rise and Fall Time)

3.0 ns

3.4 ns

3.9 ns

4.4 ns

RESET

Reset. This active Low input is OR'ed with the control register Reset bit
(0.15). The LXT972A reset cycle is extended to 258

µs (nominal) after

reset is deasserted.

ADDR0

Address0. Sets device address.

RBIAS

Bias. This pin provides bias current for the internal circuitry. Must be tied
to ground through a 22.1 k

, 1% resistor.

PAUSE

Pause. When set High, the LXT972A advertises Pause capabilities during
auto negotiation.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

Table 2. LXT972A MII Signal Descriptions (Continued)

LQFP

Pin#

Symbol

Type

Signal Description

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

PWRDWN

Power Down. When set High, this pin puts the LXT972A in a power-
down mode.

1
2

REFCLK/XI
XO

Crystal Input and Output. A 25 MHz crystal oscillator circuit can be
connected across XI and XO. A clock can also be used at XI. Refer to
Functional Description for detailed clock requirements.

9, 10,

N/C

No Connection. These pins are not used and should not be terminated.

Table 5. LXT972A Power Supply Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

VCCD

Digital Power. Requires a 3.3 V power supply.

7, 11, 13,

14, 15, 16,
18, 25, 26,
32, 34, 35,

41, 50, 61

GND

Ground.

8, 40

VCCIO

MII Power. Requires either a 3.3 V or a 2.5 V supply. Must be supplied
from the same source used to power the MAC on the other side of the MII.

21, 22

VCCA

Analog Power. Requires a 3.3 V power supply.

Table 6. LXT972A JTAG Test Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

TDI

Test Data Input. Test data sampled with respect to the rising edge of TCK.

TDO

Test Data Output. Test data driven with respect to the falling edge of TCK.

TMS

Test Mode Select.

TCK

Test Clock. Test clock input sourced by ATE.

TRST

Test Reset. Test reset input sourced by ATE.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.

Table 7. LXT972A LED Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

38
37
36

LED/CFG1
LED/CFG2
LED/CFG3

I/O

LED Drivers 1 -3. These pins drive LED indicators. Each LED can
display one of several available status conditions as selected by the LED
Configuration Register (refer to

Table 52 on page 70

for details).

Configuration Inputs 1-3. These pins also provide initial configuration
settings (refer to

Table 9 on page 25

for details).

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

Table 4. LXT972A Miscellaneous Signal Descriptions (Continued)

LQFP

Pin#

Symbol

Type

Signal Description

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

3.0

Functional Description

3.1

Introduction

The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and

100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A
can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185

meters).

3.1.1

Comprehensive Functionality

The LXT972A provides a standard Media Independent Interface (MII) for 10/100 MACs. The
LXT972A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media

Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also

performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.

On power-up, the LXT972A reads its configuration pins to check for forced operation settings. If

not configured for forced operation, it uses auto-negotiation/parallel detection to automatically

determine line operating conditions. If the PHY device on the other side of the link supports auto-
negotiation, the LXT972A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY

partner does not support auto-negotiation, the LXT972A automatically detects the presence of

either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions
accordingly.

The LXT972A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.

3.1.2

OSPTM Architecture

Intel's LXT972A incorporates high-efficiency Optimal Signal ProcessingTM design techniques,

combining the best properties of digital and analog signal processing to produce a truly optimal
device.

The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by

as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques

in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results

in improved receiver noise and cross-talk performance.

The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic

switching noise generated by DSP engines. This logic switching noise can be a considerable source

of EMI generated on the device's power supplies.

The OSP-based LXT972A provides improved data recovery, EMI performance and low power
consumption.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.2

Network Media / Protocol Support

The LXT972A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair.

3.2.1

10/100 Network Interface

The network interface port consists of two differential signal pairs. Refer to

Table 3

for specific pin

assignments.

The LXT972A output drivers generate either 100BASE-TX or 10BASE-T. When not transmitting
data, the LXT972A generates 802.3-compliant link pulses or idle code. Input signals are decoded

either as a 100BASE-TX or 10BASE-T input, depending on the mode selected. Auto-negotiation/

parallel detection or manual control is used to determine the speed of this interface.

3.2.1.1

Twisted-Pair Interface

The LXT972A supports either 100BASE-TX or 10BASE-T connections over 100

, Category 5,

Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT972A continuously

transmits and receives MLT3 symbols. When not transmitting data, the LXT972A generates

"IDLE" symbols.

During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link

up.

Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete

this interface. On the transmit side, the LXT972A has an active internal termination and does not
require external termination resistors. Intel's patented waveshaping technology shapes the outgoing

signal to help reduce the need for external EMI filters. Four slew rate settings (refer to

Table 4 on

page 14

) allow the designer to match the output waveform to the magnetic characteristics. On the

receive side, the internal impedance is high enough that it has no practical effect on the external

termination circuit.

3.2.1.2

Fault Detection and Reporting

The LXT972A supports one fault detection and reporting mechanism. "Remote Fault" refers to a
MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is

used only during Auto-Negotiation, and therefore is applicable only to twisted-pair links. "Far-End

Fault" is an optional PMA-layer function that may be embedded within PHY devices. The
LXT972A supports only the Remote Fault Function, explained in the paragraph that follows.

Remote Fault

indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the

link partner that the link is down because the advertising device detected a fault.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it
does the following:

Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and

Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.

3.2.2

MII Data Interface

The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data

interface and a management interface. The MII Data Interface passes data between the LXT972A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and

receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically,

once the operating conditions of the network link have been determined. Refer to

"MII Operation"

on page 26

for additional details.

3.2.2.1

Increased MII Drive Strength

A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive

signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or

through a connector. The MII drive strength in the LXT971A can be increased by setting Register
bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO

interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a

higher drive strength.

3.2.3

Configuration Management Interface

The LXT972A provides both an MDIO interface and a Hardware Control Interface for device

configuration and management.

3.2.3.1

MDIO Management Interface

The LXT972A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to

monitor and control the state of the LXT972A. The MDIO interface consists of a physical

connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.

Some registers are required and their functions are defined by the IEEE 802.3 standard. The

LXT972A also supports additional registers for expanded functionality. The LXT972A supports

multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an "X.Y" notation, where X is the register number (0-31) and Y is the bit number (0-15).

The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this

interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write

operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the

Hardware Control Interface is not used.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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MDIO Addressing

The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is

set high or low to determine the chip address.

MDIO Frame Structure

The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in

Figure 3

and

Figure 4

(read and write). MDIO Interface timing is shown in

Table 34 on

page 55

3.2.3.2

MII Interrupts

The LXT972A provides a single interrupt pin (MDINT). Interrupt logic is shown in

Figure 5

. The

LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable

and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the

device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change
on the LXT972A. Interrupts may be caused by four conditions:

Auto-negotiation complete

Speed status change

Duplex status change

Link status change

3.2.3.3

Hardware Control Interface

The LXT972A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.

Refer to

Section 3.4.5, "Hardware Configuration Settings" on page 24

for additional details.

Figure 3. Management Interface Read Frame Structure

Figure 4. Management Interface Write Frame Structure

MDC

MDIO

(Read)

32 "1"s

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Write

Read

D15

D14

Idle

High Z

MDC

MDIO

(Write)

32 "1"s

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Idle

Write

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
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3.3

Operating Requirements

3.3.1

Power Requirements

The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and

analog circuits require 3.3 V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be decoupled to ground.

An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or

+3.3 V. The inputs on the MII interface are tolerant to 5 V signals from the controller on the other

side of the MII interface. Refer to

Table 20 on page 46

for MII I/O characteristics.

As a matter of good practice, these supplies should be as clean as possible.

3.3.2

Clock Requirements

3.3.2.1

External Crystal/Oscillator

The LXT972A requires a reference clock input that is used to generate transmit signals and recover

receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of

a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is

recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.

A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a

crystal, is frequently used in switch applications. Refer to

Table 21 on page 46

for clock timing

requirements

3.3.2.2

MDIO Clock

The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to

Table 34 on page 55

for details.

Figure 5. Interrupt Logic

Force Interrupt

Interrupt Enable

Event X Mask Reg

Event X Status Reg

Interrupt Pin

.
.
.

AND

NAND

Per Event

1. Interrupt (Event) Status Register is cleared on read.

(MDINT)

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.4

Initialization

When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the

MDIO register configuration bits to determine the line speed and operating conditions to use for

the network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in

Figure 6

3.4.1

MDIO Control Mode

In the MDIO Control mode, the LXT972A reads the Hardware Control Interface pins to set the

initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.

3.4.2

Hardware Control Mode

In the Hardware Control Mode, LXT972A disables direct write operations to the MDIO registers

via the MDIO Interface. On power-up or hardware reset the LXT972A reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.

The following modes are available using either Hardware Control or MDIO Control:

Force network link operation to:
100BASE-TX, Full-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Full-Duplex
10BASE-T, Half-Duplex

Allow auto-negotiation/parallel-detection

When the network link is forced to a specific configuration, the LXT972A immediately begins

operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A

begins the auto-negotiation/parallel-detection operation.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.4.3.2

Software Power Down

Software power-down control is provided by bit 0.11 in the Control Register (refer to

Table 39 on

page 60

). During soft power-down, the following conditions are true:

The network port is shut down.

The MDIO registers remain accessible.

3.4.4

Reset

The LXT972A provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware

reset, auto-negotiation and speed are read in from pins (refer to

Table 9 on page 25

for pin settings

and to

Table 39 on page 60

for register bit definitions).

During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values

made since the last hardware reset are not detected during a software reset.

During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.

During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).

3.4.5

Hardware Configuration Settings

The LXT972A provides a hardware option to set the initial device configuration. The hardware

option uses the three LED driver pins. This provides three control bits, as listed in

Table 9

. The

LED drivers can operate as either open-drain or open-source circuits as shown in

Figure 7

Figure 7. Hardware Configuration Settings

Configuration Bit = 1

Configuration Bit = 0

LED/CFG Pin

3.3 V

1. The LED/CFG pins automatically adjust their

polarity upon power-up or reset.

2. Unused LEDs may be implemented with pull-up/

pull-down resistors of 10 K.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
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3.5

Establishing Link

See

Figure 8

for an overview of link establishment.

3.5.1

Auto-Negotiation

If not configured for forced operation, the LXT972A attempts to auto-negotiate with its link

partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced
62.5

µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may

be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are

referred to as a "link code word". All devices that support auto-negotiation must implement the
"Base Page" defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional "Next

Page" function as described in

Table 46

and

Table 47

(registers 7 and 8).

3.5.1.1

Base Page Exchange

By exchanging Base Pages, the LXT972A and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to continue.

Each side identifies the highest common capabilities that both sides support and configures itself

accordingly.

3.5.1.2

Next Page Exchange

Additional information, above that required by base page exchange, is also sent via "Next Pages".
The LXT972A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.

Table 9. Hardware Configuration Settings

Desired Mode

LED/CFGn

Pin Settings

Resulting Register Bit Values

Control Register

Auto-Neg Advertisement

Auto-Neg

Speed

(Mbps)

Duplex

AutoNeg

0.12

Speed

0.13

0.8

100FD

4.8

100TX

4.7

10FD

4.6

10T

4.5

Disabled

Half

Low

N/A

Auto-Negotiation Advertisement

Full

Low

High

100

Half

Low

High

Low

Full

Low

High

Enabled

100 Only

Half

High

Low

Full

High

Low

High

10/100

Half Only

High

Low

Full or

Half

High

1. Refer to

Table 7 on page 16

for LED/CFG pin assignments.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.5.1.3

Controlling Auto-Negotiation

When auto-negotiation is controlled by software, the following steps are recommended:

After power-up, power-down, or reset, the power-down recovery time, as specified in

Table 36

on page 56

, must be exhausted before proceeding.

Set the Auto-Negotiation Advertise Register bits.

Enable auto-negotiation (set MDIO Register bit 0.12 = 1).

3.5.2

Parallel Detection

For the parallel detection feature of auto-negotiation, the LXT972A also monitors for 10BASE-T

Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device

automatically reverts to the corresponding operating mode. Parallel detection allows the LXT972A
to communicate with devices that do not support auto-negotiation.

3.6

MII Operation

The LXT972A device implements the Media Independent Interface (MII) as defined in the IEEE
802.3 standard. Separate channels are provided for transmitting data from the MAC to the

LXT972A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine signals are used to pass received data to the

MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit

data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER.

The LXT972A supplies both clock signals as well as separate outputs for carrier sense and
collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.

Figure 8. Link Establishment Overview

Check Value

0.12

Start

Done

Enable

Auto-Neg/Parallel Detection

Go To Forced

Settings

Attempt Auto-

Negotiation

Listen for 10T

Link Pulses

Listen for 100TX

Idle Symbols

Link Up?

YES

Power-Up, Reset,

or Link Failure

Disable

Auto-Negotiation

0.12 = 0

0.12 = 1

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.6.1

MII Clocks

The LXT972A is the master clock source for data transmission and supplies both MII clocks

(RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When
the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at

10 Mbps, the clocks are set to 2.5 MHz.

Figure 9

through

Figure 11

show the clock cycles for each

mode. The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT972A samples these signals on the rising edge of TX_CLK.

3.6.2

Transmit Enable

The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.

3.6.3

Receive Data Valid

The LXT972A asserts RX_DV when it receives a valid packet. Timing changes depend on line

operating speed:

For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the

data packet.

For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet.

3.6.4

Carrier Sense

Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received

from the line and in half-duplex when a packet is transmitted.

Carrier sense is not generated when a packet is transmitted and in full-duplex mode.

Table 10

summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.

3.6.5

Error Signals

When LXT972A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts

RX_ER and drives "1110" on the RXD pins.

When the MAC asserts TX_ER, the LXT972A drives "H" symbols out on the TPOP/N pins.

3.6.6

Collision

The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is

half-duplex and the transmitter and receiver are active at the same time.

Table 10

summarizes the

conditions for assertion of carrier sense, collision, and data loopback signals.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.6.7

Loopback

The LXT972A provides two loopback functions, operational and test (see

Table 10

). Loopback

paths are shown in

Figure 12

3.6.7.1

Operational Loopback

Operational loopback is provided for 10 Mbps half-duplex links when bit 16.8 = 0. Data

transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData).

Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.

3.6.7.2

Test Loopback

A test loopback function is provided for diagnostic testing of the LXT972A. During test loopback,
the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the

LXT972A and returned to the MAC.

Test loopback is available for both 100TX and 10T operation. Test loopback is enabled by setting

bits as follows:

0.14 = 1

0.8 = 1 (full-duplex)

0.12 = 0 (disable auto-negotiation).

Figure 12. Loopback Paths

Table 10. Carrier Sense, Loopback, and Collision Conditions

Speed

Duplex Condition

Carrier Sense

Test

Loopback

Operational

Loopback

Collision

100 Mbps

Full-Duplex

Receive Only

Yes

None

Half-Duplex

Transmit or Receive

Transmit and

Receive

1. Test Loopback is enabled when Register bit 0.14 = 1

10T

Loopback

Digital

Block

MII

TX Driver

100X

Loopback

Analog

Block

LXT972A

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.7

100 Mbps Operation

3.7.1

100BASE-X Network Operations

During 100BASE-X operation, the LXT972A transmits and receives 5-bit symbols across the
network link.

Figure 13

shows the structure of a standard frame packet. When the MAC is not

actively transmitting data, the LXT972A sends out Idle symbols on the line.

In 100TX mode, the LXT972A scrambles and transmits the data to the network using MLT-3 line

code (

Figure 14 on page 31

). MLT-3 signals received from the network are descrambled, decoded,

and sent across the MII to the MAC.

10 Mbps

Full-Duplex

Receive Only

Yes

None

Half-Duplex,
Register bit 16.8 = 0

Transmit or Receive

Yes

Transmit and
Receive

Half-Duplex,
Register bit 16.8 = 1

Transmit or Receive

Transmit and
Receive

Table 10. Carrier Sense, Loopback, and Collision Conditions (Continued)

Speed

Duplex Condition

Carrier Sense

Test

Loopback

Operational

Loopback

Collision

1. Test Loopback is enabled when Register bit 0.14 = 1

Figure 13. 100BASE-X Frame Format

SFD

64-Bit Preamble

(8 Octets)

Start-of-Frame

Delimiter (SFD)

Destination and Source

Address (6 Octets each)

Packet Length

(2 Octets)

Data Field

(Pad to minimum packet size)

Frame Check Field

(4 Octets)

CRC

InterFrame Gap / Idle Code

(> 12 Octets)

Replaced by

/T/R/ code-groups

End-of-Stream Delimiter (ESD)

IFG

Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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As shown in

Figure 13 on page 30

, the MAC starts each transmission with a preamble pattern. As

soon as the LXT972A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,

symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.

Once the packet ends, the LXT972A transmits the End-of Stream-Delimiter (ESD, symbols T and

R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in

Table 11 on page 34

Figure 15

shows normal reception with no errors. When the LXT972A receives invalid symbols

from the line, it asserts RX_ER as shown in

Figure 16

Figure 14. 100BASE-TX Data Path

Parallel

Serial

Parallel

MLT3

-1

Transition = 1.

No Transition = 0.

All transitions must follow

pattern: 0, +1, 0, -1, 0, +1...

Scrambler Bypass Data Flow

S0 S1 S2 S3 S4

Standard Data Flow

Parallel

Serial

Parallel

D0 D1 D2 D3

4B/5B

S0 S1 S2 S3 S4

MLT3

-1

Transition = 1.

No Transition = 0.

All transitions must follow

pattern: 0, +1, 0, -1, 0, +1...

Scramble

De-

Scramble

Figure 15. 100BASE-TX Reception with no Errors

RX_CLK

RX_DV

RXD<3:0>

RX_ER

preamble SFD SFD DA

CRC

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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3.7.2

Collision Indication

Figure 17

shows normal transmission. Upon detection of a collision, the COL output is asserted

and remains asserted for the duration of the collision as shown in

Figure 18

3.7.3

100BASE-X Protocol Sublayer Operations

With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY)

device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium

Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from

the reference model point of view.

Figure 16. 100BASE-TX Reception with Invalid Symbol

RX_CLK

RX_DV

RXD<3:0>

RX_ER

preamble SFD SFD DA

Figure 17. 100BASE-TX Transmission with no Errors

Figure 18. 100BASE-TX Transmission with Collision

DA DA DA DA DA

DA DA

TX_CLK

TX_EN

TXD<3:0>

CRS

COL

JAM

TX_CLK

TX_EN

TXD<3:0>

CRS

COL

JAM

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

3.7.3.1

PCS Sublayer

The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/

decoding function.

For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver
as long as TX_EN is de-asserted.

Preamble Handling

When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-

Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues

to encode the remaining MII data, following the coding in

Table 11 on page 34

, until TX_EN is de-

asserted. It then returns to supplying IDLE symbols to the line driver.

In the receive direction, the PCS layer performs the opposite function, substituting two preamble

nibbles for the SSD.

Dribble Bits

The LXT972A handles dribbles bits in all modes. If between one through four dribble bits are

received, the nibble is passed across the MII, padded with 1s if necessary. If between five through
seven dribble bits are received, the second nibble is not sent onto the MII bus.

Figure 19. Protocol Sublayers

Encoder/Decoder

Serializer/De-serializer

Link/Carrier Detect

PCS

Sublayer

PMA

Sublayer

MII Interface

LXT972A

100BASE-TX

Scrambler/

De-scrambler

PMD

Sublayer

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 11. 4B/5B Coding

Code Type

4B Code

3 2 1 0

Name

5B Code

4 3 2 1 0

Interpretation

0 0 0 0

1 1 1 1 0

Data 0

0 0 0 1

0 1 0 0 1

Data 1

0 0 1 0

1 0 1 0 0

Data 2

0 0 1 1

1 0 1 0 1

Data 3

0 1 0 0

0 1 0 1 0

Data 4

0 1 0 1

0 1 0 1 1

Data 5

0 1 1 0

0 1 1 1 0

Data 6

DATA

0 1 1 1

0 1 1 1 1

Data 7

1 0 0 0

1 0 0 1 0

Data 8

1 0 0 1

1 0 0 1 1

Data 9

1 0 1 0

1 0 1 1 0

Data A

1 0 1 1

1 0 1 1 1

Data B

1 1 0 0

1 1 0 1 0

Data C

1 1 0 1

1 1 0 1 1

Data D

1 1 1 0

1 1 1 0 0

Data E

1 1 1 1

1 1 1 0 1

Data F

IDLE

undefined

1 1 1 11

Idle. Used as inter-stream fill code

0 1 0 1

1 1 0 0 0

Start-of-Stream Delimiter (SSD), part 1
of 2

CONTROL

0 1 0 1

1 0 0 0 1

Start-of-Stream Delimiter (SSD), part 2
of 2

undefined

0 1 1 0 1

End-of-Stream Delimiter (ESD), part 1
of 2

undefined

0 0 1 1 1

End-of-Stream Delimiter (ESD), part 2
of 2

undefined

0 0 1 0 0

Transmit Error. Used to force signaling
errors

undefined

Invalid

0 0 0 0 0

Invalid

undefined

Invalid

0 0 0 0 1

Invalid

undefined

Invalid

0 0 0 1 0

Invalid

INVALID

undefined

Invalid

0 0 0 1 1

Invalid

undefined

Invalid

0 0 1 0 1

Invalid

undefined

Invalid

0 0 1 1 0

Invalid

undefined

Invalid

0 1 0 0 0

Invalid

1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
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3.7.3.2

PMA Sublayer

Link

In 100 Mbps mode, the LXT972A establishes a link whenever the scrambler becomes locked and

remains locked for approximately 50 ms. Whenever the scrambler loses lock (receiving less than
12 consecutive idle symbols during a 2 ms window), the link are taken down. This provides a very

robust link, essentially filtering out any small noise hits that may otherwise disrupt the link.

Furthermore, 100 M idle patterns will not bring up a 10 Mbps link.

The LXT972A reports link failure via the MII status bits Register bits 1.2 and 17.10) and interrupt
functions. If auto-negotiation is enabled, link failure causes the LXT972A to re-negotiate.

Link Failure Override

The LXT972A normally transmits data packets only if it detects the link is up. Setting Register bit

16.14 = 1 overrides this function, allowing the LXT972A to transmit data packets even when the

link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be
disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the

LXT972A automatically transmits FLP bursts if the link is down.

Carrier Sense

For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of
carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of

CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in

this case RX_ER is asserted for one clock cycle when CRS is de-asserted.

Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:

De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to

appear somewhat shorter to the MAC than it actually is on the wire.

CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.

Receive Data Valid

The LXT972A asserts RX_DV to indicate that the received data maps to valid symbols. However,

RXD outputs zeros until the received data is decoded and available for transfer to the controller.

undefined

Invalid

0 1 1 0 0

Invalid

undefined

Invalid

1 0 0 0 0

Invalid

undefined

Invalid

1 1 0 0 1

Invalid

Table 11. 4B/5B Coding (Continued)

Code Type

4B Code

3 2 1 0

Name

5B Code

4 3 2 1 0

Interpretation

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

3.7.3.3

Twisted-Pair PMD Sublayer

The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and

de-scrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10BASE-T), as well
as receiving polarity correction and baseline wander correction functions.

Scrambler/De-scrambler

The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using

an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial

whenever IDLE symbols are received.

Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are
scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed.

Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the

design.

Scrambler Bypass. The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1.
Scrambler bypass is provided for diagnostic and test support.

Baseline Wander Correction

The LXT972A provides a baseline wander correction function which makes the device robust

under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by

definition "unbalanced". This means that the average value of the signal voltage can "wander"
significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at

long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are

completely data dependent.

The LXT972A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case "killer" packets over all cable lengths.

Polarity Correction

The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the

receive signal at TPIP and TPIN is inverted.

Programmable Slew Rate Control

The LXT972A device supports a slew rate mechanism whereby one of four pre-selected slew rates
can be used. This allows the designer to optimize the output waveform to match the characteristics

of the magnetics. The slew rate is determined by the TxSLEW pins as shown in

Table 4 on page 14

3.8

10 Mbps Operation

The LXT972A operates as a standard 10BASE-T transceiver. The LXT972A supports all the

standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT972A transmits and

receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, the LXT972A drives link pulses onto the line.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT972A and sent across the MII to the

MAC.

3.8.1

10BASE-T Preamble Handling

The LXT972A offers two options for preamble handling, selected by bit 16.5. In 10T Mode when
Register bit 16.5 = 0, the LXT972A strips the entire preamble off of received packets. CRS is

asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When

RX_DV is asserted, the very first two nibbles driven by the LXT972A are the SFD "5D" hex
followed by the body of the packet.

In 10BASE-T mode when Register bit 16.5 = 1, the LXT972A passes the preamble through the

MII and asserts RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT972A loops

back whatever the MAC transmits to it, including the preamble.

3.8.2

10BASE-T Carrier Sense

For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on

reception of an end-of-frame (EOF) marker. Bit 16.7 allows CRS de-assertion to be synchronized

with RX_DV de-assertion. Refer to

Table 48 on page 66

3.8.3

10BASE-T Dribble Bits

The LXT972A device handles dribbles bits in all modes. If between one through four dribble bits

are received, the nibble is passed across the MII, padded with 1s if necessary. If between five

through seven dribble bits are received, the second nibble is not sent onto the MII bus.

3.8.4

10BASE-T Link Integrity Test

In 10BASE-T mode, the LXT972A always transmits link pulses. When the Link Integrity Test

function is enabled (the normal configuration), it monitors the connection for link pulses. Once link
pulses are detected, data transmission is enabled and remains enabled as long as either the link

pulses or data transmission continue. If the link pulses stop, the data transmission is disabled.

If the Link Integrity Test function is disabled, the LXT972A transmits to the connection regardless

of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit
16.14 = 1.

3.8.4.1

Link Failure

Link failure occurs if Link Integrity Test is enabled and link pulses or packets stop being received.

If this condition occurs, the LXT972A returns to the auto-negotiation phase if auto-negotiation is

enabled. If the Link Integrity Test function is disabled by setting Register bit 16.14 = 1 in the
Configuration Register, the LXT972A transmits packets, regardless of link status.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

3.8.5

10T SQE (Heartbeat)

By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To
enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT972A asserts

its COL output for 5-15 BT after each packet. See

Figure 29 on page 53

for SQE timing

parameters.

3.8.6

10T Jabber

If a transmission exceeds the jabber timer, the LXT972A disables the transmit and loopback

functions. See

Figure 28 on page 53

for jabber timing parameters.

The LXT972A automatically exits jabber mode after the unjabber time has expired. This function

can be disabled by setting Register bit 16.10 = 1.

3.8.7

10T Polarity Correction

The LXT972A automatically detects and corrects for the condition where the receive signal (TPIP/

N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-

frame (EOF) markers, are received consecutively. If link pulses or data are not received by the
maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.

3.9

Monitoring Operations

3.9.1

Monitoring Auto-Negotiation

Auto-negotiation can be monitored as follows:

3.9.1.1

Monitoring Next Page Exchange

The LXT972A offers an Alternate Next Page mode to simplify the next page exchange process.

Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode

is enabled (Register bit 16.1 = 1), Register bit 6.1 is automatically cleared whenever a new
negotiation process takes place. This prevents the user from reading an old value in Register bit

6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally,

the LXT972A uses Register bit 6.5 to indicate when the current received page is the base page.
This information is useful for recognizing when next pages must be resent due to a new negotiation

process starting. Register bits 6.1 and 6.5 are cleared when read.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

3.9.2

LED Functions

The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for
approximately one second after reset de-asserts. Each LED driver can be programmed using the

LED Configuration Register (refer to

Table 52 on page 70

) to indicate one the following

conditions:

Operating Speed

Transmit Activity

Receive Activity

Collision Condition

Link Status

Duplex Mode

The LED drivers can also be programmed to display various combined status conditions. For
example, setting Register bits 20.15:12 = 1101 produces the following combination of Link and

Activity indications:

If Link is down, LED is off.

If Link is up, LED is on.

If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register

bits 20.3:2 and continues to blink as long as activity is present.

The LED driver pins also provide initial configuration settings. The LED pins are sensitive to
polarity and automatically pulls up or pulls down to configure for either open drain or open source

circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the

discussion of

"Hardware Configuration Settings" on page 24

for details.

3.9.2.1

LED Pulse Stretching

The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms.
If during this pulse stretch period the event occurs again, the pulse stretch time is further extended.

When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.

The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires, the stretch timer is reset and the stretch time is extended.

When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.

When the stretch timer expires the edge detector is reset so that a long event causes another pulse to

be generated from the edge detector, which resets the stretch timer and causes the LED driver to
remain asserted.

Figure 20

shows how the stretch operation functions.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

3.10

Boundary Scan (JTAG1149.1) Functions

LXT972A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input,

output, and input/output pins are accessible. The BSDL file is available by contacting your local
sales office (see the back page) or by accessing the Intel web site (developer.intel.com/design/

network/).

3.10.1

Boundary Scan Interface

This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is

internally pulled down. TDO does not have an internal pull-up or pull-down.

3.10.2

State Machine

The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are

high for five TCK periods.

3.10.3

Instruction Register

After the state machine resets, the IDCODE instruction is always invoked. The decode logic

ensures the correct data flow to the Data registers according to the current instruction. Valid

instructions are listed in

Table 13

3.10.4

Boundary Scan Register (BSR)

Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the

serial shift stage and the parallel output stage. There are four modes of operation as listed in

Table

Figure 20. LED Pulse Stretching

Event

LED

Note: The direct drive LED outputs in this diagram are shown as active Low.

stretch

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Table 12. BSR Mode of Operation

Mode

Description

Capture

Shift

Update

System Function

Table 13. Supported JTAG Instructions

Name

Code

Description

Mode

Data Register

EXTEST

1111 1111 1110 1000

External Test

Test

BSR

IDCODE

1111 1111 1111 1110

ID Code Inspection

Normal

ID REG

SAMPLE

1111 1111 1111 1000

Sample Boundary

Normal

BSR

HIGHZ

1111 1111 1100 1111

Force Float

Normal

Bypass

CLAMP

1111 1111 1110 1111

Control Boundary to 1/0

Test

Bypass

BYPASS

1111 1111 1111 1111

Bypass Scan

Normal

Bypass

Table 14. Device ID Register

31:28

27:12

11:8

7:1

Version

Part ID (hex)

Jedec Continuation Characters

JEDEC ID

Reserved

XXXX

03CB

0000

111 1110

1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110) which

becomes 111 1110.

2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the

Jedec continuation characters.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

4.0

Application Information

4.1

Magnetics Information

The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer

isolation voltage should be rated at 2kV to protect the circuitry from static voltages across the
connectors and cables. Refer to

Table 15

for transformer requirements.

A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic

Manufacturers for Networking Product Applications (document number 248991) and is found on

the Intel web site (www.Intel.com). Before committing to a specific component, designers should
contact the manufacturer for current product specifications, and validate the magnetics for the

specific application.

4.2

Typical Twisted-Pair Interface

Table 16

provides a comparison of the RJ-45 connections for NIC and switch applications in a

typical twisted-pair interface setting.

Figure 21 on page 43

shows a typical twisted-pair interface with the RJ-45 connections crossed

over for a switch configuration.

Figure 22 on page 44

provides a typical twisted-pair interface with

the RJ-45 connections configured for a NIC application.

Table 15. Magnetics Requirements

Parameter

Min

Nom

Max

Units

Test Condition

Rx turns ratio

1 : 1

Tx turns ratio

1 : 1

Insertion loss

0.0

0.6

1.1

Primary inductance

350

µH

Transformer isolation

1.5

Differential to common mode rejection

.1 to 60 MHz

60 to 100 MHz

Return Loss

-16

30 MHz

-10

80 MHz

Table 16. RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces

Symbol

RJ-45

Switch

NIC

TPIP

TPIN

TPOP

TPON

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

5.0

Test Specifications

Note:

Table 17

through

Table 36

and

Figure 24

through

Figure 35

represent the target specifications of

the LXT972A. These specifications are guaranteed by test except where noted "by design."

Minimum and maximum values listed in

Table 19

through

Table 36

apply over the recommended

operating conditions specified in

Table 18

5.1

Electrical Parameters

Table 17. Absolute Maximum Ratings

Parameter

Sym

Min

Max

Units

Supply voltage

-0.3

4.0

Operating temperature

OPA

-15

+85

ºC

Storage temperature

-65

+150

ºC

Caution: Exceeding these values may cause permanent damage.

Functional operation under these conditions is not implied.

Exposure to maximum rating conditions for extended periods may affect device
reliability.

Table 18. Operating Conditions

Parameter

Sym

Min

Typ

Max

Units

Recommended operating
temperature

LXT972A_C
(Commercial)

OPA

ºC

Recommended supply voltage

Analog & Digital

Vcca, Vccd

3.14

3.3

3.45

I/O

Vccio

2.35

3.45

current

100BASE-TX

110

10BASE-T

Hard Power Down

Soft Power Down

Icc

Auto-Negotiation

110

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 19. Digital I/O Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Input Low voltage

0.8

Input High voltage

2.0

Input current

-10

µA

0.0 < V

< V

Output Low voltage

0.4

= 4 mA

Output High voltage

2.4

= -4 mA

1. Applies to all pins except MII, LED and XI/XO pins. Refer to

Table 20

for MII I/O Characteristics,

Table 21

for XI/

XO and

Table 22

for LED Characteristics.

2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 20. Digital I/O Characteristics - MII Pins

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Input Low voltage

0.8

Input High voltage

2.0

Input current

-10

µA

0.0 < V

< VCCIO

Output Low voltage

0.4

= 4 mA

Output High voltage

2.2

= -4 mA, VCCIO = 3.3 V

2.0

= -4 mA, VCCIO = 2.5 V

Driver output resistance
(Line driver output enabled)

100

VCCIO = 2.5 V

100

VCCIO = 3.3 V

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.

Table 21. I/O Characteristics - REFCLK/XI and XO Pins

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Input Low Voltage

0.8

Input High Voltage

2.0

Input Clock Frequency Tolerance

100

ppm

Input Clock Duty Cycle

Tdc

Input Capacitance

3.0

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.

Table 22. I/O Characteristics - LED/CFG Pins

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Input Low Voltage

0.8

Input High Voltage

2.0

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

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Input Current

-10

µA

0 < V

< VCCIO

Output Low Voltage

0.4

= 10 mA

Output High Voltage

2.0

= -10 mA

Table 23. 100BASE-TX Transceiver Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Peak differential output voltage

0.95

1.05

Note 2

Signal amplitude symmetry

Vss

102

Note 2

Signal rise/fall time

3.0

5.0

Note 2

Rise/fall time symmetry

RFS

0.5

Note 2

Duty cycle distortion

Offset from 16ns pulse
width at 50% of pulse
peak

Overshoot/Undershoot

Jitter (measured differentially)

1.4

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100

(+/-1%) resistor.

Table 24. 10BASE-T Transceiver Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output
voltage

2.2

2.5

2.8

With transformer, line
replaced by 100

resistor

Transition timing jitter added
by the MAU and PLS sections

After line model specified
by IEEE 802.3 for
10BASE-T MAU

Receiver

Receive Input Impedance

Differential Squelch
Threshold

300

420

585

Table 25. 10BASE-T Link Integrity Timing Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Time Link Loss Receive

150

Link Pulse

Link Pulses

Link Min Receive Timer

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 22. I/O Characteristics - LED/CFG Pins (Continued)

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

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Rev. Date: August 7, 2002

Figure 34. Power-Up Timing

Table 35. Power-Up Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Voltage threshold

2.9

Power Up delay

300

µs

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY

comes out of reset after a delay of No MORE Than 300

s. System designers should consider this as a minimum

value - After threshold v1 is reached, the MAC should delay No LESS Than 300

before accessing the MDIO port.

Figure 35. RESET Pulse Width and Recovery Timing

Table 36. RESET Pulse Width and Recovery Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

RESET pulse width

RESET recovery delay

300

µs

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the

PHY comes out of reset after a delay of No MORE Than 300

s. System designers should consider this as a minimum

value - After de-asserting RESET*, the MAC should delay No LESS Than 300

s before accessing the MDIO port.

VCC

MDIO,etc

RESET

MDIO,etc

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

6.0

Register Definitions

The LXT972A register set includes multiple 16-bit registers. Refer to

Table 37

for a complete

Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and

Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation" sections of the IEEE 802.3 standard.

Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique

chip functions.

Table 37. Register Set

Address

Register Name

Bit Assignments

Control Register

Refer to

Table 39 on page 60

Status Register #1

Refer to

Table 40 on page 61

PHY Identification Register 1

Refer to

Table 41 on page 62

PHY Identification Register 2

Refer to

Table 42 on page 62

Auto-Negotiation Advertisement Register

Refer to

Table 43 on page 63

Auto-Negotiation Link Partner Base Page Ability Register

Refer to

Table 44 on page 64

Auto-Negotiation Expansion Register

Refer to

Table 45 on page 65

Auto-Negotiation Next Page Transmit Register

Refer to

Table 46 on page 65

Auto-Negotiation Link Partner Received Next Page
Register

Refer to

Table 47 on page 66

1000BASE-T/100BASE-T2 Control Register

Not Implemented

1000BASE-T/100BASE-T2 Status Register

Not Implemented

Extended Status Register

Not Implemented

Port Configuration Register

Refer to

Table 48 on page 66

Status Register #2

Refer to

Table 49 on page 67

Interrupt Enable Register

Refer to

Table 50 on page 68

Interrupt Status Register

Refer to

Table 51 on page 68

LED Configuration Register

Refer to

Table 52 on page 70

21-25

Reserved

27-30

Transmit Control Register

Refer to

Table 54 on page 72

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

a
ble 38.

Register

Bit M

a
p

Reg T

i
tle

Bit Fields

Addr

1
4

B13

1
2

1
0

Con

t
r
o
l Register

Contr

o
l

e
s
e
t

o
opb

ack

Speed Select

A/N En

able

Power Down

Isolate

e
-start A/

Duplex Mo

e
st

Spee

Select

s
e
r
v
e
d

S
t
at

u
s
Register

a
t
u

100B

ase-X

Full

Duplex

100Base-X

Half

Duplex

b
ps

Full

Duplex

b
p
s

Half

Duplex

100Base- T2 Full Duplex

ase

2
Half

Duplex

tend

a
t
u
s

Res

e
r
v
ed

eamble

Suppr

e
s
s

A/N

o
mplete

Rem

o
t
e

A/N

Ability

n
k
S

t
a
t
us

b
b
e
r

Detect

tend

a
pability

PHY ID Registers

Y ID 1

1
5

1
4

1
3

1
2

1
1

1
0

543

PHY ID No

MFR

Model No

MFR R

e
v No

Auto-Negotiation Advert

ement Regis

t
e
r

A/N Advert

e
s
e
r
v
ed

Remo

Faul

Res

e
rv

Asymm

Pause

ase

ase-

TX Full Duplex

Bas

e
-T

Full

Duplex

10B

a
se-T

EE Selector

Field

Auto-Negotiation Link

a
rtner

Base Page Abil

y Register

A/N Lin

Abilit

Ack

Remo

Faul

Res

e
rv

Asymm

Pause

ase

ase-

TX Full Duplex

Bas

e
-T

Full

Duplex

10B

a
se-T

EE Selector

Field

Auto-Negotiation

Expansion Regis

t
e
r

A/N Exp

a
nsi

o
n

Res

e
rv

Base Page

Parallel Detect Fa

Link

Par

t
ner

xt Page Able

Able

Page

eceived

Link

Partn

e
r

A/N Able

Auto-Negotiation

Next Pa

ge T

r
ansmit Register

A/N Next P

a
ge

i
t

e
s
e
r
v
ed

Messag

g
e

Ack

T
oggle

sage

/ Unf

o
r
m

atted Code F

i
eld

Auto-Negotiation Link

a
rtn

er Next Page Receive Register

A/N Link Next

Pag

Ack

Messag

g
e

Ack

T
oggle

sage

/ Unf

o
r
m

atted Code F

i
eld

Configuration Register

Port Config

Reser

v
ed

For

ce Link Pass

Txmit Dis

a
ble

y
p
a
ss

Scrambler

00T

Reser

v
ed

)

Jab

b
er

)

SQE

0T)

back

)

CRS Select

)

Reserv

e
served

e
se

rved

Alternate Next Page

Reser

v
ed

1
6

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

S
t
a
t
us

gis

t
er #2

S
t
atus Register

s
e
rv

e
d

/10

r
ansmit St

a
t
u
s

Receive St

a
t
u
s

Collision

a
t
u
s

Lin

Duplex Mo

Auto-Neg

u
to-

Neg

o
mplete

Reserved

P
o
larity

Paus

rror

eserved

1
7

Interrupt Enable Register

Interrupt E

able

Reser

v
ed

Res

e
rv

u
to-

Neg

Mask

Speed Mask

Duplex Mask

Link M

a
s
k

Res

e
r
v
ed

e
served

terru

a
b
l
e

s
t

t
e
rr

u
p
t

Interrupt S

t
atus Register

Interrupt

a
t
u

Reser

v
ed

Res

e
rv

u
to-

Neg

Done

Speed Chan

Duplex Ch

ang

Link

a
n
g
e

Res

e
rv

t
e
r
r
u
p
t

e
served

Reserv

1
9

LED Configuration

Register

D Config

LED1

ED2

ED3

ED Freq

Pulse St

r
e
t
c
h

s
e
rv

e
d

2
0

Digital Config Regis

t
e
r

Digital Config

Reserved

S
t
r
o
ng

Dig

i
ta

Pac

Sym

bol

Error

Res

e
rv

r
ansmit Contr

o
l
Register

a
n

s
.
C

o
n
t
r
o
l

Reser

v
e
d

r
ansmit

w Pwr

rt Rise T

i
me C

o
n
t
rol

eser

ved

3
0

a
ble 38.

Register

Bit Map (Continued)

Reg T

i
tle

Bit Fields

Add

1
5

1
4

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 39. Control Register (Address 0)

Bit

Name

Description

Type

Default

0.15

Reset

1 = PHY reset
0 = Normal operation

R/W

0.14

Loopback

1 = Enable loopback mode
0 = Disable loopback mode

R/W

0.13

Speed Selection

0.6

0.13

Speed Selected

R/W

Note 2

1
1
0
0

1
0
1
0

Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps

0.12

Auto-Negotiation
Enable

1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process

R/W

Note 2

0.11

Power-Down

1 = Power-down
0 = Normal operation

R/W

0.10

Isolate

1 = Electrically isolate PHY from MII
0 = Normal operation

R/W

0.9

Restart
Auto-Negotiation

1 = Restart Auto-Negotiation Process
0 = Normal operation

R/W

0.8

Duplex Mode

1 = Full Duplex
0 = Half Duplex

R/W

Note 2

0.7

Collision Test

1 = Enable COL signal test
0 = Disable COL signal test

R/W

0.6

Speed Selection

0.6

0.13

Speed Selected

R/W

1
1
0
0

1
0
1
0

Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps

0.5:0

Reserved

Write as 0, ignore on Read

R/W

00000

1. R/W = Read/Write

RO = Read Only
SC = Self Clearing

2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to

Table 9 on page 25

Table 40. MII Status Register #1 (Address 1)

Bit

Name

Description

Type

Default

1.15

100BASE-T4
Not Supported

1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4

1.14

100BASE-X Full-
Duplex

1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X

1.13

100BASE-X Half-
Duplex

1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X

1. RO = Read Only

LL = Latching Low
LH = Latching High

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

1.12

10 Mbps Full-Duplex

1 = PHY able to operate at 10 Mbps in full-duplex mode
0 = PHY not able to operate at 10 Mbps full-duplex
mode

1.11

10 Mbps Half-Duplex

1 = PHY able to operate at 10 Mbps in half-duplex mode
0 = PHY not able to operate at 10 Mbps in half-duplex

1.10

100BASE-T2 Full-
Duplex
Not Supported

1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2

1.9

100BASE-T2 Half-
Duplex
Not Supported

1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2

1.8

Extended Status

1 = Extended status information in register 15
0 = No extended status information in register 15

1.7

Reserved

1 = ignore when read

1.6

MF Preamble
Suppression

1 = PHY accepts management frames with preamble
suppressed
0 = PHY will not accept management frames with
preamble suppressed

1.5

Auto-Negotiation
Complete

1 = Auto-negotiation complete
0 = Auto-negotiation not complete

1.4

Remote Fault

1 = Remote fault condition detected
0 = No remote fault condition detected

RO/LH

1.3

Auto-Negotiation
Ability

1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation

1.2

Link Status

1 = Link is up
0 = Link is down

RO/LL

1.1

Jabber Detect

1 = Jabber condition detected
0 = Jabber condition not detected

RO/LH

1.0

Extended Capability

1 = Extended register capabilities
0 = Basic register capabilities

Table 41. PHY Identification Register 1 (Address 2)

Bit

Name

Description

Type

Default

2.15:0

PHY ID Number

The PHY identifier composed of bits 3 through 18 of the
OUI.

0013 hex

1. RO = Read Only

Table 40. MII Status Register #1 (Address 1)

Bit

Name

Description

Type

Default

1. RO = Read Only

LL = Latching Low
LH = Latching High

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Table 43. Auto Negotiation Advertisement Register (Address 4)

Bit

Name

Description

Type

Default

4.15

1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.

R/W

4.14

Reserved

Ignore.

4.13

Remote Fault

1 = Remote fault.
0 = No remote fault.

R/W

4.12

Reserved

Ignore.

R/W

4.11

Asymmetric
Pause

Pause operation defined in Clause 40 and 27.

R/W

4.10

Pause

1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.

R/W

Note 2

4.9

100BASE-T4

1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT972A does not support 100BASE-T4 but allows this
bit to be set to advertise in the Auto-Negotiation sequence for
100BASE-T4 operation. An external 100BASE-T4 transceiver
could be switched in if this capability is desired.)

R/W

4.8

100BASE-TX
full-duplex

1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.

R/W

Note 3

4.7

100BASE-TX

1 = Port is 100BASE-TX capable.
0 = Port is not 100BASE-TX capable.

R/W

Note 3

4.6

10BASE-T
full-duplex

1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.

R/W

Note 3

4.5

10BASE-T

1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.

R/W

Note 3

4.4:0

Selector Field,
S<4:0>

<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation
development.
<11111> = Reserved for future Auto-Negotiation
development.
Unspecified or reserved combinations should not be
transmitted.

R/W

00001

1. R/W = Read/Write

RO = Read Only

2. Default value of bit 4.10 is determined by pin 33/H8.
3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to

Table 9

for details.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 44. Auto Negotiation Link Partner Base Page Ability Register (Address 5)

Bit

Name

Description

Type

Default

5.15

1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple pages.

N/A

5.14

Acknowledge

1 = Link Partner has received Link Code Word from
LXT972A.
0 = Link Partner has not received Link Code Word from the
LXT972A.

N/A

5.13

Remote Fault

1 = Remote fault.
0 = No remote fault.

N/A

5.12

Reserved

Ignore.

N/A

5.11

Asymmetric
Pause

Pause operation defined in Clause 40 and 27.
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.

N/A

5.10

Pause

1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.

N/A

5.9

100BASE-T4

1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.

N/A

5.8

100BASE-TX
full-duplex

1 = Link Partner is 100BASE-TX full-duplex capable.
0 = Link Partner is not 100BASE-TX full-duplex capable.

N/A

5.7

100BASE-TX

1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.

N/A

5.6

10BASE-T
full-duplex

1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable.

N/A

5.5

10BASE-T

1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.

N/A

5.4:0

Selector Field
S<4:0>

N/A

1. RO = Read Only

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

Table 45. Auto Negotiation Expansion (Address 6)

Bit

Name

Description

Type

Default

6.15:6

Reserved

Ignore on read.

6.5

Base Page

This bit indicates the status of the Auto-Negotiation variable,
base page. It flags synchronization with the Auto-
Negotiation state diagram allowing detection of interrupted
links. This bit is only used if bit 16.1 (Alternate NP feature)
is set.
1 = basepage = true
0 = basepage = false

RO/

6.4

Parallel
Detection Fault

1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.

RO/

6.3

Link Partner
Next Page Able

1 = Link partner is next page able.
0 = Link partner is not next page able.

6.2

Next Page Able

1 = Local device is next page able.
0 = Local device is not next page able.

6.1

Page Received

1 = Indicates that a new page has been received and the
received code word has been loaded into register 5 (base
pages) or register 8 (next pages) as specified in clause 28 of
802.3. This bit is cleared on read. If bit 16.1 is set, the Page
Received bit is also cleared when mr_page_rx = false or
transmit_disable = true.

RO
LH

6.0

Link Partner A/N
Able

1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.

1. RO = Read Only LH = Latching High

Table 46. Auto Negotiation Next Page Transmit Register (Address 7)

Bit

Name

Description

Type

Default

7.15

Next Page
(NP)

1 = Additional next pages follow
0 = Last page

R/W

7.14

Reserved

Write as 0, ignore on read

7.13

Message Page
(MP)

1 = Message page
0 = Unformatted page

R/W

7.12

Acknowledge 2
(ACK2)

1 = Complies with message
0 = Can not comply with message

R/W

7.11

Toggle
(T)

1 = Previous value of the transmitted Link Code Word
equalled logic zero
0 = Previous value of the transmitted Link Code Word
equalled logic one

R/W

7.10:0

Message/Unformatted
Code Field

R/W

000000000

1. RO = Read Only. R/W = Read/Write

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 47. Auto Negotiation Link Partner Next Page Receive Register (Address 8)

Bit

Name

Description

Type

Default

8.15

Next Page
(NP)

1 = Link Partner has additional next pages to send
0 = Link Partner has no additional next pages to send

8.14

Acknowledge
(ACK)

1 = Link Partner has received Link Code Word from
LXT972A
0 = Link Partner has not received Link Code Word from
LXT972A

8.13

Message Page
(MP)

1 = Page sent by the Link Partner is a Message Page
0 = Page sent by the Link Partner is an Unformatted Page

8.12

Acknowledge 2
(ACK2)

1 = Link Partner complies with the message
0 = Link Partner can not comply with the message

8.11

Toggle
(T)

1 = Previous value of the transmitted Link Code Word
equalled logic zero
0 = Previous value of the transmitted Link Code Word
equalled logic one

8.10:0

Message/Unformatted
Code Field

User definable

1. RO = Read Only.

Table 48. Configuration Register (Address 16, Hex 10)

Bit

Name

Description

Type

Default

16.15

Reserved

Write as zero, ignore on read.

R/W

16.14

Force Link Pass

1 = Force Link pass
0 = Normal operation

R/W

16.13

Transmit Disable

1 = Disable Twisted Pair transmitter
0 = Normal Operation

R/W

16.12

Bypass Scrambler
(100BASE-TX)

1 = Bypass Scrambler and Descrambler
0 = Normal Operation

R/W

16.11

Reserved

Ignore

R/W

16.10

Jabber
(10BASE-T)

1 = Disable Jabber Correction
0 = Normal operation

R/W

16.9

SQE
(10BASE-T)

1 = Enable Heart Beat
0 = Disable Heart Beat

R/W

16.8

TP Loopback
(10BASE-T)

1 = Disable TP loopback during half-duplex operation
0 = Normal Operation

R/W

16.7

CRS Select
(10BASE-T)

1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation

R/W

16.6

Reserved

Write as zero, ignore on read.

R/W

16.5

PRE_EN

Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when CRS is
asserted.

R/W

16.4:3

Reserved

Write as zero, ignore on read.

R/W

1. R/W = Read /Write, LHR = Latches High on Reset

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

16.2

Reserved

Write as zero, ignore on read.

R/W

16.1

Alternate NP
feature

1 = Enable alternate auto negotiate next page feature.
0 = Disable alternate auto negotiate next page feature

R/W

16.0

Reserved

Write as zero, ignore on read.

R/W

Table 49. Status Register #2 (Address 17)

Bit

Name

Description

Type

Default

17.15

Reserved

Always 0.

17.14

10/100 Mode

1 = LXT972A is operating in 100BASE-TX mode.
0 = LXT972A is not operating 100BASE-TX mode.

17.13

Transmit Status

1 = LXT972A is transmitting a packet.
0 = LXT972A is not transmitting a packet.

17.12

Receive Status

1 = LXT972A is receiving a packet.
0 = LXT972A is not receiving a packet.

17.11

Collision Status

1 = Collision is occurring.
0 = No collision.

17.10

Link

1 = Link is up.
0 = Link is down.

17.9

Duplex Mode

1 = Full-duplex.
0 = Half-duplex.

17.8

Auto-Negotiation

1 = LXT972A is in Auto-Negotiation Mode.
0 = LXT972A is in manual mode.

17.7

Auto-Negotiation
Complete

1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
This bit is only valid when auto negotiate is enabled, and
is equivalent to bit 1.5.

17.6

Reserved

Reserved.

17.5

Polarity

1 = Polarity is reversed.
0 = Polarity is not reversed.

17.4

Pause

1 = Device Pause capable.
0 = Device Not Pause capable.

17:3

Error

1 = Error Occurred (Remote Fault, X,Y,Z).
0 = No error occurred.

17:2

Reserved

Always 0.

17:1

Reserved

Always 0.

17.0

Reserved

Always 0.

1. RO = Read Only. R/W = Read/Write

Table 48. Configuration Register (Address 16, Hex 10) (Continued)

Bit

Name

Description

Type

Default

1. R/W = Read /Write, LHR = Latches High on Reset

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

Table 50. Interrupt Enable Register (Address 18)

Bit

Name

Description

Type

Default

18.15:9

Reserved

Write as 0; ignore on read.

R/W

N/A

18.8

Reserved

Write as 0; ignore on read.

R/W

18.7

ANMSK

Mask for Auto Negotiate Complete
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.

R/W

18.6

SPEEDMSK

Mask for Speed Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.

R/W

18.5

DUPLEXMSK

Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.

R/W

18.4

LINKMSK

Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.

R/W

18.3

Reserved

Write as 0, ignore on read.

R/W

18.2

Reserved

Write as 0, ignore on read.

R/W

18.1

INTEN

1 = Enable interrupts.
0 = Disable interrupts.

R/W

18.0

TINT

1 = Force interrupt on MDINT.
0 = Normal operation.

R/W

1. R/W = Read /Write

Table 51. Interrupt Status Register (Address 19, Hex 13)

Bit

Name

Description

Type

Default

19.15:9

Reserved

Ignore

N/A

19.8

Reserved

Ignore

19.7

ANDONE

Auto Negotiation Status
1 = Auto Negotiation has completed.
0 = Auto Negotiation has not completed.

RO/SC

N/A

19.6

SPEEDCHG

Speed Change Status
1 = A Speed Change has occurred since last reading this
register.
0 = A Speed Change has not occurred since last reading this
register.

RO/SC

19.5

DUPLEXCHG

Duplex Change Status
1 = A Duplex Change has occurred since last reading this
register.
0 = A Duplex Change has not occurred since last reading this
register.

RO/SC

1. R/W = Read/Write, SC = Self Clearing.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

19.4

LINKCHG

Link Status Change Status
1 = A Link Change has occurred since last reading this
register.
0 = A Link Change has not occurred since last reading this
register.

RO/SC

19.3

Reserved

Ignore

19.2

MDINT

1 = MII interrupt pending.
0 = No MII interrupt pending.

19.1

Reserved

Ignore.

N/A

19.0

Reserved

Ignore

Table 52. LED Configuration Register (Address 20, Hex 14)

Bit

Name

Description

Type

Default

20.15:12

LED1
Programming
bits

0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Unused
0111 = Display Receive or Transmit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined

(Stretched)

1101 = Display Link and Activity Status combined

(Stretched)

1110 = Display Duplex and Collision Status combined

(Stretched)

1111 = Unused

R/W

0000

1. R/W = Read /Write

RO = Read Only
LH = Latching High

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive or Activity) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched

regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

5. Values are relative approximations. Not guaranteed or production tested.

Table 51. Interrupt Status Register (Address 19, Hex 13) (Continued)

Bit

Name

Description

Type

Default

1. R/W = Read/Write, SC = Self Clearing.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186

Revision #: 003

Rev. Date: August 7, 2002

20.11:8

LED2
Programming
bits

0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status (Default)
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined

(Stretched)

1101 = Display Link and Activity Status combined

(Stretched)

1110 = Display Duplex and Collision Status combined

(Stretched)

1111 = Unused

R/W

0100

20.7:4

LED3
Programming
bits

0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status (Default)
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined

(Stretched)

1101 = Display Link and Activity Status combined

(Stretched)

1110 = Display Duplex and Collision Status combined

(Stretched)

1111 = Unused

R/W

0010

20.3:2

LEDFREQ

00 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved.

R/W

20.1

PULSE-
STRETCH

0 = Disable pulse stretching of all LEDs.
1 = Enable pulse stretching of all LEDs.

R/W

20.0

Reserved

Ignore.

R/W

N/A

Table 52. LED Configuration Register (Address 20, Hex 14) (Continued)

Bit

Name

Description

Type

Default

1. R/W = Read /Write

RO = Read Only
LH = Latching High

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive or Activity) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched

regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

5. Values are relative approximations. Not guaranteed or production tested.

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002

8.0

Product Ordering Information

Table 55. Product Information

Number

Revision

Qualification

Tray MM

Tape & Reel MM

DJLXT972ALC.A4

834109

834917

Figure 38. Ordering Information - Sample

Temperature Range
A
C
E

= Ambient (0 - 55° C)
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)

Product Revision
xn

= 2 Alphanumeric characters

Build Format
E000
E001

= Tray
= Tape and reel

972A

LXT

E001

Internal Package Designator
L
P
N
Q
H
T
B
C
E
K

= LQFP
= PLCC
= DIP
= PQFP
= QFP with heat spreader
= TQFP
= BGA
= CBGA
= TBGA
= HSBGA (BGA with heat slug)

Qualification
Q
S

= Pre-production material
= Production material

IXA Product Prefix
LXT
IXE
IXF
IXP

= PHY layer device
= Switching engine
= Formatting device (MAC)
= Network processor

Intel Package Designator
DJ
FA
FL
FW
HB
HD
HF
HG
S
GC
N

= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= CBGA
= SOIC
= QFP
= TBGA
= PLCC

xxxx

= 3-5 Digit Alphanumeric Product Code

Document Outline

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Document Outline

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