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November 1994

INTEL CORPORATION 1995

Order Number 272430-002

80186 80188

HIGH-INTEGRATION 16-BIT MICROPROCESSORS

Integrated Feature Set

Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller

Available in 10 MHz and 8 MHz
Versions

High-Performance Processor

4 Mbyte Sec Bus Bandwidth
Interface

8 MHz (80186)

5 Mbyte Sec Bus Bandwidth
Interface

10 MHz (80186)

Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O

Completely Object Code Compatible
with All Existing 8086 8088 Software

10 New Instruction Types

Numerics Coprocessing Capability
Through 8087 Interface

Available in 68 Pin

Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)

Available in EXPRESS

Standard Temperature with Burn-In
Extended Temperature Range
(

40 C to

85 C)

272430 1

Figure 1 Block Diagram

80186 80188

Table 1 Pin Descriptions

Symbol

Type

Name and Function

SYSTEM POWER

5 volt power supply

System Ground

RESET

Reset Output indicates that the CPU is being reset and can be used as a system
reset It is active HIGH synchronized with the processor clock and lasts an
integer number of clock periods corresponding to the length of the RES signal

Crystal Inputs X1 and X2 provide external connections for a fundamental mode
parallel resonant crystal for the internal oscillator Instead of using a crystal an

external clock may be applied to X1 while minimizing stray capacitance on X2
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT)

CLKOUT

Clock Output provides the system with a 50% duty cycle waveform All device
pin timings are specified relative to CLKOUT

RES

An active RES causes the processor to immediately terminate its present
activity clear the internal logic and enter a dormant state This signal may be
asynchronous to the processor clock The processor begins fetching
instructions approximately 6

clock cycles after RES is returned HIGH For

proper initialization V

must be within specifications and the clock signal must

be stable for more than 4 clocks with RES held LOW RES is internally
synchronized This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network

TEST

I O

TEST is examined by the WAIT instruction If the TEST input is HIGH when
``WAIT'' execution begins instruction execution will suspend TEST will be
resampled until it goes LOW at which time execution will resume If interrupts
are enabled while the processor is waiting for TEST interrupts will be serviced
During power-up active RES is required to configure TEST as an input This pin
is synchronized internally

TMR IN 0

Timer Inputs are used either as clock or control signals depending upon the
programmed timer mode These inputs are active HIGH (or LOW-to-HIGH

TMR IN 1

transitions are counted) and internally synchronized

TMR OUT 0

Timer outputs are used to provide single pulse or continous waveform
generation depending upon the timer mode selected

TMR OUT 1

DRQ0

DMA Request is asserted HIGH by an external device when it is ready for DMA
Channel 0 or 1 to perform a transfer These signals are level-triggered and

DRQ1

internally synchronized

NMI

The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition
from LOW to HIGH is latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be asserted for at least one
clock The Non-Maskable Interrupt cannot be avoided by programming

INT0

Maskable Interrupt Requests can be requested by activating one of these pins
When configured as inputs these pins are active HIGH Interrupt Requests are

INT1 SELECT

synchronized internally INT2 and INT3 may be configured to provide active-

INT2 INTA0

I O

LOW interrupt-acknowledge output signals All interrupt inputs may be

INT3 INTA1 IRQ

I O

configured to be either edge- or level-triggered To ensure recognition all
interrupt requests must remain active until the interrupt is acknowledged When
Slave Mode is selected the function of these pins changes (see Interrupt
Controller section of this data sheet)

NOTE
Pin names in parentheses apply to the 80188

80186 80188

Table 1 Pin Descriptions

(Continued)

Symbol

Type

Name and Function

A19 S6

Address Bus Outputs (1619) and Bus Cycle Status (36) indicate the four most
significant address bits during T

These signals are active HIGH During T

A18 S5

and T

the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a

A17 S4

DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW

A16 S3

The status pins float during bus HOLD or RESET

AD15 (A15)

I O

Address Data Bus signals constitute the time multiplexed memory or I O address (T

)

and data (T

and T

) bus The bus is active HIGH A

is analogous to BHE for

AD14 (A14)

I O

the lower byte of the data bus pins D

through D

It is LOW during T

when a byte is

AD13 (A13)

I O

to be transferred onto the lower portion of the bus in memory or I O operations BHE

AD12 (A12)

I O

does not exist on the 80188 as the data bus is only 8 bits wide

AD11 (A11)

I O

AD10 (A10)

I O

AD9 (A9)

I O

AD8 (A8)

I O

AD7

I O

AD6

I O

AD5

I O

AD4

I O

AD3

I O

AD2

I O

AD1

I O

AD0

I O

BHE S7

During T

the Bus High Enable signal should be used to determine if data is to be

enabled onto the most significant half of the data bus pins D

BHE is LOW

(S7)

during T

for read write and interrupt acknowledge cycles when a byte is to be

transferred on the higher half of the bus The S

status information is available during

and T

is logically equivalent to BHE BHE S7 floats during HOLD On the

80188 S7 is high during normal operation

BHE and A0 Encodings (80186 Only)

BHE

Function

Value

Word Transfer

Byte Transfer on upper half of data bus (D15D8)

Byte Transfer on lower half of data bus (D

)

Reserved

ALE QS0

Address Latch Enable Queue Status 0 is provided by the processor to latch the
address ALE is active HIGH Addresses are guaranteed to be valid on the trailing
edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T

of the associated bus cycle effectively one-half clock cycle

earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in
T

as in the 8086 Note that ALE is never floated

WR QS1

Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I O device WR is active for T

and T

of any write cycle It is active

LOW and floats during HOLD When the processor is in queue status mode the ALE
QS0 and WR QS1 pins provide information about processor instruction queue
interaction

QS1

QS0

Queue Operation

No queue operation

First opcode byte fetched from the queue

Subsequent byte fetched from the queue

Empty the queue

NOTE
Pin names in parentheses apply to the 80188

80186 80188

Table 1 Pin Descriptions

(Continued)

Symbol

Type

Name and Function

RD QSMD

I O

Read Strobe is an active LOW signal which indicates that the processor is
performing a memory or I O read cycle It is guaranteed not to go LOW
before the A D bus is floated An internal pull-up ensures that RD is HIGH
during RESET Following RESET the pin is sampled to determine whether
the processor is to provide ALE RD and WR or queue status information
To enable Queue Status Mode RD must be connected to GND RD will
float during bus HOLD

ARDY

Asynchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT and is active HIGH The
falling edge of ARDY must be synchronized to the processor clock
Connecting ARDY HIGH will always assert the ready condition to the CPU
If this line is unused it should be tied LOW to yield control to the SRDY pin

SRDY

Synchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT The use of SRDY allows a
relaxed system timing over ARDY This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal Connecting SRDY high will always assert the ready condition to the
CPU If this line is unused it should be tied LOW to yield control to the
ARDY pin

LOCK

LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix It remains active until the completion of that instruction No
instruction prefetching will occur while LOCK is asserted When executing
more than one LOCK instruction always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction LOCK is driven HIGH for one clock during RESET
and then floated

Bus cycle status S0 S2 are encoded to provide bus-transaction
information

Bus Cycle Status Information

Bus Cycle Initiated

Interrupt Acknowledge

Read I O

Write I O

Halt

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

The status pins float during HOLD
S2 may be used as a logical M IO indicator and S1 as a DT R indicator

NOTE
Pin names in parentheses apply to the 80188

80186 80188

Table 1 Pin Descriptions

(Continued)

Symbol

Type

Name and Function

HOLD

HOLD indicates that another bus master is requesting the local bus The
HOLD input is active HIGH HOLD may be asynchronous with respect to the

HLDA

processor clock The processor will issue a HLDA (HIGH) in response to a
HOLD request at the end of T

or T

Simultaneous with the issuance of

HLDA the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will lower HLDA When the processor
needs to run another bus cycle it will again drive the local bus and control
lines

UCS

Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K 256K block) of memory
This line is not floated during bus HOLD The address range activating UCS is
software programmable

LCS

Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K 256K) of memory This line is not
floated during bus HOLD The address range activating LCS is software
programmable

MCS0

Mid-Range Memory Chip Select signals are active LOW when a memory
reference is made to the defined mid-range portion of memory (8K 512K)

MCS1

These lines are not floated during bus HOLD The address ranges activating

MCS2

MCS0 3 are software programmable

MCS3

PCS0

Peripheral Chip Select signals 0 4 are active LOW when a reference is made
to the defined peripheral area (64 Kbyte I O space) These lines are not

PCS1

floated during bus HOLD The address ranges activating PCS0 4 are

PCS2

software programmable

PCS3

PCS4

PCS5 A1

Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select or to provide an internally latched A1 signal The
address range activating PCS5 is software-programmable PCS5 A1 does
not float during bus HOLD When programmed to provide latched A1 this pin
will retain the previously latched value during HOLD

PCS6 A2

Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select or to provide an internally latched A2 signal
The address range activating PCS6 is software programmable PCS6 A2
does not float during bus HOLD When programmed to provide latched A2
this pin will retain the previously latched value during HOLD

DT R

Data Transmit Receive controls the direction of data flow through an
external data bus transceiver When LOW data is transferred to the
processsor When HIGH the processor places write data on the data bus

DEN

Data Enable is provided as a data bus transceiver output enable DEN is
active LOW during each memory and I O access DEN is HIGH whenever
DT R changes state During RESET DEN is driven HIGH for one clock then
floated DEN also floats during HOLD

NOTE
Pin names in parentheses apply to the 80188

80186 80188

FUNCTIONAL DESCRIPTION

Introduction

The following Functional Description describes the
base architecture of the 80186 The 80186 is a very
high integration 16-bit microprocessor It combines
15 20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086 The 80186 is ob-
ject code compatible with the 8086 8088 microproc-
essors and adds 10 new instruction types to the
8086 8088 instruction set

For more detailed information on the architecture
please refer to the 80C186XL 80C188XL User's
Manual The 80186 and the 80186XL devices are
functionally and register compatible

CLOCK GENERATOR

The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter

synchronous and asynchronous

ready inputs and reset circuitry

Oscillator

The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal This is
used as the time base for the processor The crystal
frequency selected will be double the CPU clock fre-
quency Use of an LC or RC circuit is not recom-
mended with this oscillator If an external oscillator is
used it can be connected directly to the input pin X1
in lieu of a crystal The output of the oscillator is not
directly available outside the processor The recom-
mended crystal configuration is shown in Figure 5

80186-10 (10 MHz) 20

272430 5

80186

(8 MHz) 16

Figure 5 Recommended

Crystal Configuration

Intel recommends the following values for crystal se-
lection parameters

Temperature Range

0 to 70 C

ESR (Equivalent Series Resistance)

30X max

(Shunt Capacitance of Crystal)

7 0 pf max

(Load Capacitance)

20 pf

2 pf

Drive Level

1 mW max

Clock Generator

The clock generator provides the 50% duty cycle
processor clock for the processor It does this by
dividing the oscillator output by 2 forming the sym-
metrical clock If an external oscillator is used the
state of the clock generator will change on the fall-
ing edge of the oscillator signal The CLKOUT pin
provides the processor clock signal for use outside
the device This may be used to drive other system
components All timings are referenced to the output
clock

READY Synchronization

The processor provides both synchronous and asyn-
chronous ready inputs In addition the processor as
part of the integrated chip-select logic has the capa-
bility to program WAIT states for memory and
peripheral blocks

RESET Logic

The processor provides both a RES input pin and a
synchronized RESET output pin for use with other
system components The RES input pin is provided
with hysteresis in order to facilitate power-on Reset
generation via an RC network RESET output is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks

LOCAL BUS CONTROLLER

The processor provides a local bus controller to
generate the local bus control signals In addition it
employs a HOLD HLDA protocol for relinquishing
the local bus to other bus masters It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus

80186 80188

Memory Peripheral Control

The processor provides ALE RD and WR bus con-
trol signals The RD and WR signals are used to
strobe data from memory or I O to the processor or
to strobe data from the processor to memory or I O
The ALE line provides a strobe to latch the address
when it is valid The local bus controller does not
provide a memory I O signal If this is required use
the S2 signal (which will require external latching)
make the memory and I O spaces nonoverlapping
or use only the integrated chip-select circuitry

Local Bus Arbitration

The processor uses a HOLD HLDA system of local
bus exchange This provides an asynchronous bus
exchange mechanism This means multiple masters
utilizing the same bus can operate at separate clock
frequencies

The processor provides a single

HOLD HLDA pair through which all other bus mas-
ters may gain control of the local bus External cir-
cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter-
nate local bus master When the processor relin-
quishes control of the local bus it floats DEN RD
WR

S0 S2

LOCK

AD0 AD15

(AD0 AD7)

A16 A19 (A8 A19) BHE (S7) and DT R to allow
another master to drive these lines directly

Local Bus Controller and Reset

During RESET the local bus controller will perform
the following action

Drive DEN RD and WR HIGH for one clock cy-
cle then float

NOTE

RD is also provided with an internal pull-up de-
vice to prevent the processor from inadvertently
entering Queue Status Mode during RESET

Drive S0 S2 to the inactive state (all HIGH) and
then float

Drive LOCK HIGH and then float

Float AD0 15 (AD0 AD7) A16 19 (A8A19)
BHE (S7) DT R

Drive ALE LOW (ALE is never floated)

Drive HLDA LOW

PERIPHERAL ARCHITECTURE

All of the integrated peripherals are controlled by
16-bit registers contained within an internal 256-byte
control block The control block may be mapped into

either memory or I O space Internal logic will recog-
nize control block addresses and respond to bus cy-
cles During bus cycles to internal registers the bus
controller will signal the operation externally (i e the
RD WR status address data etc lines will be driv-
en as in a normal bus cycle) but D

150

)

SRDY and ARDY will be ignored The base address
of the control block must be on an even 256-byte
boundary (i e the lower 8 bits of the base address
are all zeros)

The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
control block It provides the upper 12 bits of the
base address of the control block

In addition to providing relocation information for the
control block the relocation register contains bits
which place the interrupt controller into Slave Mode
and cause the CPU to interrupt upon encountering
ESC instructions

Chip-Select Ready Generation Logic

The

processor contains logic which provides

programmable chip-select generation for both mem-
ories and peripherals In addition it can be pro-
grammed to provide READY (or WAIT state) genera-
tion It can also provide latched address bits A1 and
A2 The chip-select lines are active for all memory
and I O cycles in their programmed areas whether
they be generated by the CPU or by the integrated
DMA unit

MEMORY CHIP SELECTS

The processor provides 6 memory chip select out-
puts for 3 address areas upper memory lower
memory and midrange memory One each is provid-
ed for upper memory and lower memory while four
are provided for midrange memory

UPPER MEMORY CS

The processor provides a chip select called UCS
for the top of memory The top of memory is usually
used as the system memory because after reset the
processor begins executing at memory location
FFFF0H

LOWER MEMORY CS

The processor provides a chip select for low memo-
ry called LCS The bottom of memory contains the
interrupt vector table starting at location 00000H

80186 80188

The lower limit of memory defined by this chip select
is always 0H while the upper limit is programmable
By programming the upper limit the size of the
memory block is defined

MID-RANGE MEMORY CS

The processor provides four MCS lines which are
active within a user-locatable memory block This
block can be located within the 1-Mbyte memory ad-
dress space exclusive of the areas defined by UCS
and LCS Both the base address and size of this
memory block are programmable

PERIPHERAL CHIP SELECTS

The processor can generate chip selects for up to
seven peripheral devices These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address The base address
may be located in either memory or I O space Sev-
en CS lines called PCS0 6 are generated by the
processor

PCS5 and PCS6 can also be pro-

grammed to provide latched address bits A1 and A2
If so programmed they cannot be used as peripher-
al selects These outputs can be connected directly
to the A0 and A1 pins used for selecting internal
registers of 8-bit peripheral chips

READY GENERATION LOGIC

The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0 3 wait states for all accesses to the area for
which the chip select is active In addition the proc-
essor may be programmed to either ignore external
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator

CHIP SELECT READY LOGIC AND RESET

Upon RESET the Chip-Select Ready Logic will per-
form the following actions

All chip-select outputs will be driven HIGH

Upon leaving RESET the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i e UMCS resets to FFFBH)

No other chip select or READY control registers
have any predefined values after RESET They
will not become active until the CPU accesses
their control registers Both the PACS and MPCS
registers must be accessed before the PCS lines
will become active

DMA Channels

The DMA controller provides two independent DMA
channels Data transfers can occur between memo-
ry and I O spaces (e g Memory to I O) or within the
same space (e g Memory to Memory or I O to I O)
Data can be transferred either in bytes or in words
(80186 only) to or from even or odd addresses
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers)
Each data transfer consumes 2 bus cycles (a mini-
mum of 8 clocks) one cycle to fetch data and the
other to store data This provides a maximum data
transfer rate of 1 25 Mword sec or 2 5 Mbytes sec
at 10 MHz (half of this rate for the 80188)

DMA CHANNELS AND RESET

Upon RESET the DMA channels will perform the
following actions

The Start Stop bit for each channel will be reset
to STOP

Any transfer in progress is aborted

Timers

The processor provides three internal 16-bit pro-
grammable timers Two of these are highly flexible
and are connected to four external pins (2 per timer)
They can be used to count external events time ex-
ternal events generate nonrepetitive waveforms
etc The third timer is not connected to any external
pins and is useful for real-time coding and time de-
lay applications In addition the third timer can be
used as a prescaler to the other two or as a DMA
request source

80186 80188

TIMERS AND RESET

Upon RESET the Timers will perform the following
actions

All EN (Enable) bits are reset preventing timer
counting

For Timers 0 and 1 the RIU bits are reset to zero
and the ALT bits are set to one This results in the
Timer Out pins going high

Interrupt Controller

The processor can receive interrupts from a number
of sources both internal and external The internal
interrupt controller serves to merge these requests
on a priority basis for individual service by the CPU

Internal interrupt sources (Timers and DMA chan-
nels) can be disabled by their own control registers
or by mask bits within the interrupt controller The
interrupt controller has its own control register that
sets the mode of operation for the controller

INTERRUPT CONTROLLER AND RESET

Upon RESET the interrupt controller will perform
the following actions

All SFNM bits reset to 0 implying Fully Nested
Mode

All PR bits in the various control registers set to 1
This places all sources at lowest priority (level
111)

All LTM bits reset to 0 resulting in edge-sense
mode

All Interrupt Service bits reset to 0

All Interrupt Request bits reset to 0

All MSK (Interrupt Mask) bits set to 1 (mask)

All C (Cascade) bits reset to 0 (non-Cascade)

All PRM (Priority Mask) bits set to 1 implying no
levels masked

Initialized to Master Mode

80186 80188

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature under Bias

0 C to 70 C

Storage Temperature

65 C to a150 C

Voltage on any Pin with

Respect to Ground

1 0V to a7V

Power Dissipation

NOTICE This is a production data sheet The specifi-
cations are subject to change without notice

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

D C CHARACTERISTICS

0 C to a70 C V

10%)

Applicable to 8 MHz and 10 MHz devices

Symbol

Parameter

Min

Max

Units

Test Conditions

Input Low Voltage

0 5

0 8

Input High Voltage

2 0

0 5

(All except X1 and (RES)

IH1

Input High Voltage (RES)

3 0

0 5

Output Low Voltage

0 45

2 5 mA for S0 S2

2 0 mA for all other Outputs

Output High Voltage

2 4

e b

400 mA

Power Supply Current

600

e b

40 C

550

0 C

415

e a

70 C

Input Leakage Current

Output Leakage Current

0 45V

OUT

CLO

Clock Output Low

0 6

4 0 mA

CHO

Clock Output High

4 0

e b

200 mA

CLI

Clock Input Low Voltage

0 5

0 6

CHI

Clock Input High Voltage

3 9

1 0

Input Capacitance

I O Capacitance

For extended temperature parts only

80186 80188

A C CHARACTERISTICS

0 C to a70 C V

10%)

Timing Requirements

All Timings Measured At 1 5V Unless Otherwise Noted

Symbol

Parameter

8 MHz

10 MHz

Units

Conditions

Test

Min

Max

Min

Max

DVCL

Data in Setup (A D)

CLDX

Data in Hold (A D)

ARYHCH

Asynchronous Ready

(ARDY) Active Setup
Time

(1)

ARYLCL

ARDY Inactive Setup Time

CLARX

ARDY Hold Time

ARYCHL

Asynchronous Ready

Inactive Hold Time

SRYCL

Synchronous Ready (SRDY)

Transition Setup Time

(2)

CLSRY

SRDY Transition Hold

Time

(2)

HVCL

HOLD Setup

(1)

INVCH

INTR NMI TEST TIM IN

Setup

(1)

INVCL

DRQ0 DRQ1 Setup

(1)

Master Interface Timing Responses

CLAV

Address Valid Delay

20 pF200 pF

all Outputs

CLAX

Address Hold

(Except T

CLTMV

)

8 MHz and 10 MHz

CLAZ

Address Float Delay

CLAX

CHCZ

Command Lines Float Delay

CHCV

Command Lines Valid Delay

(after Float)

LHLL

ALE Width

CLCL

CHLH

ALE Active Delay

CHLL

ALE Inactive Delay

LLAX

Address Hold from ALE

CHCL

Inactive

CLDV

Data Valid Delay

CLDOX

Data Hold Time

WHDX

Data Hold after WR

CLCL

CVCTV

Control Active Delay 1

CHCTV

Control Active Delay 2

CVCTX

Control Inactive Delay

CVDEX

DEN Inactive Delay

(Non-Write Cycle)

1 To guarantee recognition at next clock
2 To guarantee proper operation

80186 80188

A C CHARACTERISTICS

0 C to a70 C V

10%) (Continued)

Master Interface Timing Responses

(Continued)

Symbol

Parameter

8 MHz

10 MHz

Units

Conditions

Test

Min

Max

Min

Max

AZRL

Address Float to RD Active

CLRL

RD Active Delay

CLRH

RD Inactive Delay

RHAV

RD Inactive to Address

CLCL

Active

CLHAV

HLDA Valid Delay

RLRH

RD Width

CLCL

WLWH

WR Width

CLCL

AVLL

Address Valid to ALE Low

CLCH

CHSV

Status Active Delay

CLSH

Status Inactive Delay

CLTMV

Timer Output Delay

100 pF max

10 MHz

CLRO

Reset Delay

CHQSV

Queue Status Delay

CHDX

Status Hold Time

AVCH

Address Valid to Clock High

CLLV

LOCK Valid Invalid Delay

Chip-Select Timing Responses

CLCSV

Chip-Select Active Delay

CXCSX

Chip-Select Hold from

Command Inactive

CHCSX

Chip-Select Inactive Delay

CLKIN Requirements

CKIN

CLKIN Period

62 5

250

CKHL

CLKIN Fall Time

3 5 to 1 0V

CKLH

CLKIN Rise Time

1 0 to 3 5V

CLCK

CLKIN Low Time

1 5V

CHCK

CLKIN High Time

1 5V

CLKOUT Timing (200 pF load)

CICO

CLKIN to CLKOUT Skew

CLCL

CLKOUT Period

125

500

100

500

CLCH

CLKOUT Low Time

CLCL

7 5

CLCL

6 0

1 5V

CHCL

CLKOUT High Time

CLCL

7 5

CLCL

6 0

1 5V

CH1CH2

CLKOUT Rise Time

1 0 to 3 5V

CL2CL1

CLKOUT Fall Time

3 5 to 1 0V

80186 80188

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has from 5 to 7 characters The
first character is always a ``T'' (stands for time) The
other characters

depending on their positions

stand for the name of a signal or the logical status of
that signal The following is a list of all the charac-
ters and what they stand for

Address

ARY Asynchronous Ready Input
C

Clock Output

Clock Input

Chip Select

Control (DT R DEN

)

Data Input

DEN

Logic Level High

Input (DRQ0 TIM0

)

Logic Level Low or ALE

Output

Queue Status (QS1 QS2)

RD signal RESET signal

Status (S0 S1 S2)

SRY Synchronous Ready Input
V

Valid

WR Signal

No Longer a Valid Logic Level

Float

Examples

CLAV

Time from Clock low to Address valid

CHLH

Time from Clock high to ALE high

CLCSV

Time from Clock low to Chip Select valid

80186 80188

WAVEFORMS

(Continued)

272430 17

EXPRESS

The Intel EXPRESS system offers enhancements to
the operational specifications of the microprocessor
EXPRESS products are designed to meet the needs
of those applications whose operating requirements
exceed commercial standards

The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range without burn-in

With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to a70 C With the ex-
tended temperature range option operational char-
acteristics are guaranteed over the range of b40 C
to a85 C

The optional burn-in is dynamic for a minimum time
of 160 hours at a125 C with V

5 5V

0 25V

following guidelines in MIL-STD-883 Method 1015

Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number The
prefixes are listed in Table 2 All A C and D C speci-
fications not mentioned in this section are the same
for both commercial and EXPRESS parts

Table 2 Prefix Identification

Prefix

Package

Temperature

Burn-In

Type

Range

PGA

Commercial

PLCC

Commercial

LCC

Commercial

PGA

Extended

PGA

Commercial

Yes

LCC

Commercial

Yes

NOTE
Not all package temperature range speed combinations
are available

80186 80188

EXECUTION TIMINGS

A determination of program execution timing must
consider the bus cycles necessary to prefetch in-
structions as well as the number of execution unit
cycles necessary to execute instructions The fol-
lowing instruction timings represent the minimum ex-
ecution time in clock cycles for each instruction The
timings given are based on the following assump-
tions

The opcode along with any data or displacement
required for execution of a particular instruction
has been prefetched and resides in the queue at
the time it is needed

No wait states or bus HOLDS occur

All word-data is located on even-address bound-
aries

All instructions which involve memory accesses can
also require one or two additional clocks above the
minimum timings shown due to the asynchronous
handshake between the bus interface unit (BIU) and
execution unit

All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address

The 80186 has sufficient bus performance to ensure
that an adequate number of prefetched bytes will
reside in the queue (6 bytes) most of the time
Therefore actual program execution time will not be
substantially greater than that derived from adding
the instruction timings shown

The 80188 is noticeably limited in its performance
relative to the execution unit A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time Therefore actual
program execution time may be substantially greater
than that derived from adding the instruction timings
shown

80186 80188

INSTRUCTION SET SUMMARY

80186

80188

Function

Format

Clock

Comments

Cycles

DATA TRANSFER
MOV

Move

1 0 0 0 1 0 0 w

mod reg r m

2 12

1 0 0 0 1 0 1 w

mod reg r m

2 9

Immediate to register memory

1 1 0 0 0 1 1 w

mod 000 r m

data

data if w

12 13

8 16-bit

Immediate to register

1 0 1 1 w reg

data

data if w

3 4

8 16-bit

Memory to accumulator

1 0 1 0 0 0 0 w

addr-low

addr-high

Accumulator to memory

1 0 1 0 0 0 1 w

addr-low

addr-high

1 0 0 0 1 1 1 0

mod 0 reg r m

2 9

2 13

Segment register to register memory

1 0 0 0 1 1 0 0

mod 0 reg r m

2 11

2 15

PUSH

Push

Memory

1 1 1 1 1 1 1 1

mod 1 1 0 r m

0 1 0 1 0 reg

Segment register

0 0 0 reg 1 1 0

Immediate

0 1 1 0 1 0 s 0

data

data if s

PUSHA

Push All

0 1 1 0 0 0 0 0

POP

Pop

Memory

1 0 0 0 1 1 1 1

mod 0 0 0 r m

0 1 0 1 1 reg

Segment register

0 0 0 reg 1 1 1

(reg

01)

POPA

Pop All

0 1 1 0 0 0 0 1

XCHG

Exchange

1 0 0 0 0 1 1 w

mod reg r m

4 17

1 0 0 1 0 reg

Input from

Fixed port

1 1 1 0 0 1 0 w

port

Variable port

1 1 1 0 1 1 0 w

OUT

Output to

Fixed port

1 1 1 0 0 1 1 w

port

Variable port

1 1 1 0 1 1 1 w

XLAT

Translate byte to AL

1 1 0 1 0 1 1 1

LEA

Load EA to register

1 0 0 0 1 1 0 1

mod reg r m

LDS

Load pointer to DS

1 1 0 0 0 1 0 1

mod reg r m

(mod

11)

LES

Load pointer to ES

1 1 0 0 0 1 0 0

mod reg r m

(mod

11)

LAHF

Load AH with flags

1 0 0 1 1 1 1 1

SAHF

Store AH into flags

1 0 0 1 1 1 1 0

PUSHF

Push flags

1 0 0 1 1 1 0 0

POPF

Pop flags

1 0 0 1 1 1 0 1

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

80186 80188

INSTRUCTION SET SUMMARY

(Continued)

80186

80188

Function

Format

Clock

Comments

Cycles

DATA TRANSFER

(Continued)

SEGMENT

Segment Override

0 0 1 0 1 1 1 0

0 0 1 1 0 1 1 0

0 0 1 1 1 1 1 0

0 0 1 0 0 1 1 0

ARITHMETIC
ADD

Add

Reg memory with register to either

0 0 0 0 0 0 d w

mod reg r m

3 10

Immediate to register memory

1 0 0 0 0 0 s w

mod 0 0 0 r m

data

data if s w

4 16

Immediate to accumulator

0 0 0 0 0 1 0 w

data

data if w

3 4

8 16-bit

ADC

Add with carry

Reg memory with register to either

0 0 0 1 0 0 d w

mod reg r m

3 10

Immediate to register memory

1 0 0 0 0 0 s w

mod 0 1 0 r m

data

data if s w

4 16

Immediate to accumulator

0 0 0 1 0 1 0 w

data

data if w

3 4

8 16-bit

INC

Increment

1 1 1 1 1 1 1 w

mod 0 0 0 r m

3 15

0 1 0 0 0 reg

SUB

Subtract

Reg memory and register to either

0 0 1 0 1 0 d w

mod reg r m

3 10

Immediate from register memory

1 0 0 0 0 0 s w

mod 1 0 1 r m

data

data if s w

4 16

Immediate from accumulator

0 0 1 0 1 1 0 w

data

data if w

3 4

8 16-bit

SBB

Subtract with borrow

Reg memory and register to either

0 0 0 1 1 0 d w

mod reg r m

3 10

Immediate from register memory

1 0 0 0 0 0 s w

mod 0 1 1 r m

data

data if s w

4 16

Immediate from accumulator

0 0 0 1 1 1 0 w

data

data if w

3 4

8 16-bit

DEC

Decrement

1 1 1 1 1 1 1 w

mod 0 0 1 r m

3 15

0 1 0 0 1 reg

CMP

Compare

0 0 1 1 1 0 1 w

mod reg r m

3 10

0 0 1 1 1 0 0 w

mod reg r m

3 10

Immediate with register memory

1 0 0 0 0 0 s w

mod 1 1 1 r m

data

data if s w

3 10

Immediate with accumulator

0 0 1 1 1 1 0 w

data

data if w

3 4

8 16-bit

NEG

Change sign register memory

1 1 1 1 0 1 1 w

mod 0 1 1 r m

3 10

AAA

ASCII adjust for add

0 0 1 1 0 1 1 1

DAA

Decimal adjust for add

0 0 1 0 0 1 1 1

AAS

ASCII adjust for subtract

0 0 1 1 1 1 1 1

DAS

Decimal adjust for subtract

0 0 1 0 1 1 1 1

MUL

Multiply (unsigned)

1 1 1 1 0 1 1 w

mod 100 r m

2628

3537

Memory-Byte

3234

Memory-Word

4143

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

80186 80188

INSTRUCTION SET SUMMARY

(Continued)

80186

80188

Function

Format

Clock

Comments

Cycles

ARITHMETIC

(Continued)

IMUL

Integer multiply (signed)

1 1 1 1 0 1 1 w

mod 1 0 1 r m

2528

3437

Memory-Byte

3134

Memory-Word

4043

IMUL

Integer Immediate multiply

0 1 1 0 1 0 s 1

mod reg r m

data

data if s

2225

(signed)

2932

DIV

Divide (unsigned)

1 1 1 1 0 1 1 w

mod 1 1 0 r m

Memory-Byte

Memory-Word

IDIV

Integer divide (signed)

1 1 1 1 0 1 1 w

mod 1 1 1 r m

4452

5361

Memory-Byte

5058

Memory-Word

5967

AAM

ASCII adjust for multiply

1 1 0 1 0 1 0 0

0 0 0 0 1 0 1 0

AAD

ASCII adjust for divide

1 1 0 1 0 1 0 1

0 0 0 0 1 0 1 0

CBW

Convert byte to word

1 0 0 1 1 0 0 0

CWD

Convert word to double word

1 0 0 1 1 0 0 1

LOGIC
Shift Rotate Instructions

1 1 0 1 0 0 0 w

mod TTT r m

2 15

1 1 0 1 0 0 1 w

mod TTT r m

n 17

n 5

n 17

1 1 0 0 0 0 0 w

mod TTT r m

count

n 17

n 5

n 17

TTT Instruction
0 0 0

ROL

0 0 1

ROR

0 1 0

RCL

0 1 1

RCR

1 0 0

SHL SAL

1 0 1

SHR

1 1 1

SAR

AND

And

Reg memory and register to either

0 0 1 0 0 0 d w

mod reg r m

3 10

Immediate to register memory

1 0 0 0 0 0 0 w

mod 1 0 0 r m

data

data if w

4 16

Immediate to accumulator

0 0 1 0 0 1 0 w

data

data if w

3 4

8 16-bit

TEST

And function to flags no result

1 0 0 0 0 1 0 w

mod reg r m

3 10

Immediate data and register memory

1 1 1 1 0 1 1 w

mod 0 0 0 r m

data

data if w

4 10

Immediate data and accumulator

1 0 1 0 1 0 0 w

data

data if w

3 4

8 16-bit

Reg memory and register to either

0 0 0 0 1 0 d w

mod reg r m

3 10

Immediate to register memory

1 0 0 0 0 0 0 w

mod 0 0 1 r m

data

data if w

4 16

Immediate to accumulator

0 0 0 0 1 1 0 w

data

data if w

3 4

8 16-bit

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

80186 80188

INSTRUCTION SET SUMMARY

(Continued)

80186

80188

Function

Format

Clock

Comments

Cycles

LOGIC

(Continued)

XOR

Exclusive or

Reg memory and register to either

0 0 1 1 0 0 d w

mod reg r m

3 10

Immediate to register memory

1 0 0 0 0 0 0 w

mod 1 1 0 r m

data

data if w

4 16

Immediate to accumulator

0 0 1 1 0 1 0 w

data

data if w

3 4

8 16-bit

NOT

Invert register memory

1 1 1 1 0 1 1 w

mod 0 1 0 r m

3 10

STRING MANIPULATION

MOVS

Move byte word

1 0 1 0 0 1 0 w

CMPS

Compare byte word

1 0 1 0 0 1 1 w

SCAS

Scan byte word

1 0 1 0 1 1 1 w

LODS

Load byte wd to AL AX

1 0 1 0 1 1 0 w

STOS

Store byte wd from AL AX

1 0 1 0 1 0 1 w

INS

Input byte wd from DX port

0 1 1 0 1 1 0 w

OUTS

Output byte wd to DX port

0 1 1 0 1 1 1 w

Repeated by count in CX (REP REPE REPZ REPNE REPNZ)

MOVS

Move string

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 w

CMPS

Compare string

1 1 1 1 0 0 1 z

1 0 1 0 0 1 1 w

22n

SCAS

Scan string

1 1 1 1 0 0 1 z

1 0 1 0 1 1 1 w

15n

LODS

Load string

1 1 1 1 0 0 1 0

1 0 1 0 1 1 0 w

11n

STOS

Store string

1 1 1 1 0 0 1 0

1 0 1 0 1 0 1 w

INS

Input string

1 1 1 1 0 0 1 0

0 1 1 0 1 1 0 w

OUTS

Output string

1 1 1 1 0 0 1 0

0 1 1 0 1 1 1 w

CONTROL TRANSFER

CALL

Call

Direct within segment

1 1 1 0 1 0 0 0

disp-low

disp-high

1 1 1 1 1 1 1 1

mod 0 1 0 r m

13 19

17 27

indirect within segment

Direct intersegment

1 0 0 1 1 0 1 0

segment offset

segment selector

Indirect intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r m

(mod

11)

JMP

Unconditional jump

Short long

1 1 1 0 1 0 1 1

disp-low

Direct within segment

1 1 1 0 1 0 0 1

disp-low

disp-high

1 1 1 1 1 1 1 1

mod 1 0 0 r m

11 17

11 21

indirect within segment

Direct intersegment

1 1 1 0 1 0 1 0

segment offset

segment selector

Indirect intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r m

(mod

11)

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

80186 80188

INSTRUCTION SET SUMMARY

(Continued)

80186

80188

Function

Format

Clock

Comments

Cycles

CONTROL TRANSFER

(Continued)

RET

Return from CALL

Within segment

1 1 0 0 0 0 1 1

Within seg adding immed to SP

1 1 0 0 0 0 1 0

data-low

data-high

Intersegment

1 1 0 0 1 0 1 1

Intersegment adding immediate to SP

1 1 0 0 1 0 1 0

data-low

data-high

JE JZ

Jump on equal zero

0 1 1 1 0 1 0 0

disp

4 13

JMP not

JL JNGE

Jump on less not greater or equal

0 1 1 1 1 1 0 0

disp

4 13

taken JMP

JLE JNG

Jump on less or equal not greater

0 1 1 1 1 1 1 0

disp

4 13

taken

JB JNAE

Jump on below not above or equal

0 1 1 1 0 0 1 0

disp

4 13

JBE JNA

Jump on below or equal not above

0 1 1 1 0 1 1 0

disp

4 13

JP JPE

Jump on parity parity even

0 1 1 1 1 0 1 0

disp

4 13

Jump on overflow

0 1 1 1 0 0 0 0

disp

4 13

Jump on sign

0 1 1 1 1 0 0 0

disp

4 13

JNE JNZ

Jump on not equal not zero

0 1 1 1 0 1 0 1

disp

4 13

JNL JGE

Jump on not less greater or equal

0 1 1 1 1 1 0 1

disp

4 13

JNLE JG

Jump on not less or equal greater

0 1 1 1 1 1 1 1

disp

4 13

JNB JAE

Jump on not below above or equal

0 1 1 1 0 0 1 1

disp

4 13

JNBE JA

Jump on not below or equal above

0 1 1 1 0 1 1 1

disp

4 13

JNP JPO

Jump on not par par odd

0 1 1 1 1 0 1 1

disp

4 13

JNO

Jump on not overflow

0 1 1 1 0 0 0 1

disp

4 13

JNS

Jump on not sign

0 1 1 1 1 0 0 1

disp

4 13

JCXZ

Jump on CX zero

1 1 1 0 0 0 1 1

disp

5 15

LOOP

Loop CX times

1 1 1 0 0 0 1 0

disp

6 16

LOOP not

LOOPZ LOOPE

Loop while zero equal

1 1 1 0 0 0 0 1

disp

6 16

taken LOOP

LOOPNZ LOOPNE

Loop while not zero equal

1 1 1 0 0 0 0 0

disp

6 16

taken

ENTER

Enter Procedure

1 1 0 0 1 0 0 0

data-low

data-high

16(n

20(n

LEAVE

Leave Procedure

1 1 0 0 1 0 0 1

INT

Interrupt

Type specified

1 1 0 0 1 1 0 1

type

Type 3

1 1 0 0 1 1 0 0

if INT taken

INTO

Interrupt on overflow

1 1 0 0 1 1 1 0

48 4

if INT not

taken

IRET

Interrupt return

1 1 0 0 1 1 1 1

BOUND

Detect value out of range

0 1 1 0 0 0 1 0

mod reg r m

3335

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

80186 80188

INSTRUCTION SET SUMMARY

(Continued)

80186

80188

Function

Format

Clock

Comments

Cycles

PROCESSOR CONTROL

CLC

Clear carry

1 1 1 1 1 0 0 0

CMC

Complement carry

1 1 1 1 0 1 0 1

STC

Set carry

1 1 1 1 1 0 0 1

CLD

Clear direction

1 1 1 1 1 1 0 0

STD

Set direction

1 1 1 1 1 1 0 1

CLI

Clear interrupt

1 1 1 1 1 0 1 0

STI

Set interrupt

1 1 1 1 1 0 1 1

HLT

Halt

1 1 1 1 0 1 0 0

WAIT

Wait

1 0 0 1 1 0 1 1

if TEST

LOCK

Bus lock prefix

1 1 1 1 0 0 0 0

ESC

Processor Extension Escape

1 1 0 1 1 T T T

mod LLL r m

(TTT LLL are opcode to processor extension)

NOP

No Operation

1 0 0 1 0 0 0 0

Shaded areas indicate instructions not available in 8086 8088 microsystems

NOTE

Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer

FOOTNOTES

The Effective Address (EA) of the memory operand
is computed according to the mod and r m fields

if mod e 11 then r m is treated as REG field
if mod e 00 then DISP e 0

disp-low and disp-high are absent

if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high
is absent
if mod e 10 then DISP e disp-high disp-low
if r m e 000 then EA e (BX) a (SI) a DISP
if r m e 001 then EA e (BX) a (DI) a DISP
if r m e 010 then EA e (BP) a (SI) a DISP
if r m e 011 then EA e (BP) a (DI) a DISP
if r m e 100 then EA e (SI) a DISP
if r m e 101 then EA e (DI) a DISP
if r m e 110 then EA e (BP) a DISP
if r m e 111 then EA e (BX) a DISP

DISP follows 2nd byte of instruction (before data if
required)

except if mod e 00 and r m e 110 then EA e

disp-high disp-low

EA calculation time is 4 clock cycles for all modes
and is included in the execution times given whenev-
er appropriate

Segment Override Prefix

reg

reg is assigned according to the following

reg

Segment

REG is assigned according to the following table

16-Bit (w e 1)

8-Bit (w e 0)

000 AX

000 AL

001 CX

001 CL

010 DX

010 DL

011 BX

011 BL

100 SP

100 AH

101 BP

101 CH

110 SI

110 DH

111 DI

111 BH

The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment which may not be overridden

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: N80188

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: N80188