November 1994

Order Number 210393-008

UPI-41AH 42AH

UNIVERSAL PERIPHERAL INTERFACE

8-BIT SLAVE MICROCONTROLLER

UPI-41 6 MHz UPI-42 12 5 MHz

Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products

8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package

2048 x 8 ROM OTP 256 x 8 RAM on
UPI-42 1024 x 8 ROM OTP 128 x 8
RAM on UPI-41 8-Bit Timer Counter 18
Programmable I O Pins

One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface

DMA Interrupt or Polled Operation
Supported

Fully Compatible with all Intel and Most
Other Microprocessor Families

Interchangeable ROM and OTP EPROM
Versions

Expandable I O

Sync Mode Available

Over 90 Instructions 70% Single Byte

Available in EXPRESS

Standard Temperature Range

inteligent Programming Algorithm

Fast OTP Programming

Available in 40-Lead Plastic and 44-
Lead Plastic Leaded Chip Carrier
Packages

(See Packaging Spec Order

240800-001)

Package Type P and N

The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer
to develop customized solutions for peripheral device control

They are essentially ``slave'' microcontrollers or microcontrollers with a slave interface included on the chip
Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS
Modules and iAPX family as well as other 8- 16- and 32-bit systems

To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP) All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to
production level designs

210393 2

Figure 1 DIP Pin Configuration

210393 3

Figure 2 PLCC Pin Configuration

UPI-41AH 42AH

210393 1

Figure 3 Block Diagram

UPI PRODUCT MATRIX

UPI

ROM

OTP

RAM

Programming

Device

EPROM

Voltage

8042AH

256

8242AH

256

8742AH

256

12 5V

8041AH

128

8741AH

128

12 5V

THE INTEL 8242

As shown in the UPI-42 product matrix the UPI-42
will be offered as a pre-programmed 8042 with sev-
eral software vendors' keyboard controller firmware
The current list of available 8242 versions include
keyboard controller firmware from both Phoenix
Technologies Ltd

IBM and Award Software Inc

The 8242 is programmed with Phoenix Technologies
Ltd keyboard controller firmware for AT-compatible
systems This keyboard controller is fully compatible
with all AT-compatible operating systems and appli-
cations The 8242PC also contains Phoenix Tech-
nologies Ltd

firmware

This keyboard controller

provides support for AT PS 2 and most EISA plat-
forms as well as PS 2-style mouse support for either
AT or PS 2 platforms

The Intel 8242BB is programmed with IBM's key-
board controller firmware The 8242BB provides an
off the shelf keyboard and auxiliary device controller
for AT PS 2 EISA and PCI architectures

The 8242WA contains Award Software Inc firm-
ware This device provides at AT-compatible key-
board controller for use in IBM PC AT compatible
computers

The 8242WB contains a version of

Award Software Inc firmware that provides PS 2
style mouse support in addition to the standard fea-
tures of the 8242WA

Contact factory for current code revision available in all versions of the 8242 product lines

UPI-41AH 42AH

Table 1 Pin Description

DIP

PLCC

Symbol

Type

Name and Function

TEST 0

TEST INPUTS

Input pins which can be directly tested using conditional branch

instructions

TEST 1

FREQUENCY REFERENCE

TEST 1 (T

) also functions as the event timer input (under

software control) TEST 0 (T

) is used during PROM programming and ROM EPROM

verification It is also used during Sync Mode to reset the instruction state to S1 and
synchronize the internal clock to PH1 See the Sync Mode Section

XTAL 1

INPUTS

Inputs for a crystal LC or an external timing signal to determine the internal

oscillator frequency

XTAL 2

RESET

Input used to reset status flip-flops and to set the program counter to zero

RESET is also used during EPROM programming and verification

SINGLE STEP

Single step input used in conjunction with the SYNC output to step the

program through each instruction (EPROM) This should be tied to

5V when not used

This pin is also used to put the device in Sync Mode by applying 12 5V to it

CHIP SELECT

Chip select input used to select one UPI microcomputer out of several

connected to a common data bus

EXTERNAL ACCESS

External access input which allows emulation testing and

ROM EPROM verification This pin should be tied low if unused

READ

I O read input which enables the master CPU to read data and status words from

the OUTPUT DATA BUS BUFFER or status register

COMMAND DATA SELECT

Address Input used by the master processor to indicate

whether byte transfer is data (A

0 F1 is reset) or command (A

1 F1 is set) A

during program and verify operations

WRITE

I O write input which enables the master CPU to write data and command words

to the UPI INPUT DATA BUS BUFFER

SYNC

OUTPUT CLOCK

Output signal which occurs once per UPI instruction cycle SYNC can

be used as a strobe for external circuitry it is also used to synchronize single step
operation

(BUS)

12 19 14 21

I O

DATA BUS

Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI

microcomputer to an 8-bit master system data bus

27 34 30 33

I O

PORT 1

8-bit PORT 1 quasi-bidirectional I O lines P

access the signature row

and security bit

35 38

21 24 24 27

I O

PORT 2

8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P

) interface

directly to the 8243 I O expander device and contain address and data information during

35 38 39 42

PORT 4 7 access The upper 4 bits (P

) can be programmed to provide interrupt

Request and DMA Handshake capability Software control can configure P

as Output

Buffer Full (OBF) interrupt P

as Input Buffer Full (IBF) interrupt P

as DMA Request

(DRQ) and P

as DMA ACKnowledge (DACK)

PROG

I O

PROGRAM

Multifunction pin used as the program pulse input during PROM programming

During I O expander access the PROG pin acts as an address data strobe to the 8243
This pin should be tied high if unused

POWER

5V main power supply pin

POWER

5V during normal operation

12 5V during programming operation Low

power standby supply pin

GROUND

Circuit ground potential

UPI-41AH 42AH

UPI-41AH and UPI-42AH FEATURES

Two Data Bus Buffers one for input and one for
output This allows a much cleaner Master Slave
protocol

210393 4

8 Bits of Status

IBF OBF

are user definable status bits These

bits are defined by the ``MOV STS A'' single byte
single cycle instruction Bits 4 7 of the acccumu-
lator are moved to bits 4 7 of the status register
Bits 0 3 of the status register are not affected

MOV STS A

Op Code 90H

RD and WR are edge triggered IBF OBF F

and

INT change internally after the trailing edge of RD
or WR

210393 6

During the time that the host CPU is reading the
status register the UPI is prevented from updat-
ing this register or is `locked out '

and P

are port pins or Buffer Flag pins

which can be used to interrupt a master proces-
sor These pins default to port pins on Reset

If the ``EN FLAGS'' instruction has been execut-
ed P

becomes the OBF (Output Buffer Full) pin

A ``1'' written to P

enables the OBF pin (the pin

outputs the OBF Status Bit) A ``0'' written to P

disables the OBF pin (the pin remains low) This
pin can be used to indicate that valid data is avail-
able from the UPI (in Output Data Bus Buffer)

If ``EN FLAGS'' has been executed P

becomes

the IBF (Input Buffer Full) pin A ``1'' written to P

enables the IBF pin (the pin outputs the inverse of
the IBF Status Bit A ``0'' written to P

disables

the IBF pin (the pin remains low) This pin can be
used to indicate that the UPI is ready for data

210393 5

Data Bus Buffer Interrupt Capability

EN FLAGS

Op Code 0F5H

UPI-41AH 42AH

and P

are port pins or DMA handshake pins

for use with a DMA controller These pins default
to port pins on Reset

If the ``EN DMA'' instruction has been executed
P

becomes the DRQ (DMA Request) pin A ``1''

written to P

causes a DMA request (DRQ is acti-

vated)

DRQ

deactivated

DACK

WR or execution of the ``EN DMA'' in-

struction

If ``EN DMA'' has been executed P

becomes

the DACK (DMA ACKnowledge) pin This pin acts
as a chip select input for the Data Bus Buffer reg-
isters during DMA transfers

210393 7

DMA Handshake Capability

EN DMA

Op Code 0E5H

When EA is enabled on the UPI the program
counter is placed on Port 1 and the lower three
bits of Port 2 (MSB e P

LSB e P

) On the

UPI this information is multiplexed with PORT
DATA (see port timing diagrams at end of this
data sheet)

The 8741AH and 8742AH support the inteligent

Programming Algorithm (See the Programming
Section )

210393 8

Figure 5 8088-UPI-41AH 42AH Interface

210393 10

Figure 6 8048H-UPI-41 42 Interface

210393 9

Figure 7 UPI-41 42-8243 Keyboard Scanner

APPLICATIONS

210393 30

Figure 4 UPI-41AH 42AH Keyboard Controller

UPI-41AH 42AH

210393 11

Figure 8 UPI-41AH 42AH 80-Column

Matrix Printer Interface

PROGRAMMING AND VERIFYING THE
8741AH AND 8742AH OTP EPROM

Programming Verification

In brief the programming process consists of acti-
vating the program mode applying an address
latching the address applying data and applying a
programming pulse Each word is programmed com-
pletely before moving on to the next and is followed
by a verification step The following is a list of the
pins used for programming and a description of their
functions

Function

XTAL 1

2 Clock Inputs

Reset

Initialization and Address Latching

Test 0

Selection of Program or Verify Mode

Activation of Program Verify Signature
Row Security Bit Modes

BUS

Address and Data Input
Data Output During Verify

2022

Address Input

Programming Power Supply

PROG

Program Pulse Input

WARNING
An attempt to program a missocketed 8741AH or 8742AH will result in
severe damage to the part An indication of a properly socketed part is
the appearance of the SYNC clock output The lack of this clock may
be used to disable the programmer

The Program Verify sequence is

1 CS e 5V V

5V V

5V RESET e 0V

0V TEST 0 e 5V clock applied or internal

oscillator operating BUS floating PROG e 5V

2 Insert 8741AH or 8742AH in programming socket

3 TEST 0 e 0V (select program mode)

4 EA e 12 5V (active program mode)

5 V

6V (programming supply)

6 V

12 5V (programming power)

7 Address applied to BUS and P

2022

8 RESET e 5V (latch address)

9 Data applied to BUS

10 PROG e 5V followed by one 1 ms pulse to 0V

11 TEST 0 e 5V (verify mode)

12 Read and verify data on BUS

13 TEST 0 e 0V

14 Apply overprogram pulse

15 RESET e 0V and repeat from step 6

16 Programmer should be at conditions of step 1

when 8741AH or 8742AH is removed from socket

Please follow the inteligent Programming flow chart

for proper programming procedure

inteligent Programming Algorithm

The inteligent Programming Algorithm rapidly pro-

grams Intel 8741AH 8742AH EPROMs using an effi-
cient and reliable method particularly suited to the
production programming environment Typical pro-
gramming time for individual devices is on the order
of 10 seconds Programming reliability is also en-
sured as the incremental program margin of each
byte is continually monitored to determine when it
has been successfully programmed A flowchart of
the 8741AH 8742AH inteligent Programming Algo-

rithm is shown in Figure 9

The inteligent Programming Algorithm utilizes two

different pulse types initial and overprogram The
duration of the initial PROG pulse(s) is one millisec-
ond which will then be followed by a longer overpro-
gram pulse of length 3X msec X is an iteration coun-
ter and is equal to the number of the initial one milli-
second pulses applied to a particular 8741AH
8742AH location before a correct verify occurs Up
to 25 one-millisecond pulses per byte are provided
for before the overprogram pulse is applied

UPI-41AH 42AH

The entire sequence of program pulses and byte
verifications is performed at V

6 0V and V

12 5V When the inteligent Programming cycle has

been completed all bytes should be compared to
the original data with V

5 0 V

Verify

A verify should be performed on the programmed
bits to determine that they have been correctly pro-
grammed The verify is performed with T0 e 5V
V

5V EA e 12 5V SS e 5V PROG e 5V

A0 e 0V and CS e 5V

SECURITY BIT

The security bit is a single EPROM cell outside the
EPROM array The user can program this bit with the
appropriate access code and the normal program-
ming procedure to inhibit any external access to the
EPROM contents Thus the user's resident program
is protected There is no direct external access to
this bit However the security byte in the signature
row has the same address and can be used to
check indirectly whether the security bit has been
programmed or not The security bit has no effect on
the signature mode so the security byte can always
be examined

SECURITY BIT PROGRAMMING
VERIFICATION

Programming

a Read the security byte of the signature mode

Make sure it is 00H

b Apply access code to appropriate inputs to put

the device into security mode

c Apply high voltage to EA and V

pins

d Follow the programming procedure as per the

inteligent Programming Algorithm with known

data on the databus Not only the security bit but
also the security byte of the signature row is pro-
grammed

e Verify that the security byte of the signature

mode contains the same data as appeared on
the data bus (If DB0 DB7 e high the security
byte will contain FFH )

Read two consecutive known bytes from the
EPROM array and verify that the wrong data are
retrieved in at least one verification

If the

EPROM can still be read the security bit may
have not been fully programmed though the se-
curity byte in the signature mode has

Verification

Since the security bit address overlaps the address
of the security byte of the signature mode it can be
used to check indirectly whether the security bit has
been programmed or not Therefore the security bit
verification is a mere read operation of the security
byte of the signature row (0FFH e security bit pro-
grammed 00H e security bit unprogrammed) Note
that during the security bit programming the reading
of the security byte does not necessarily indicate
that the security bit has been successfully pro-
grammed Thus it is recommended that two consec-
utive known bytes in the EPROM array be read and
the wrong data should be read at least once be-
cause it is highly improbable that random data coin-
cides with the correct ones twice

UPI-41AH 42AH

SIGNATURE MODE

The UPI-41AH 42AH has an additional 32 bytes of
EPROM available for Intel and user signatures and
miscellaneous purposes The 32 bytes are parti-
tioned as follows

A Test code checksum

This can accommodate

up to 25 bytes of code for testing the internal
nodes that are not testable by executing from the
external memory The test code checksum is
present on ROMs and OTPs

B Intel signature

This allows the programmer to

read from the UPI-41AH 42AH the manufacturer
of the device and the exact product name It fa-
cilitates automatic device identification and will
be present in the ROM and OTP versions Loca-
tion 10H contains the manufacturer code For In-
tel it is 89H Location 11H contains the device
code

The code is 43H and 42H for the 8042AH and
OTP 8742AH and 41H and 40H for the 8041AH
and OTP 8741AH respectively The code is 44H
for any device with the security bit set by Intel

C User signature

The user signature memory is

implemented in the EPROM and consists of 2
bytes for the customer to program his own signa-
ture code (for identification purposes and quick
sorting of previously programmed materials)

D Test signature

This memory is used to store

testing information such as test data bin num-
ber etc (for use in quality and manufacturing
control)

E Security byte

This byte is used to check

whether the security bit has been programmed
(see the security bit section)

The signature mode can be accessed by setting P10 e 0 P11 P17 e 1 and then following the programming
and or verification procedures The location of the various address partitions are as follows

Address

Device

No of

Type

Bytes

Test Code Checksum

0FH

ROM OTP

16H

1EH

Intel Signature

10H

11H

ROM OTP

User Signature

12H

13H

OTP

Test Signature

14H

15H

ROM OTP

Security Byte

1FH

OTP

UPI-41AH 42AH

SYNC MODE

The Sync Mode is provided to ease the design of
multiple controller circuits by allowing the designer
to force the device into known phase and state time
The Sync Mode may also be utilized by automatic
test equipment (ATE) for quick easy and efficient
synchronizing between the tester and the DUT (de-
vice under test)

Sync Mode is enabled when SS pin is raised to high
voltage level of a12 volts To begin synchroniza-
tion T0 is raised to 5 volts at least four clock cycles
after SS T0 must be high for at least four X1 clock
cycles to fully reset the prescaler and time state
generators T0 may then be brought down during
low state of X1 Two clock cycles later with the ris-
ing edge of X1 the device enters into Time State 1
Phase 1 SS is then brought down to 5 volts 4 clocks
later after T0 RESET is allowed to go high 5 tCY (75
clocks) later for normal execution of code

SYNC MODE TIMING DIAGRAMS

210393 28

Minimum Specifications
SYNC Operation Time t

SYNC

3 5 XTAL 1 Clock cycles Reset Time t

4 t

NOTE
The rising and falling edges of T0 should occur during low state of XTAL1 clock

UPI-41AH 42AH

ACCESS CODE

The following table summarizes the access codes required to invoke the Sync Mode Signature Mode
and the Security Bit respectively Also the programming and verification modes are included for
comparison

Control Signals

Data Bus

Access Code

Modes

Port 2

Port 1

RST SS EA PROG V

0 1 2 0

1 2 3 4 5 6 7

Programming

1 HV

DDH

Address

Addr

X X X X X X

Mode

1 HV

STB

DDH

Data In

Addr

Verification

1 HV

Address

Addr

X X X X X X

Mode

1 HV

Data Out

Addr

Sync Mode

STB

HV 0

X X X X X X X X X X X

High

Signature Prog

1 HV

DDH

Addr (see Sig Mode Table)

0 0 0 0

1 1 1 1 X X 1

Mode

1 HV

STB

DDH

Data In

0 0 0

Verify

1 HV

Addr (see Sig Mode Table)

0 0 0

1 HV

Data Out

0 0 0

Security

Prog

1 HV

DDH

Address

0 0 0

Bit Byte

1 HV

STB

DDH

Data In

0 0 0

Verify

1 HV

Address

0 0 0

1 HV

Data Out

0 0 0

NOTES
1 a

0 or 1 a

must

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias

0 C to a70 C

Storage Temperature

65 C to a150 C

Voltage on Any Pin with

Respect to Ground

0 5V to a7V

Power Dissipation

1 5 W

NOTICE This is a production data sheet The specifi-
cations are subject to change without notice

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

D C CHARACTERISTICS

0 C to a70 C V

e a

10%

Symbol

Parameter

UPI-41AH 42AH

Units

Notes

Min

Max

Input Low Voltage (Except XTAL1 XTAL2 RESET)

0 5

0 8

IL1

Input Low Voltage (XTAL1 XTAL2 RESET)

0 5

0 6

Input High Voltage (Except XTAL1 XTAL2 RESET)

2 0

IH1

Input High Voltage (XTAL1 RESET)

3 5

IH2

Input High Voltage (XTAL2)

2 2

Output Low Voltage (D

)

0 45

2 0 mA

UPI-41AH 42AH

D C CHARACTERISTICS

0 C to a70 C V

e a

10% (Continued)

Symbol

Parameter

UPI-41AH 42AH

Units

Notes

Min

Max

OL1

Output Low Voltage (P

Sync)

0 45

1 6 mA

OL2

Output Low Voltage (PROG)

0 45

1 0 mA

Output High Voltage (D

)

2 4

e b

400 mA

OH1

Output High Voltage (All Other Outputs)

2 4

e b

50 mA

Input Leakage Current (T

RD WR CS A

EA)

OFL

Output Leakage Current (D

High Z State)

0 45

OUT

Low Input Load Current (P

)

0 3

mA V

0 8V

LI1

Low Input Load Current (RESET SS)

0 2

mA V

0 8V

Supply Current

mA Typical e 8 mA

Total Supply Current

135

mA Typical e 80 mA

Standby Power Down Supply Current

mA Typical e 8 mA

Input Leakage Current (P

)

100

Input Capacitance

25 C

(1)

I O Capacitance

25 C

(1)

NOTE
1 Sampled not 100% tested

D C CHARACTERISTICS

PROGRAMMING

25 C

5 C V

0 25V V

12 5V

0 5V

Symbol

Parameter

Min

Max

Units

DDH

Program Voltage High Level

(1)

DDL

Voltage Low Level

4 75

5 25

PROG Program Voltage High Level

2 0

5 5

PROG Voltage Low Level

0 5

0 8

EAH

Input High Voltage for EA

12 0

13 0

(2)

EAL

EA Voltage Low Level

0 5

5 25

High Voltage Supply Current

50 0

EA High Voltage Supply Current

1 0

NOTES
1 Voltages over 13V applied to pin V

will permanently damage the device

2 V

EAH

must be applied to EA before V

DDH

and removed after V

DDL

3 V

must be applied simultaneously or before V

and must be removed simultaneously or after V

UPI-41AH 42AH

A C CHARACTERISTICS

0 C to a70 C V

0V V

e a

10%

DBB READ

Symbol

Parameter

Min

Max

Units

CS A

Setup to RD

CS A

Hold After RD

RD Pulse Width

160

CS A

to Data Out Delay

130

to Data Out Delay

130

to Data Float Delay

DBB WRITE

Symbol

Parameter

Min

Max

Units

CS A

Setup to WR

CS A

Hold After WR

WR Pulse Width

160

Data Setup to WR

130

Data Hold After WR

CLOCK

Symbol

Parameter

Min

Max

Units

(UPI-41AH 42AH)

Cycle Time

1 2

9 20

(1)

CYC

(UPI-41AH 42AH)

Clock Period

613

PWH

Clock High Time

PWL

Clock Low Time

Clock Rise Time

Clock Fall Time

NOTE
1 t

15 f(XTAL)

A C CHARACTERISTICS

DMA

Symbol

Parameter

Min

Max

Units

ACC

DACK to WR or RD

CAC

RD or WR to DACK

ACD

DACK to Data Valid

130

CRQ

RD or WR to DRQ Cleared

110

(1)

NOTE
1 C

150 pF

UPI-41AH 42AH

A C CHARACTERISTICS

PROGRAMMING

25 C

5 C V

0 25V V

DDL

e a

0 25V V

DDH

12 5V

0 5V

(8741AH 8742AH ONLY)

Symbol

Parameter

Min

Max

Units

Address Setup Time to RESET

Address Hold Time After RESET

Data in Setup Time to PROG

Data in Hold Time After PROG

Initial Program Pulse Width

0 95

1 05

(1)

Test 0 Setup Time for Program Mode

Test 0 Hold Time After Program Mode

Test 0 to Data Out Delay

RESET Pulse Width to Latch Address

PROG Rise and Fall Times

0 5

100

CPU Operation Cycle Time

2 5

3 75

RESET Setup Time Before EA

OPW

Overprogram Pulse Width

2 85

78 75

(2)

EA High to V

High

NOTES
1 Typical Initial Program Pulse width tolerance

1 ms

2 This variation is a function of the iteration counter value X
3 If TEST 0 is high t

can be triggered by RESET

A C CHARACTERISTICS

PORT 2

0 C to a70 C V

e a

10%

Symbol

Parameter

f(t

)

(3)

Min

Max

Units

Port Control Setup Before Falling Edge of PROG

1 15 t

(1)

Port Control Hold After Falling Edge of PROG

1 10 t

125

(2)

PROG to Time P2 Input Must Be Valid

8 15 t

650

(1)

Input Data Hold Time

150

(2)

Output Data Setup Time

2 10 t

250

(1)

Output Data Hold Time

1 10 t

(2)

PROG Pulse Width

6 10 t

750

NOTES
1 C

80 pF

2 C

20 pF

3 t

1 25 ms

UPI-41AH 42AH

A C TESTING INPUT OUTPUT WAVEFORM

INPUT OUTPUT

210393 14

A C TESTING LOAD CIRCUIT

210393 15

DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS

6 MHz

210393 16

210393 17

Rise and Fall Times Should Not Exceed 10 ns Resis-
tors to V

are Needed to Ensure V

3 5V if TTL

Circuitry is Used

LC OSCILLATOR MODE

NOMINAL

f e

0LC

45 H 20 pF

5 2 MHz

120 H 20 pF

3 2 MHz

C e

C a 3Cpp

Cpp j 5 10 pF
Pin-to-Pin Capacitance

210393 18

Each C Should be Approximately 20 pF including Stray Capacitance

CRYSTAL OSCILLATOR MODE

210393 19

5 pF (STRAY 5 pF)

(CRYSTAL a STRAY) 8 pF

20 30 pF INCLUDING STRAY

Crystal Series Resistance Should
be Less Than 30X at 12 5 MHz

UPI-41AH 42AH

Table 2 UPI Instruction Set

Mnemonic

Description

Bytes

Cycles

ACCUMULATOR
ADD A Rr

Add register to A

ADD A

Add data memory

to A

ADD A

data

Add immediate to A

ADDC A Rr

Add register to A

with carry

ADDC A

Add data memory

to A with carry

ADDC A

data

Add immediate

to A with carry

ANL A Rr

AND register to A

ANL A

AND data memory

to A

ANL A

data

AND immediate to A

ORL A Rr

OR register to A

ORL A

OR data memory

to A

ORL A

data

OR immediate to A

XRL A Rr

Exclusive OR regis-

ter to A

XRL A

Exclusive OR data

memory to A

XRL A

data

Exclusive OR imme-

diate to A

INC A

Increment A

DEC A

Decrement A

CLR A

Clear A

CPL A

Complement A

DA A

Decimal Adjust A

SWAP A

Swap nibbles of A

RL A

Rotate A left

RLC A

Rotate A left through

carry

RR A

Rotate A right

RRC A

Rotate A right

through carry

INPUT OUTPUT
IN A Pp

Input port to A

OUTL Pp A

Output A to port

ANL Pp

data

AND immediate to

port

ORL Pp

data

OR immediate to

port

IN A DBB

Input DBB to A

clear IBF

OUT DBB A

Output A to DBB

set OBF

MOV STS A

to Bits 4 7 of

Status

MOVD A Pp

Input Expander

port to A

MOVD Pp A

Output A to

Expander port

ANLD Pp A

AND A to Expander

port

ORLD Pp A

OR A to Expander

port

Mnemonic

Description

Bytes

Cycles

DATA MOVES
MOV A Rr

Move register to A

MOV A

Move data memory

to A

MOV A

data

Move immediate to A

MOV Rr A

Move A to register

MOV

Rr A

Move A to data

memory

MOV Rr

data

Move immediate to

MOV

Move immediate to

data

data memory

MOV A PSW

Move PSW to A

MOV PSW A

Move A to PSW

XCH A Rr

Exchange A and

XCH A

Exchange A and

data memory

XCHD A

Exchange digit of A

and register

MOVP A

Move to A from

current page

MOVP3 A

Move to A from

page 3

TIMER COUNTER
MOV A T

Read Timer Counter

MOV T A

Load Timer Counter

STRT T

Start Timer

STRT CNT

Start Counter

STOP TCNT

Stop Timer Counter

EN TCNTI

Enable Timer

Counter Interrupt

DIS TCNTI

Disable Timer

Counter Interrupt

CONTROL
EN DMA

Enable DMA Hand-

shake Lines

EN I

Enable IBF Interrupt

DIS I

Diable IBF Inter-

rupt

EN FLAGS

Enable Master

Interrupts

SEL RB0

Select register

bank 0

SEL RB1

Select register

bank 1

NOP

No Operation

REGISTERS
INC Rr

Increment register

INC

Increment data

memory

DEC Rr

Decrement register

UPI-41AH 42AH

Table 2 UPI Instruction Set

(Continued)

Mnemonic

Description

Bytes

Cycles

SUBROUTINE
CALL addr

Jump to subroutine

RET

Return

RETR

Return and restore

status

FLAGS
CLR C

Clear Carry

CPL C

Complement Carry

CLR F0

Clear Flag 0

CPL F0

Complement Flag 0

CLR F1

Clear F1 Flag

CPL F1

Complement F1 Flag

BRANCH
JMP addr

Jump unconditional

JMPP

Jump indirect

DJNZ Rr addr

Decrement register

and jump

JC addr

Jump on Carry

JNC addr

Jump on Carry

JZ addr

Jump on A Zero

JNZ addr

Jump on A not Zero

JT0 addr

Jump on T0

JNT0 addr

Jump on T0

JT1 addr

Jump on T1

JNT1 addr

Jump on T1

JF0 addr

Jump on F0 Flag

JF1 addr

Jump on F1 Flag

JTF addr

Jump on Timer Flag

1 Clear Flag

JNIBF addr

Jump on IBF Flag

JOBF addr

Jump on OBF Flag

JBb addr

Jump on Accumula-

for Bit

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