Document Outline
- 1.0 INTRODUCTION
- 2.0 ARCHITECTURE OVERVIEW
- 3.0 CONNECTOR INTERFACE
- 4.0 FUNCTIONAL DESCRIPTION
- 5.0 MECHANICAL SPECIFICATION
- 6.0 THERMAL SPECIFICATION
- 7.0 LABELING INFORMATION
- 8.0 ENVIRONMENTAL STANDARDS
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes
previously published specifications on these devices from Intel
.
INTEL CORPORATION 1999, 2000
February 2000
Order Number: 245109-003
Pentium
II Processor
With On-die Cache Mobile Module
Connector 1 (MMC-1)
Datasheet
Product Features
n
Core frequencies of 400 MHz, 366 MHz, 333 MHz,
300 MHz, and 266 MHz
n
256K of on-die 2
nd
level cache
n
66-MHz processor system bus speed
n
Integrated Active Thermal Feedback (ATF) system
ACPI Rev. 1.0 compliant
Internal A/Ddigital signaling (SMBus) across
the module interface
Programmable trip point interrupt or poll mode
for temperature reading
n
Processor core voltage regulation supports input
voltages from 5V to 21V
Above 80 percent peak efficiency
n
Thermal transfer plate on the CPU and the Intel
82433DX provides heat dissipation
n
Intel
82443DX Host Bridge system controller
DRAM controller supports EDO and SDRAM at
3.3V
Supports PCI CLKRUN# protocol
SDRAM clock support and self refresh of EDO
or SDRAM during Suspend mode
3.3V only PCI bus control, Rev 2.1 compliant
2
Intel
Pentium
II Processor With On-die Cache Mobile Module MMC-1
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life-saving, or life-sustaining applications. Intel may make changes to specifications and product descriptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium II processor with on-die cache mobile modules may contain design defects or errors known as errata. Current characterized errata are
available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725 or by visiting Intel's web site at
http://www.intel.com
Copyright Intel Corporation1999, 2000.
*Third-party brands and names are the property of their respective owners.
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Intel
Pentium
II Processor With On-die Cache Mobile Module MMC-1
CONTENTS
1.0
INTRODUCTION ..................................................5
1.1
Revision History ....................................................5
2.0
ARCHITECTURE OVERVIEW.............................5
3.0
MODULE CONNECTOR INTERFACE ................7
3.1
Signal Definition ....................................................7
3.1.1
Signal List ................................................8
3.1.2
Memory (108 Signals).............................9
3.1.3.
PCI (56 Signals) ....................................10
3.1.4
Processor and PIIX4E/M Sideband
(9 Signals) ............................................11
3.1.5
Power Management (8 Signals) ...........12
3.1.6
Clock (8 Signals) ...................................13
3.1.7
Voltages (39 Signals)............................14
3.1.8
JTAG (7 Signals)...................................14
3.1.9
Miscellaneous (45 Signals)...................15
3.2
Connector Pin Assignments ...............................16
3.3
Pin and Pad Assignments...................................18
4.0
FUNCTIONAL DESCRIPTION ...........................19
4.1
Pentium II Processor With On-Die Cache Mobile
Module MMC-1......................................................19
4.2
L2 Cache .............................................................19
4.3
The 82443DX Host Bridge System Controller ...19
4.3.1
Memory Organization............................19
4.3.2
Reset Strap Options..............................20
4.3.3
PCI Interface..........................................20
4.3.4
AGP Feature Set...................................20
4.4
Power Management............................................20
4.4.1
Clock Control Architecture ....................20
4.4.2
Normal State..........................................22
4.4.3
Auto Halt State ......................................22
4.4.4
Stop Grant State....................................22
4.4.5
Quick Start State ...................................22
4.4.6
HALT/Grant Snoop State ......................22
4.4.7
Sleep State ............................................22
4.4.8
Deep Sleep State ..................................23
4.5
Typical POS/STR Power...................... 23
4.6
Electrical Requirements ..................................... 24
4.6.1
DC Requirements ................................. 24
4.6.2
AC Requirements ................................. 25
4.6.2.1
BCLK Signal Quality Specifications and
Measurement Guidelines ..................... 26
4.7
The Voltage Regulator ....................................... 26
4.7.1
Voltage Regulator Efficiency ................ 26
4.7.2.
Control of the Voltage Regulator.......... 27
4.7.2.1
Voltage Signal Definition and
Sequencing ........................................... 28
4.7.3
Power Planes: Bulk Capacitance Requirements 29
4.7.4
Surge Current Guidelines..................... 30
4.7.4.1
Slew-rate Control: Circuit Description.. 32
4.7.4.2
Undervoltage Lockout: Circuit
Description (V_uv_lockout) .................. 33
4.7.4.3
Overvoltage Lockout: Circuit Description
(V_ov_lockout)...................................... 34
4.7.4.4
Overcurrent Protection: Circuit
Description ............................................ 34
4.8
Active Thermal Feedback .................................. 34
4.9
Thermal Sensor Configuration Register ............ 35
5.0
MECHANICAL SPECIFICATION....................... 35
5.1
Module Dimensions............................................ 35
5.1.1
MMC-1 Connector Pin 1 Location........ 36
5.1.2
Printed Circuit Board Thickness........... 36
5.1.3
Height Restrictions ............................... 37
5.2
Thermal Transfer Plate....................................... 38
5.3
Physical Support................................................. 39
5.3.1
Mounting Requirements ....................... 39
5.3.2
Module Weight...................................... 40
6.0
THERMAL SPECIFICATION ............................. 40
6.1
Thermal Design Power....................................... 40
6.2
Thermal Sensor Setpoint ................................... 40
7.0
LABELING INFORMATION ............................... 41
8.0
ENVIRONMENTAL STANDARDS..................... 42
4
Intel
Pentium
II Processor With On-die Cache Mobile Module MMC-1
FIGURES
Figure 1. Block Diagram of the Pentium II Processor With
On-die Cache Mobile Module MMC-1.....................6
Figure 2. 280-Pin Connector Footprint Pad Numbers,
Module Secondary Side ........................................18
Figure 3. Clock Control States ..............................................21
Figure 4. BCLK, TCK, and PICCLK Generic Clock Waveform
at the Processor Core Pin .....................................26
Figure 5. Power-on Sequence Timing ..................................29
Figure 6. Instantaneous In-rush Current Model....................30
Figure 7. Instantaneous In-rush Current...............................31
Figure 8. Over Current Protection Circuit .............................32
Figure 9. Spice Simulation Using In-rush Protection
(Example Only) ......................................................33
Figure 10. Board Dimensions................................................35
Figure 11. Board Dimensions- Pin 1 Orientation..................36
Figure 12. Printed Circuit Board Thickness ..........................37
Figure 13. Keep-out Zone .....................................................37
Figure 14. Thermal Transfer Plate (A) ..................................38
Figure 15. Thermal Transfer Plate (B) ..................................39
Figure 16. Standoff Holes, Board Edge Clearance, and EMI
Containment Ring................................................40
Figure 17. Product Tracking Code ........................................41
TABLES
Table 1. Module Connector Signal Summary ........................ 7
Table 2. Memory Signal Descriptions .................................... 9
Table 3. PCI Signal Description ........................................... 10
Table 4. Processor/PIIX4E/M Sideband Signal
Descriptions............................................................ 11
Table 5. Power Management Signal Descriptions............... 12
Table 6. Clock Signal Descriptions ...................................... 13
Table 7. Voltage Descriptions .............................................. 14
Table 8. JTAG Pins............................................................... 14
Table 9. Miscellaneous Pins................................................. 15
Table 10. Connector Pin Assignments................................. 16
Table 11. Connector Specifications ..................................... 19
Table 12. Configuration Straps for the 82443DX Host Bridge
System Controller................................................. 20
Table 13. Clock State Characteristics.................................. 23
Table 14. POS/STR Power................................................... 23
Table 15. Power Supply Design Specifications
.................. 24
Table 16. AC Specifications (BCLK) at the Processor
Core Pins.............................................................. 25
Table 17. BCLK Signal Quality Specifications at the
Processor Core..................................................... 26
Table 18. Typical Voltage Regulator Efficiency ................... 27
Table 19. Voltage Signal Definitions and Sequences ......... 28
Table 20. VR_ON In-rush Current........................................ 29
Table 21. Capacitance Requirements per Power Plane ..... 30
Table 22. Thermal Sensor SMBus Address Table .............. 34
Table 23. Thermal Sensor Configuration Register .............. 35
Table 24. Thermal Design Power Specifications................. 40
Table 25. Environmental Standards..................................... 42
5
Intel
Pentium
II Processor With On-die Cache Mobile Module MMC-1
1.0
INTRODUCTION
This document provides the technical information for
integrating the Pentium
II Processor Mobile Module
Connector 1 (MMC-1) into the latest notebook systems for
today's notebook market.
Building around this modular design gives the system
manufacturer these advantages:
Avoids complexities associated with designing high-
speed processor core logic boards.
Provides an upgrade path from previous Intel
Mobile
Modules using a standard interface.
1.1
Revision History
Date
Revision
Updates
2/ 1999
1.0
Initial release
5/ 1999
2.0
Updates include:
Addition of the 400-MHz
processor speed
POS/STR measurement
corrections
ESD specification clarification
VR_ON and VR_PWRGD
specification correction
L2 cache specification correction
Power sequence clarification
2/ 2000
3.0
Revised Table 22
2.0
ARCHITECTURE OVERVIEW
The Pentium II processor with on-die cache mobile module
MMC-1 is a highly integrated assembly containing the mobile
Pentium II processor with on-die cache and its immediate
system-level support. The Pentium II processor with on-die
cache mobile module MMC-1 offers speeds of 400
megahertz,366 megahertz, 333 megahertz, 300 megahertz,
and 266 megahertz. All processor speeds have a 66-
megahertz processor system bus (PSB) speed.
The PIIX4E/M PCI/ISA Bridge is one of two large-scale
integrated devices of the Intel 440DX PCIset. A notebook's
system electronics must include a PIIX4E/M device to
connect to the Pentium II processor with on-die cache
mobile module. The PIIX4E/M provides extensive power
management capabilities and supports the second integrated
device, the Intel
82443DX Host Bridge. Key features of the
Intel 82443DX Host Bridge system controller include the
DRAM controller, which supports EDO at 3.3 volts with a
burst read at 7-2-2-2 (60 nanoseconds) or SDRAM at 3.3
volts with a burst read at 8-1-1-1 (66 megahertz, CL=2).
The 82443DX Host Bridge also regulates the PCI clock on
the PCI bus. The 82443DX clock enables Self Refresh mode
of EDO or SDRAM during Suspend mode and is compatible
with SMRAM (C_SMRAM) and Extended SMRAM
(E_SMRAM) modes of power management. E_SMRAM
mode supports write-back cacheable SMRAM up to 1
megabyte.
A thermal transfer plate (TTP) on the 82443DX Host Bridge
and the CPU provides heat dissipation and a thermal attach
point for the notebook manufacturer's thermal solution.
An on-board voltage regulator converts the system DC
voltage to the processor's core and I/O voltage. Isolating the
processor voltage requirements allows the system
manufacturer to incorporate different processor variants into
a single notebook system.
Supporting input voltages from 5 volts to 21 volts, the
processor core voltage regulator enables an above 80
percent peak efficiency and decouples processor voltage
requirements from the system.
The Pentium II processor with on-die cache mobile module
MMC-1 also incorporates Active Thermal Feedback (ATF)
sensing, compliant to the ACPI Specification Rev 1.0. A
system management bus (SMBus) supports the internal and
external temperature sensing with programmable trip points.
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