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Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and
Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without
notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 242973-001
Compatible with Large Software Base
-
-
MS-DOS, Windows, OS/2, UNIX
32-Bit CPU with 64-Bit Data Bus
Superscalar Architecture
-
-
Two Pipelined Integer Units Are
Capable of 2 Instructions/Clock
-
-
Pipelined Floating Point Unit
Separate Code and Data Caches
-
-
8K Code, 8K Writeback Data
-
-
MESI Cache Protocol
Advanced Design Features
-
-
Branch Prediction
-
-
Virtual Mode Extensions
Low Voltage BiCMOS Silicon
Technology
4M Pages for Increased TLB Hit Rate
IEEE 1149.1 Boundary Scan
Internal Error Detection Features
SL Enhanced Power Management
Features
-
-
System Management Mode
-
-
Clock Control
Voltage Reduction Technology
-
-
2.9V V
CC
for core supply
-
-
3.3V V
CC
for I/O buffer supply
Fractional Bus Operation
-
-
75-MHz Core / 50-MHz Bus
-
-
90-MHz Core / 60-MHz Bus
-
-
100-MHz Core / 66-MHz Bus
The Pentium
processor is fully compatible with the entire installed base of applications for DOS, Windows,
OS/2, and UNIX, and all other software that runs on any earlier Intel 8086 family product. The Pentium
processor's superscalar architecture can execute two instructions per clock cycle. Branch prediction and
separate caches also increase performance. The pipelined floating-point unit delivers workstation level
performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The
Pentium processor with voltage reduction technology has 3.3 million transistors. It is built on Intel's advanced low
voltage BiCMOS silicon technology, and has full SL Enhanced power management features, including System
Management Mode (SMM) and clock control. The additional SL Enhanced features, 2.9V core operation along
with 3.3V I/O buffer operation, and the option of the TCP, which are not available in the desktop version of the
Pentium processor, make the Pentium processor with voltage reduction technology ideal for enabling mobile
Pentium processor designs. The Pentium processor may contain design defects or errors known as errata.
Current characterized errata are available upon request.
Other brands and trademarks are the property of their respective owners.
PENTIUM
PROCESSOR AT iCOMP
INDEX 815\100 MHz
PENTIUM PROCESSOR AT iCOMP INDEX 735\90 MHz
PENTIUM PROCESSOR AT iCOMP INDEX 610\75 MHz
WITH VOLTAGE REDUCTION TECHNOLOGY
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
2
CONTENTS
PAGE
PAGE
1.0. INTRODUCTION _______________________2
2.0. MICROPROCESSOR ARCHITECTURE
OVERVIEW____________________________3
2.1. Pentium Processor Family Architecture ___4
3.0. TCP PINOUT __________________________6
3.1. Pentium Processor with Voltage Reduction
Technology Differences from the SPGA 3.3V
Pentium
Processor ____________________6
3.2. TCP Pinout and Pin Descriptions _________8
3.2.1. TCP PENTIUM PROCESSOR
PINOUT _________________________8
3.2.2. TCP PIN CROSS REFERENCE TABLE
FOR PENTIUM PROCESSOR ______9
3.3. Design Notes________________________13
3.4. Quick Pin Reference __________________15
3.5. Pin Reference Tables _________________22
3.6. Pin Grouping According to Function ______25
4.0. TCP PENTIUM PROCESSOR ELECTRICAL
SPECIFICATIONS _____________________26
4.1. Maximum Ratings ____________________26
4.2. DC Specifications ____________________26
4.2.1. POWER SEQUENCING ___________26
4.3. AC Specifications ____________________29
4.3.1. POWER AND GROUND ___________29
4.3.2. DECOUPLING
RECOMMENDATIONS ____________29
4.3.3. CONNECTION SPECIFICATIONS ___29
4.3.4. AC TIMINGS FOR A 50-MHZ BUS ___30
4.3.5. AC TIMINGS FOR A 60-MHZ BUS ___34
4.3.6. AC TIMINGS FOR A 66-MHZ BUS ___38
4.4. I/O Buffer Models_____________________47
4.4.1. BUFFER MODEL PARAMETERS ____51
4.4.2. SIGNAL QUALITY
SPECIFICATIONS________________52
4.4.2.1. Ringback ____________________53
4.4.2.2. Settling Time _________________54
5.0. TCP PENTIUM PROCESSOR MECHANICAL
SPECIFICATIONS_____________________ 55
5.1. TCP Mechanical Diagrams_____________ 55
6.0. TCP PENTIUM PROCESSOR
THERMAL SPECIFICATIONS ___________ 61
6.1. Measuring Thermal Values_____________ 61
6.2. Thermal Equations ___________________ 61
6.3. TCP Thermal Characteristics ___________ 61
6.4. PC Board Enhancements______________ 61
6.4.1. STANDARD TEST BOARD
CONFIGURATION _______________ 63
7.0. SPGA PENTIUM PROCESSOR
SPECIFICATIONS_____________________ 63
7.1. SPGA Pentium Processor with Voltage
Reduction Technology Differences from 3.3V
Pentium Processor___________________ 63
7.1.1. Features Removed _______________ 63
7.1.2. Maximum Rating _________________ 64
7.1.3. DC Specifications ________________ 64
7.1.3.1 Power Sequencing_____________ 67
7.1.4. AC Specifications ________________ 67
7.1.4.1. Power and Ground ____________ 67
7.1.4.2. Decoupling Recommendations___ 67
7.1.4.3. Connection Specifications ______ 67
7.1.4.4. AC Timings __________________ 68
7.1.5. Thermal Specifications ____________ 68
7.1.6. SPGA Package Differences ________ 68
7.1.6.1 Pinout_________________________ 68
7.1.6.2. Package Dimensions __________ 68
7.1.7. I/O Buffer Models___________________ 68
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PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
3
1.0.
INTRODUCTION
Intel is manufacturing a reduced power version of the
latest Pentium
processor, the Pentium processor
with voltage reduction technology, targeting the
mobile market. Voltage reduction technology allows
the processor to "talk" to industry standard 3.3-volt
components while its inner core, operating at
2.9 volts, consumes less power to promote a longer
battery life. The Pentium processor with voltage
reduction technology is offered in the Tape Carrier
Package (TCP) and the Staggered Pin Grid Array
(SPGA) package. It has all the advanced features of
the 3.3V Pentium except for the differences listed in
sections 3.1 and 7.1.1.
The Pentium processor with voltage reduction
technology has several features which allow high-
performance notebooks to be designed with the
Pentium processor, including the following:
TCP dimensions are ideal for small form-factor
designs.
TCP has superior thermal resistance
characteristics.
2.9V core and 3.3V I/O buffer V
CC
inputs reduce
power consumption significantly, while
maintaining 3.3V compatibility externally.
The SL Enhanced feature set, which was initially
implemented in the Intel486
TM
CPU.
The architecture and internal features of the Pentium
processor with voltage reduction technology are
identical to the desktop version of the Pentium
processor specifications provided in the
Pentium
Processor Family Developer's Manual, Volume 1:
Pentium
Processors
., except several features not
used in mobile applications have been eliminated to
streamline it for mobile applications.
This document should be used in conjunction with
the following related Pentium processor documents.
Pentium
Processor Family Developer's Manual,
Volume 1: Pentium
Processors
(Order Number:
241428)
Pentium
Processor Family Developer's Manual,
Volume 3: Architecture and Programming
Manual
(Order Number: 241430)
2.0.
MICROPROCESSOR
ARCHITECTURE OVERVIEW
The Pentium processor with voltage reduction
technology extends the Intel Pentium family of
microprocessors. It is compatible with a host of other
Intel products.
The Pentium processor family consists of the
Pentium processor with voltage reduction technology
described in this document, the original mobile
Pentium processor and the various desktop Pentium
processors. "Pentium processor" will be used in this
document to refer to the entire Pentium processor
family in general.
The mobile Pentium processor family architecture
contains all of the features of the Intel486 CPU
family, and provides significant enhancements and
additions including the following:
Superscalar Architecture
Dynamic Branch Prediction
Pipelined Floating-Point Unit
Improved Instruction Execution Time
Separate 8K Code and 8K Data Caches
Writeback MESI Protocol in the Data Cache
64-Bit Data Bus
Bus Cycle Pipelining
Address Parity
Internal Parity Checking
Execution Tracing
Performance Monitoring
IEEE 1149.1 Boundary Scan
System Management Mode
Virtual Mode Extensions
Voltage Reduction Technology
SL Power Management Features
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
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4
2.1.
Mobile Pentium
Processor
Family Architecture
The application instruction set of the Pentium
processor family includes the complete Intel486 CPU
family instruction set with extensions to
accommodate some of the additional functionality of
the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of CPUs.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one clock,
or one floating point instruction (under certain
circumstances, two floating-point instructions) in one
clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch code
in a linear fashion, and one that prefetches code
according to the Branch Target Buffer (BTB) so the
needed code is almost always prefetched before it is
needed for execution.
The floating-point unit has been completely
redesigned over the Intel486 CPU. Faster algorithms
provide up to 10X speed-up for common operations
including add, multiply and load.
Pentium processors include separate code and data
caches integrated on-chip to meet performance
goals. Each cache is 8 Kbytes in size, with a 32-byte
line size and is 2-way set associative. Each cache
has a dedicated Translation Lookaside Buffer (TLB)
to translate linear addresses to physical addresses.
The data cache is configurable to be writeback or
writethrough on a line-by-line basis and follows the
MESI protocol. The data cache tags are triple-ported
to support two data transfers and an inquire
cycle in the same clock. The code cache is an
inherently write-protected cache. The code cache
tags are also triple ported to support snooping and
split line accesses. Individual pages can be
configured as cacheable or non-cacheable by
software or hardware. The caches can be enabled or
disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate. Burst
read and burst writeback cycles are supported by the
Pentium processors. In addition, bus cycle pipelining
has been added to allow two bus cycles to be in
progress simultaneously. The Pentium processors'
MMU contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.
The Pentium processors have added significant data
integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis.
Address parity checking and internal parity checking
features have been added along with a new
exception, the machine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased. To
address this, the Pentium processors have increased
test and debug capability. The Pentium processors
implement IEEE Boundary Scan (Standard 1149.1).
In addition, the Pentium processors have specified
four breakpoint pins that correspond to each of the
debug registers and externally indicate a breakpoint
match. Execution tracing provides external
indications when an instruction has completed
execution in either of the two internal pipelines, or
when a branch has been taken.
System Management Mode (SMM) has been
implemented along with some extensions to the SMM
architecture. Enhancements to the virtual 8086 mode
have been made to increase performance by
reducing the number of times it is necessary to trap
to a virtual 8086 monitor.
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