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Электронный компонент: STEL-2176

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R
STEL-2176
User Manual
STel-MAN-97709
STEL-2176
Digital Mod/Demod ASIC
16/64/256 QAM Receiver
with FEC
QPSK/16 QAM Transmitter
with FEC
STEL-2176
User Manual
TRADEMARKS
Stanford Telecom
and STEL
are registered trademarks of Stanford Telecommunications, Incorporated.
User Manual
STEL-2176
FOREWORD
The Telecom Component Products Division of Stanford Telecommunications, Inc., is pleased to provide its
customers with this copy of the STEL 2176 User Manual.
This User Manual contains product information for the STEL 2176 and is being provided to assist our customers in
understanding the advantages to be gained by integrating both the receiver and transmitter functions as an integral
portion of their cable modem chip.
Recipients of this User Manual should note that the content contained here-in is subject to change. The content of
this User Manual will be updated to reflect the latest technical data, without notice to the recipients of this
document.
STEL-2176
User Manual
ERRATA for STEL-2176
Supported Modes of Operation:
Downstream
FEC
16 QAM
64 QAM
256 QAM
Annex A
X
X
Annex B
X
X
Annex C
X
X
Upstream
STD
BPSK
QPSK
16 QAM
MCNS
X
X
DAVIC
X
X
User Manual
i
STEL-2176
TABLE OF CONTENTS
PARAGRAPH
PAGE
KEY FEATURES.....................................................................................................................................
1
RECEIVER...........................................................................................................................................
1
TRANSMITTER ...................................................................................................................................
1
INTRODUCTION ..................................................................................................................................
2
RECEIVER OVERVIEW........................................................................................................................
2
TRANSMITTER OVERVIEW ................................................................................................................
2
MECHANICAL SPECIFICATIONS ........................................................................................................
3
208-PIN SQFP PACKAGE.....................................................................................................................
3
ELECTRICAL SPECIFICATIONS ........................................................................................................
8
RECEIVER .............................................................................................................................................
10
OVERVIEW.........................................................................................................................................
10
FUNCTIONAL BLOCKS ......................................................................................................................
11
ADC..............................................................................................................................................
11
Microcontroller Interface.................................................................................................................
11
Master Receive Clock Generator......................................................................................................
12
QAM Demodulator Blocks..............................................................................................................
13
FEC Decoder Blocks .......................................................................................................................
14
RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS ....................................................................
20
PROGRAMMING THE 2176 RECEIVE FUNCTIONS .............................................................................
20
REGISTER DESCRIPTIONS..................................................................................................................
20
Bank 0 - Universal Registers (Group 1).............................................................................................
20
Bank 0 - QAM Demodulator Registers Universal Registers (Group 2) ................................................
22
Bank 1 - FEC Registers (Group 3).....................................................................................................
30
TIMING.................................................................................................................................................
35
NO GAP, PARALLEL MODE ...............................................................................................................
35
NO GAP, SERIAL MODE .....................................................................................................................
35
GAPS, PARALLEL MODE....................................................................................................................
35
GAPS, SERIAL MODE .........................................................................................................................
35
TRANSMITTER.....................................................................................................................................
39
INTRODUCTION ................................................................................................................................
39
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS .............................................................................
39
DATA PATH DESCRIPTION ...............................................................................................................
39
Bit SYNC Block ..............................................................................................................................
39
Bit Encoder Block ...........................................................................................................................
41
Symbol Mapper Block.....................................................................................................................
45
Nyquist FIR Filter...........................................................................................................................
50
Interpolating Filter .........................................................................................................................
50
Modulator .....................................................................................................................................
51
10-Bit DAC.....................................................................................................................................
52