1
File Number
2930.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 2000
HS-26CT32RH
Radiation Hardened Quad Differential Line
Receiver
The Intersil HS-26CT32RH is a differential line receiver
designed for digital data transmission over balanced lines
and meets the requirements of EIA standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
The HS-26CT32RH has an input sensitivity typically of
200mV over the common mode input voltage range of
7V.
The receivers are also equipped with input fail safe circuitry,
which causes the outputs to go to a logic "1" when the inputs
are open. Enable and Disable functions are common to all
four receivers.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95631. A "hot-link" is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
Logic Diagram
Features
Electrically Screened to SMD # 5962-95631
QML Qualified per MIL-PRF-38535 Requirements
1.2 Micron Radiation Hardened CMOS
- Total Dose . . . . . . . . . . . . . . . . . . . .Up to 300kRAD(Si)
Latchup Free
EIA RS-422 Compatible Outputs
TTL Compatible Inputs
Input Fail Safe Circuitry
High Impedance Inputs when Disabled or Powered Down
Low Power Dissipation Standby (Max). . . . . . . . . .138mW
Single 5V Supply
Full Military Temperature Range . . . . . . . -55
o
C to 125
o
C
Pinouts
HS1-26CT32RH (SBDIP) CDIP2-T16
TOP VIEW
HS9-26CT32RH (FLATPACK) CDFP4-F16
TOP VIEW
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP.
RANGE (
o
C)
5962F9563101QEC
HS1-26CT32RH-8
-55 to 125
5962F9563101QXC
HS9-26CT32RH-8
-55 to 125
5962F9563101V9A
HS0-26CT32RH-Q
25
5962F9563101VEC
HS1-26CT32RH-Q
-55 to 125
5962F9563101VXC
HS9-26CT32RH-Q
-55 to 125
HS1-26CT32RH/PROTO HS1-26CT32RH/PROTO
-55 to 125
HS9-26CT32RH/PROTO HS9-26CT32RH/PROTO
-55 to 125
ENABLE
ENABLE
AOUT
BOUT
COUT
DIN
DOUT
DIN
CIN CIN
BIN BIN
AIN AIN
+
-
+
-
+
-
+
-
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
AIN
AIN
AOUT
ENABLE
COUT
CIN
GND
CIN
VDD
BIN
BOUT
ENABLE
DOUT
DIN
DIN
BIN
AIN
AIN
AOUT
ENABLE
COUT
CIN
CIN
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VDD
BIN
BIN
BOUT
ENABLE
DOUT
DIN
DIN
Data Sheet
October 1999
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
84 mils x 130 mils
(2140
m x 3290
m)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 10k
1k
Top Metallization:
M1: Mo/Tiw
Thickness: 5800
M2: Al/Si/Cu
Thickness: 10k
1k
Substrate:
AVLSI1RA
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
V
DD
(When Powered Up)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
240
Bond Pad Size:
110
m x 100
m
Metallization Mask Layout
HS-26CT32RH
AIN
V
DD
BIN
AIN (2)
AOUT (3)
ENAB (4)
COUT (5)
CIN (6)
(8)
(9)
(14) BIN
(13) BOUT
(12) ENAB
(11) DOUT
(10) DIN
(1)
(16)
(15)
(7)
CIN
GND
DIN
HS-26CT32RH
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