148

March 1997

82C237

CMOS High Performance

Programmable DMA Controller

Features

· Fully Compatible with Intersil 82C37A

- 82C237 May be Used in 8MHz and 12.5MHz 82C37A

Sockets

· Optimized for 10MHz and 12.5MHz 80C286 Systems
· Special Mode Permits 16-Bit, Zero Wait State DMA

Transfers

· High Speed Data Transfers:

- Up to 6.25MBytes/sec with 12.5MHz Clock in

Normal Mode

- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit

Mode

· Compatible with the NMOS 8237A
· Four Independent Maskable Channels with Autoinitial-

ization Capability

· Cascadable to any Number of Channels
· Memory-to-Memory Transfers
· Static CMOS Design Permits Low Power Operation

- ICCSB = 10

A Maximum

- ICCOP = 2mA/MHz Maximum

· Fully TTL/CMOS Compatible
· Internal Registers may be Read from Software

Description

The 82C237 is a modified version of the 82C37A. The
82C237 is fully software and pin for pin compatible with the
82C37A but provides an additional mode for 16-bit DMA
transfers, as well as enhanced speed. Each channel may be
individually programmed for 8-bit or 16-bit data transfers.
The 82C237 controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C237 is designed to be used with an external address
latch, such as the 82C82, to demultiplex the most significant
8 bits of address. An additional latch is required to
temporarily store the most significant 8 bits of data if 16-bit
memory-to-memory transfers are desired. The 82C237 can
be used with industry standard microprocessors such as
80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80,
NSC800, 80186 and others. Multimode programmability
allows the user to select from three basic types of DMA
services, and reconfiguration under program control is
possible even with the clock to the controller stopped. Each
channel has a full 64K address and word count range, and
may be programmed to autoinitialize these registers
following DMA termination (end of process).

Ordering Information

PACKAGE

TEMPERATURE

RANGE

8MHz

12.5MHz

PKG. NO.

PDIP

C to +70

CP82C237

CP82C237-12

E40.6

-40

C to +85

IP82C237

IP82C237-12

E40.6

PLCC

C to +70

CS82C237

CS82C237-12

N44.65

-40

C to +85

IS82C237

IS82C237-12

N44.65

SBDIP

C to +70

CD82C237

CD82C237-12

F40.6

-40

C to +85

ID82C237

ID82C237-12

F40.6

-55

C to +125

MD82C237/B

MD82C237-12/B

F40.6

SMD#

5962-9054304MQA

5962-9054305MQA

F40.6

CLCC

-55

C to +125

MR82C237/B

MR82C237-12/B

J44.A

SMD#

5962-9054304MXA

5962-9054305MXA

J44.A

FN2965.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

149

82C237

Block Diagram

Pinouts

82C237 (DIP)

TOP VIEW

82C237 (CLCC/PLCC)

TOP VIEW

IOR

IOW

MEMR

MEMW

DWLE

READY

HLDA

ADSTB

AEN

HRQ

CLK

RESET

DACK2

DACK3

DREQ3

DREQ2

DREQ1

DREQ0

(GND) VSS

EOP

DB0

DB1

DB2

DB3

DB4

DACK0

DACK1

DB5

DB6

DB7

(NOTE)

DACK2

NC
NC

CLK

HRQ

DB0

DB1

DB2

DB3

DB4

EOP

DRE

ADSTB

AEN

RESET

HLDA

NOTE: See Pin Description.

A4 - A7

EOP

RESET

READY

CLK

AEN

ADSTB

MEMR

MEMW

IOR

IOW

TIMING

AND

CONTROL

DREQ0 -

HLDA

HRQ

DACK0 -

PRIORITY

ENCODER

AND

ROTATING

PRIORITY

LOGIC

DACK3

DREQ3

COMMAND

(8)

MASK

(4)

REQUEST

(4)

MODE

(4 x 6)

STATUS

(8)

TEMPORARY

(8)

INTERNAL DATA BUS

DECREMENTOR

COUNT REG (16)

TEMP WORD

INC DECREMENTOR

REG (16)

TEMP ADDRESS

BUFFER

16-BIT BUS

READ BUFFER

ADDRESS

BASE

(16)

WORD

BASE

COUNT

(16)

READ WRITE BUFFER

ADDRESS

CURRENT

(16)

WORD

CURRENT

COUNT

(16)

16-BIT BUS

BUFFER

WRITE

BUFFER

READ

BUFFER

OUTPUT

CONTROL

COMMAND

D0 - D1

A0 - A3

BUFFER

DB0

DB7

DWLE

DATA-WIDTH

(4)

150

82C237

Pin Description

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

: is the +5V power supply pin. A 0.1

F capacitor between pins 31 and 20 is recommended for

decoupling.

GND

Ground

CLK

CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C237
operations. This input may be driven from DC to 12.5MHz for the 82C237-12 or from DC to 8MHz
for the 82C237. The Clock may be stopped in either state for standby operation.

CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus
for CPU communications.

RESET

RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. The Data-Width register is set to perform 8-bit transfers on all channels (82C237 only).
Following a Reset, the controller is in an idle cycle.

READY

READY: This signal can be used to extend the memory read and write pulses from the 82C237 to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 14 for timing. READY is ignored in verify transfer mode.

HLDA

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of clock, during which time HLDA must not transition.

DREQ0-

DREQ3

16-19

DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. In 16-bit
Transfer mode (82C237 only), each DREQ channel may be programmed to perform either 8-bit or
16-bit DMA transfers.

DB0-DB7

21-23
26-30

I/O

DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C237 control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by AD-
STB. In memory-to-memory operations, data from the memory enters the 82C237 on the data bus
during the read-from-memory transfer, then during the write-to-memory transfer, the data bus out-
puts write the data into the new memory location.

IOR

I/O

I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C237 to access data from the peripheral during a DMA Write transfer.

IOW

I/O

I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C237. In the Active cycle, it is an output
control signal used by the 82C237 to load data to the peripheral during a DMA Read transfer.

151

82C237

EOP

I/O

END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information
concerning the completion of DMA services is available at the bidirectional EOP pin.
The 82C237 allows an external signal to terminate an active DMA service by pulling the EOP pin
low. A pulse is generated by the 82C237 when terminal count (TC) for any channel is reached,
except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will
be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor
to V

When an EOP pulse occurs, whether internally or externally generated, the 82C237 will terminate
the service, and if autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.

A0-A3

32-35

I/O

ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle
cycle, they are inputs and are used by the 82C237 to address the control register to be loaded or
read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. When
in 16-bit mode (82C237 only), and the active channel is a 16-bit channel (as defined by the Data-
Width register), then A0 will remain low during the entire transfer (i.e. an even word address will al-
ways be generated).

A4-A7

37-40

ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of
address. These lines are enabled only during the DMA service.

HRQ

HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.
When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,
the 82C237 issues HRQ. The HLDA signal then informs the controller when access to the system
busses is permitted. For stand-alone operation where the 82C237 always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.

DACK0-

DACK3

14, 15
24, 25

DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one
has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them
to active low.

AEN

ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits
onto the system address bus. AEN can also be used to disable other system bus drivers during DMA
transfers. AEN is active HIGH.

ADSTB

ADDRESS STROBE: This is an active high signal used to control latching of the upper address
byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.
During block operations, ADSTB will only be issued when the upper address byte must be updated,
thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling
edge of the 82C237 clock.

MEMR

MEMORY READ: The Memory Read signal is an active low three-state output used to access data
from the selected memory location during a DMA Read or a memory-to-memory transfer.

MEMW

MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the
selected memory location during a DMA Write or a memory-to-memory transfer.

DWLE

DATA-WIDTH, LATCH ENABLE: In normal 8-bit transfer mode (16-bit transfer mode not enabled),
this output is always high impedance three-stated. In 16-bit transfer mode (82C237 only), this output
serves a dual purpose. During S1 cycles, the DWLE output indicates the data width (0 = 16-bit, 1 =
8-bit) of the active channel. During memory-to-memory transfers, the DWLE output is used to enable
an external latch which temporarily stores the 8 most significant bits of data during the read-from-
memory transfer. DWLE enables this byte of data onto the data bus during the write-to-memory
transfer of a memory-to-memory operation.

Pin Description

(Continued)

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

152

82C237

Functional Description

The 82C237 is an improved version of the Intersil 82C37A
DMA controller and is fully software and pin for pin compati-
ble with the 82C37A. All operational and pin descriptions of
the 82C37A apply to the 82C237 with additional features
noted in the section titled 82C237 Operation.

The 82C237 direct memory access controller is designed to
improve the data transfer rate in systems which must
transfer data from an I/O device to memory, or move a block
of memory to an I/O device. It will also perform memory-to-
memory block moves, or fill a block of memory with data
from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the 82C237 to control data movement
with software transparency.

The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor move or repeated string
instructions. Memory-to-memory operations require
temporary internal storage of the data byte between
generation of the source and destination addresses, so
memory-to-memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rates
obtainable with the 82C237 are shown in Figure 1.

The block diagram of the 82C237 is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from CLK input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.

DMA Operation

In a system, the 82C237 address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller's outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C237
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously

been programmed into the controller via the Command,
Mode, Address, and Word Count registers.

For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the 82C237 Current and Base Address registers for a
particular channel, and the length of the block is loaded into
the channel's Word Count register. The corresponding Mode
register is programmed for a memory-to-I/O operation (read
transfer), and various options are selected by the Command
register and the other Mode register bits. The channel's
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.

Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count register
underflows, or an external EOP is applied.

To further understand 82C237 operation, the states
generated by each CLK cycle must be considered. The DMA
controller operates in two major cycles, active and idle. After
being programmed, the controller is normally idle until a
DMA request occurs on an unmasked channel, or a software
request is given. The 82C237 will then request control of the
system busses and enter the active cycle. The active cycle is
composed of several internal states, depending on what
options have been selected and what type of operation has
been requested.

82C237

TRANSFER

TYPE

8MHz

12.5MHz

UNIT

8-BIT

16-BIT

8-BIT

16-BIT

Compressed

4.00

8.00

6.25

12.5

MByte/sec

Normal I/O

2.67

5.34

4.17

8.34

MByte/sec

Memory-to-
Memory

1.00

2.00

1.56

3.12

MByte/sec

FIGURE 1. DMA TRANSFER RATES

NAME

SIZE

NUMBER

Base Address Registers

16-Bits

Base Word Count Registers

16-Bits

Current Address Registers

16-Bits

Current Word Count Registers

16-Bits

Temporary Address Register

16-Bits

Temporary Word Count Register

16-Bits

Status Register

8-Bits

Command Register

8-Bits

Temporary Register

8-Bits

Mode Registers

6-Bits

Mask Register

4-Bits

Request Register

4-Bits

Data-Width Register (See Note)

4-Bits

NOTE: 82C237 only

FIGURE 2. 82C237 INTERNAL REGISTERS

153

82C237

The 82C237 can assume seven separate states, each
composed of one full CLK period. State I (SI) is the idle
state. It is entered when the 82C237 has no valid DMA
requests pending, at the end of a transfer sequence, or
when a RESET or Master Clear has occurred. While in SI,
the DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).

State 0 (S0) is the first state of a DMA service. The 82C237
has requested a hold but the processor has not yet returned
an acknowledge. The 82C237 may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the READY line on
the 82C237. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.

Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the 82C237 in I/O-to-memory or
memory-to-I/O DMA transfers.

Memory-to-memory transfers require a read-from and a write-
to memory to complete each transfer. The States, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four states (S21, S22,
S23, S24) for the write-to-memory half of the transfer.

Idle Cycle

When no channel is requesting service, the 82C237 will
enter the idle cycle and perform "SI" States. In this cycle, the
82C237 will sample the DREQ lines on the falling edge of
every CLK cycle to determine if any channel is requesting a
DMA service.

Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
82C237. When CS is low and HLDA is low, the 82C237
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by read-
ing from or writing to the internal registers.

The 82C237 may be programmed with the clock stopped,
provided that HLDA is low and at least one rising CLK edge
has occurred after HLDA was driven low, so the controller is
in an SI state. Address lines A0-A3 are inputs to the device
and select which registers will be read or written. The IOR
and IOW lines are used to select and time the read or write
operations. Due to the number and size of the internal regis-
ters, an internal flip-flop called the First/Last Flip-Flop is used
to generate an additional bit of address. The bit is used to
determine the upper or lower byte of the 16-bit Address and
Work Count registers. The flip-flop is reset by Master Clear
or RESET. Separate software commands can also set or
reset this flip-flop.

Special software commands can be executed by the 82C237
in the Program Condition. These commands are decoded as
sets of addresses with CS, IOR, and IOW. The commands
do not make use of the data bus. Instructions include Set
and Clear First/Last Flip-Flop, Master Clear, Clear Mode
Register Counter, and Clear Mask Register.

Active Cycle

When the 82C237 is in the Idle cycle, and a software request
or an unmasked channel requests a DMA service, the
device will issue HRQ to the microprocessor and enter the
Active cycle. It is in this cycle that the DMA service will take
place, in one of four modes:

Single Transfer Mode - In single transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
"rolls over" from zero to FFFFH, a terminal count bit in the
status register is set, an EOP pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.

DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C237 and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.

Block Transfer Mode - In Block Transfer mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.

Demand Transfer Mode - In Demand Transfer mode the
device continues making transfers until a TC or external
EOP is encountered, or until DREQ goes inactive. Thus,
transfer may continue until the I/O device has exhausted its
data capacity. After the I/O device has had a chance to catch
up, the DMA service is reestablished by means of a DREQ.
During the time between services when the microprocessor
is allowed to operate, the intermediate values of address
and word count are stored in the 82C237 Current Address
and Current Word Count registers. Higher priority channels
may intervene in the demand process, once DREQ has
gone inactive. Only an EOP can cause an Autoinitialization
at the end of service. EOP is generated either by TC or by
an external signal.

Cascade Mode - This mode is used to cascade more than
one 82C237 for simple system expansion. The HRQ and
HLDA signals from the additional 82C237 are connected to
the DREQ and DACK signals respectively of a channel for

154

82C237

the initial 82C237. This allows the DMA requests of the
additional device to propagate through the priority network
circuitry of the preceding device. The priority chain is
preserved and the new device must wait for its turn to
acknowledge requests. Since the cascade channel of the
initial 82C237 is used only for prioritizing the additional
device, it does not output an address or control signals of its
own. These could conflict with the outputs of the active chan-
nel in the added device. The initial 82C237 will respond to
DREQ and generate DACK but all other outputs except HRQ
will be disabled. An external EOP will be ignored by the ini-
tial device, but will have the usual effect on the added
device.

Figure 3 shows two additional devices cascaded with an
initial device using two of the initial device's channels. This
forms a two-level DMA system. More 82C237s could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.

When programming cascaded controllers, start with the first
level device (closest to the microprocessor). After RESET,
the DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device's mask bits function normally on
cascaded channels, so they may be used to inhibit second-
level services.

Transfer Types

Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write and
Verify. Write transfers move data from an I/O device to the
memory by activating MEMW and IOR. Read transfers move
data from memory to an I/O device by activating MEMR and
IOW.

Verify transfers are pseudo-transfers. The 82C237 operates
as in Read or Write transfers generating addresses and
responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted

for memory-to-memory operation. READY is ignored during
verify transfers.

Autoinitialize - By setting bit 4 in the Mode register, a
channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count registers are automatically restored
from the Base Address and Base Word Count registers of the
channel following EOP. The base registers are loaded simul-
taneously with the current registers by the microprocessor
and remain unchanged throughout the DMA service. The
mask bit is not set when the channel is in Autoinitialize mode.
Following Autoinitialization, the channel is ready to perform
another DMA service, without CPU intervention, as soon as a
valid DREQ is detected, or software request made.

Memory-to-Memory - To perform block moves of data from
one memory address space to another with minimum of
program effort and time, the 82C237 includes a memory-to-
memory transfer feature. Setting bit 0 in the Command
register selects channels 0 and 1 to operate as memory-to-
memory transfer channels.

The transfer is initiated by setting the software or hardware
DREQ for channel 0. The 82C237 requests a DMA service in
the normal manner. After HLDA is true, the device, using
four-state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is the
source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the 82C237 internal Temporary reg-
ister. Another four-state transfer moves the data to memory
using the address in channel one's Current Address register
and incrementing or decrementing it in the normal manner.
The channel 1 Current Word Count is decremented.

When the word count of channel 1 decrements to FFFFH, a
TC is generated causing an EOP output, terminating the
service, and setting the channel 1 TC bit in the Status register.
The channel 1 mask bit will also be set, unless the channel 1
mode register is programmed for autoinitialization. Channel 0
word count decrementing to FFFFH will not set the channel 0
TC bit in the status register or generate an EOP, or set the
channel 0 mask bit in this mode. It will cause an autoinitializa-
tion of channel 0, if that option has been selected.

If full Autoinitialization for a memory-to-memory operation is
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA service will terminate, and
channel 1 will autoinitialize but channel 0 will not.

In memory-to-memory mode, Channel 0 may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.

The 82C237 will respond to external EOP signals during
memory-to-memory transfers, but will only relinquish the

80C86/88

MICRO-

PROCESSOR

HRQ

HLDA

DREQ

DACK

DREQ

DACK

1ST LEVEL

82C237

HRQ

HLDA

82C237

HRQ

HLDA

82C237

ADDITIONAL

DEVICES

2ND LEVEL

INITIAL DEVICE

FIGURE 3. CASCADED 82C237s

155

82C237

system busses after the transfer is complete (i.e. after an
S24 state). It should be noted that an external EOP cannot
cause the channel 0 Address and Word Count registers to
autoinitialize, even if the Mode register is programmed for
autoinitialization. An external EOP will autoinitialize the
channel 1 registers, if so programmed. Data comparators in
block search schemes may use the EOP input to terminate
the service when a match is found. The timing of memory-to-
memory transfers in found in Figure 13. Memory-to-memory
operations can be detected as an active AEN with no DACK
outputs.

Priority - The 82C237 has two types of priority encoding
available as software selectable options. The first is Fixed
Priority which fixes the channels in priority order based upon
the descending value of their numbers. The channel with the
lowest priority is 3 followed by 2, 1 and the highest priority
channel, 0. After the recognition of any one channel for ser-
vice, the other channels are prevented from interfering with
the service until it is completed.

The second scheme is Rotating Priority. The last channel to
get service becomes the lowest priority channel with the
others rotating accordingly. The next lower channel from the
channel serviced has highest priority on the following
request. Priority rotates every time control of the system bus-
ses is returned to the processor.

Rotating Priority

With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
the system.

Regardless of which priority scheme is chosen, priority is
evaluated every time a HLDA is returned to the 82C237.

Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the 82C237
can compress the transfer time to two clock cycles. From
Figure 12 it can be seen that state S3 is used to extend the
access time of the read pulse. By removing state S3, the
read pulse width is made equal to the write pulse width and a
transfer consists only of state S2 to change the address and
state S4 to perform the read/write. S1 states will still occur
when A8-A15 need updating (see Address Generation).
Timing for compressed transfers is found in Figure 15. EOP
will output in S2 if compressed timing is selected. Com-
pressed timing is not allowed for memory-to-memory trans-
fers.

Address Generation - In order to reduce pin count, the
82C237 multiplexes the eight higher order address bits on
the data lines. State S1 is used to output the higher order

address bits to an external latch from which they may be
placed on the address bus. The falling edge of Address
Strobe (ADSTB) is used to load these bits from the data
lines to the latch. Address Enable (AEN) is used to enable
the bits onto the address bus through a three-state enable.
The lower order address bits are output by the 82C237
directly. Lines A0-A7 should be connected to the address
bus. Figure 12 shows the time relationships between CLK,
AEN, ADSTB, DB0-DB7 and A0-A7.

During Block and Demand Transfer mode service, which
include multiple transfers, the addresses generated will be
sequential. For many transfers the data held in the external
address latch will remain the same. This data need only
change when a carry or borrow from A7 to A8 takes place in
the normal sequence of addresses. To save time and speed
transfers, the 82C237 executes S1 states only when
updating of A8-A15 in the latch is necessary. This means for
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings of 255 clock cycles
for each 256 transfers.

Programming

The 82C237 will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising CLK edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.

Note that a problem can occur if a DMA request occurs on
an unmasked channel while the 82C237 is being pro-
grammed. For instance, the CPU may be starting to repro-
gram the two byte Address register of channel 1 when
channel 1 receives a DMA request. If the 82C237 is enabled
(bit 2 in the Command register is 0), and channel 1 is
unmasked, a DMA service will occur after only one byte of
the Address register has been reprogrammed. This condi-
tion can be avoided by disabling the controller (setting bit 2
in the Command register) or masking the channel before
programming any of its registers. Once the programming is
complete, the controller can be enabled/unmasked.

After power-up it is suggested that all internal locations be
loaded with some known value, even if some channels are
unused. This will aid in debugging.

Register Description

Current Address Register - Each channel has a 16-bit
Current Address register. This register holds the value of the
address used during DMA transfers. The address is auto-
matically incremented or decremented by one after each
transfer and the values of the address are stored in the Cur-
rent Address register during the transfer. This register is writ-
ten or read by the microprocessor in successive 8-bit bytes.
See Figure 6 for programming information. It may also be
reinitialized by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP. In memory-to-
memory mode, the channel 0 Current Address register can
be prevented from incrementing or decrementing by setting
the address hold bit in the Command register.

1ST

SERVICE

Highest

Lowest

2nd

SERVICE

Service

3rd

SERVICE

Service

Request

Service

156

82C237

Current Word Count Register - Each channel has a 16-Bit
Current Word Count register. This register determines the
number of transfers to be performed. The actual number of
transfers will be one more than the number programmed in
the Current Word Count register (i.e., programming a count
of 100 will result in 101 transfers). The word count is
decremented after each transfer. When the value in the
register goes from zero to FFFFH, a TC will be generated.
This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.

Base Address and Base Word Count Registers - Each
Channel has a pair of Base Address and Base Word Count
registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialize these
values are used to restore the current registers to their
original values. The base registers are written simulta-
neously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor. See
Figure 6 for programming information. These registers can-
not be read by the microprocessor.

Command Register - This 8-bit register controls the opera-
tion of the 82C237. It is programmed by the microprocessor
and is cleared by RESET or a Master Clear instruction. The
following diagram lists the function of the Command register
bits. See Figure 4 for Read and Write addresses.

Mode Register - Each channel has a 6-bit Mode register
associated with it. When the register is being written to by
the microprocessor in the Program condition, bits 0 and 1
determine which channel Mode register is to be written.
When the processor reads a Mode register, bits 0 and 1 will
both be ones. See the following diagram and Figure 4 for
Mode register functions and addresses.

Request Register - The 82C237 can respond to requests
for DMA service which are initiated by software as well as by
a DREQ. Each channel has a request bit associated with it in
the 4-bit Request register. These are non-maskable and
subject to prioritization by the Priority Encoder network.
Each register bit is set or reset separately under software
control. The entire register is cleared by a RESET or Master
Clear instruction. To set or reset a bit, the software loads the
proper form of the data word. See Figure 4 for register
address coding, and the following diagram for Request
register format. A software request for DMA operation can
be made in block or single modes. For memory-to-memory
transfers, the software request for channel 0 should be set.
When reading the Request register, bits 4-7 will always read
as ones, and bits 0-3 will display the request bits of channels
0-3 respectively.

Command Register

7 6 5 4 3 2 1 0

BIT NUMBER

0
1

Memory-to-memory disable
Memory-to-memory enable

0
1
X

Channel 0 address hold disable
Channel 0 address hold enable
If bit 0 = 0

0
1

Controller enable
Controller disable

0
1
X

Normal timing
Compressed timing
If bit 0 = 1

0
1

Fixed priority
Rotating priority

0
1
X

Late write selection
Extended write selection
If bit 3 = 1

0
1

DREQ sense active high
DREQ sense active low

0
1

DACK sense active low
DACK sense active high

Mode Register

7 6 5 4 3 2 1 0

BIT NUMBER

00
01
10
11

Channel 0 select
Channel 1 select
Channel 2 select
Channel 3 select
Readback

00
01
10
11

Verify transfer
Write transfer
Read transfer
Illegal
If bits 6 and 7 = 11

0
1

Autoinitialization disable
Autoinitialization enable

0
1

Address increment select
Address decrement select

00
01
10
11

Demand mode select
Single mode select
Block mode select
Cascade mode select

Mode Register

7 6 5 4 3 2 1 0

BIT NUMBER

00
01
10
11

Select Channel 0
Select Channel 1
Select Channel 2
Select Channel 3

0
1

Reset request bit
Set request bit

Don't Care,

Write

Bits 4-7

All Ones,

Read

157

82C237

Mask Register - Each channel has associated with it a mask
bit which can be set to disable an incoming DREQ. Each
mask bit is set when its associated channel produces an EOP
if the channel is not programmed to Autoinitialize. Each bit of
the 4-bit Mask register may also be set or cleared separately
or simultaneously under software control. The entire register
is also set by a RESET or Master clear. This disables all hard-
ware DMA requests until a Clear Mask Register instruction
allows them to occur. The instruction to separately set or clear
the mask bits is similar in form to that used with the Request
register. Refer to the following diagram and Figure 4 for
details. When reading the Mask register, bits 4-7 will always
read as logical ones, and bits 0-3 will display the mask bits of
channels 0-3, respectively. The 4-bits of the mask register
may be cleared simultaneously by using the Clear Mask Reg-
ister command (see software commands section).

All four bits of the Mask register may also be written with a
single command.

Status Register - The Status register is available to be read
out of the 82C237 by the microprocessor. It contains
information about the status of the devices at this point. This
information includes which channels have reached a terminal
count and which channels have pending DMA requests. Bits
0-3 are set every time a TC is reached by that channel or an
external EOP is applied. These bits are cleared upon RESET,
Master Clear, and on each Status Read. Bits 4-7 are set
whenever their corresponding channel is requesting service,
regardless of the mask bit state. If the mask bits are set, soft-
ware can poll the Status register to determine which channels
have DREQs, and selectively clear a mask bit, thus allowing
user defined service priority. Status bits 4-7 are updated while
the clock is high, and latched on the falling edge. Status Bits
4-7 are cleared upon RESET or Master Clear.

Temporary Register - The Temporary register is used to hold
data during memory-to-memory transfers. Following the com-
pletion of the transfers, the last byte moved can be read by
the microprocessor. The Temporary register always contains
the last byte transferred in the previous memory-to-memory
operation, unless cleared by a RESET or Master Clear.

Mask Register

7 6 5 4 3 2 1 0

BIT NUMBER

00
01
10
11

Select channel 0 mask bit
Select channel 1 mask bit
Select channel 2 mask bit
Select channel 3 mask bit

0
1

Clear mask bit
Set mask bit

7 6 5 4 3 2 1 0

BIT NUMBER

0
1

Clear channel 0 mask bit
Set channel 0 mask bit

0
1

Clear channel 1 mask bit
Set channel 1 mask bit

0
1

Clear channel 2 mask bit
Set channel 2 mask bit

0
1

Clear channel 3 mask bit
Set channel 3 mask bit

Don't Care,

Write

All Ones,

Read

Status Register

7 6 5 4 3 2 1 0

BIT NUMBER

1 Channel 0 has reached TC

1 Channel 1 has reached TC

1 Channel 2 has reached TC

1 Channel 3 has reached TC

1 Channel 0 request

1 Channel 1 request

1 Channel 2 request

1 Channel 3 request

OPERATION

IOR

IOW

Read Status Register

Write Command Register

Read Request Register

Write Request Register

Read Command Register

Write Single Mask Bit

Read Mode Register

Write Mode Register

Set First/Last F/F

Clear First/Last F/F

Read Temporary Register

Master Clear

Clear Mode Reg. Counter

Clear Mask Register

Read All Mask Bits

Write All Mask Bits

FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES

158

82C237

Software Commands

There are special software commands which can be
executed by reading or writing to the 82C237. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:

Clear First/Last Flip-Flop - This command is executed prior
to writing or reading new address or word count information
to the 82C237. This command initializes the flip-flop to a
known state (low byte first) so that subsequent accesses to
register contents by the microprocessor will address upper
and lower bytes in the correct sequence.

Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.

Master Clear - This software instruction has the same effect
as the hardware RESET. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C237 will enter the idle cycle.

Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.

Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an inter-
nal two-bit counter has been included to select Mode regis-
ters during read operation. To read the Mode registers, first
execute the Clear Mode Register Counter command, then
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.

External EOP Operation

The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to V

is required. The value of the external pull-up

resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C237 will not accept
external EOP signals when it is in an SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C237 enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C237 is in an SI state.

16-Bit Transfer Mode

The 82C237 is fully software and pin for pin compatible with
the 82C37A. Therefore, the 82C237 may be used as a faster
82C37A without modifications to software or hardware. The
82C237 may be used as an 82C37A, however, the 82C237
has an additional feature in that it may be programmed to
perform 16-bit DMA transfers, thus doubling data transfer
rate. In 16-bit transfer mode the device operates the same
as in normal (8-bit) transfer mode with exceptions noted in
this section.

16-Bit Transfer Mode Initialization - To initialize the
82C237 to 16-bit Transfer Mode, a specific sequence of soft-
ware commands must be written to the device immediately
after a hardware RESET or a Master Clear instruction. The
sequence to initialize 16-bit Transfer Mode is as follows:

1) Hardware RESET or Master Clear
2) Set First/Last Flip-Flop
3) Clear First/Last Flip-Flop

These software commands must occur sequentially with no
communication to or from the 82C237 between commands.
Once in 16-bit mode, the device will remain in this mode until
a hardware RESET or Master Clear sets it back to normal (8-
bit) transfer mode. If this initialization sequence is not fol-
lowed exactly, the 82C237 will operate exactly like the
82C37A or the 82C237 in normal 8-bit mode.

16-Bit DMA Transfers - In 16-bit transfer mode, each DMA
channel may be programmed to perform 8-bit or 16-bit trans-
fers. Channels which are programmed to perform 8-bit trans-
fers will operate like a normal 82C37A transfer. On channels
programmed to perform 16-bit transfers, the Current
Address register, which is normally incremented or decre-
mented by one after each transfer, is incremented or decre-
mented by two after each transfer. Also, the Current Word
Count register, which is normally decremented by one after
each transfer, is decremented by two after each transfer.

16-Bit Memory-to-Memory Transfers - 16-bit memory-to-
memory transfers require an external latch to temporarily
store the 8 most significant bits of data. When 16-bit transfer
mode is enabled, Pin 5 (DWLE) becomes an active output
which may be used to enable the external data latch during
memory-to-memory operations. See Figure 9 for a 16-bit
DMA application. Channels 0 and 1 operate as memory-to-
memory transfer channels. IF either channel 0 or channel 1
is programmed to perform 16-bit transfers when a memory-
to-memory transfer is initiated, the transfer will be a 16-bit
transfer. If 8-bit memory-to-memory transfers are desired
while the 82C237 is in 16-bit transfer mode, channels 0 and
1 must both be programmed for 8-bit transfers.

Pin 5 DWLE Output - When the 82C237 is initialized to 16-
bit transfer mode, pin 5 is always high impedance three-
stated. This insures compatibility with the 82C37A pin 5
description. In 16-bit transfer mode, this output becomes
active and serves a dual purpose.

During the S1 cycle of a transfer, the DWLE output indicates
the data width (0 = 16-bit, 1 = 8-bit) of the active channel.
This signal may be used with the A0 output to generate a
High Byte Enable signal for use in chip select decode logic.
Since DWLE is a multiplexed pin, Data Width information
needs to be captured in an external latch on the falling edge
of ADSTB. See Figure 9 for a 16-bit DMA application.

During memory-to-memory transfer, the DWLE output is
used to enable an external latch which temporarily stores the
8 most significant bits of data during the read-from-memory
half of the transfer. DWLE enables this byte of data onto the
data bus during the write-to-memory half of the transfer. See
Figure 9 for a 16-bit DMA application.

159

If an active channel is cascaded, as defined by its mode reg-
ister, DWLE will be driven low at the start of the transfer, and
will remain low for the entire transfer. This allows the DWLE
signal from the slave 82C237 to control the system. To form
the system DWLE signal for cascaded 82C237s, simply
"OR" the individual DWLE outputs of the Master and Slaves.

Registers Affected by 16-Bit
Transfer Mode

Current Address Register - Each channel has a 16-bit Cur-
rent Address register. This register holds the value of the
address used during DMA transfers. On channels pro-
grammed to perform 8-bit DMA transfers, the address is
automatically incremented or decremented by one after
each transfer. On channels programmed for 16-bit DMA
transfers, the address is automatically incremented or decre-
mented by two after each transfer.

During all 16-bit transfers, the A0 output will remain low for
the entire transfer, even if an odd address is programmed
into the channel's Current Address register (i.e. only even
word addresses will be generated).

The Current Address register is written or read by the micro-
processor in successive 8-bit bytes. See Figure 6 for pro-
gramming information. It may also be reinitialized by an
Autoinitialize back to its original value. Autoinitialize takes
place only after an EOP. In memory-to-memory mode, the
channel 0 Current Address register can be prevented from
incrementing or decrementing by setting the address hold bit
in the Command register.

Current Word Count Register - Each channel has a 16-bit
Current Word Count register. This register determines the
number of transfers to be performed. On channels pro-
grammed for 8-bit transfers, the actual number of transfers
will be one more than the number programmed in the Cur-
rent Word Count register (i.e. programming a count of 100
will result in 101 transfers). The word count is decremented
by one after each transfer on 8-bit transfer channels.

On channels programmed for 16-bit transfers, the word
count is decremented by two after each transfer. This means
that for even values in the Current Word Count register, the
actual number of transfers will be n/2 + 1, where n is the
value in the Current Word Count register. For odd values in
this register, the actual number of transfers will be (n+1)/2.
When the value in the Current Word Count register decre-
ments past zero (i.e. 0 to FFFEH or 1 to FFFFH), a TC will
be generated.

This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC on 8-bit transfers, or
FFFEH after TC on 16-bit transfers.

Data-Width Register - When 16-bit transfer mode is enabled,
the Data-Width register becomes accessible and is used to
program each DMA channel to perform either 8-bit transfers

or 16-bit transfers. Data bits 4-7 represent DREQ channels 0-
3 respectively and determine the data width (8-bit or 16-bit) of
each channel during DMA transfers. When programming this
register, bit 3 of the data must be set to "0". Since the address
of the Data-Width register is the same as the Mask register,
bit 3 selects which register is actually written.

Data-Width Register - 16-bit transfer mode enabled

Mask Register - In 16-bit transfer mode this register oper-
ates the same as the previous Mask register description with
the exception of bit 3 when writing the instruction to sepa-
rately set or clear a mask bit. Bit 3 of the data must be "1"
when writing a single mask bit. Bits 4-7 are ignored when
this instruction is written. Refer to the following diagram for
writing single mask bits.

Mask Register - 16-bit transfer mode enabled

The software command to write all four bits of the Mask reg-
ister has no effect on the state of the Data-Width bits.

When reading the Mask/Data-Width register (they share the
same address), bits 0-3 will always display the mask bits of
channels 0-3, respectively. With 16-bit transfer mode not
enabled, bits 4-7 will always read as logical ones. With 16-bit
transfer mode enabled, bits 4-7 will display the data-width
bits for channels 0-3 respectively.

The Mask and Data-Width registers are set by RESET or
Master Clear. This disables all hardware DMA requests until
a clear mask bit instruction allows them to be recognized.
RESET or Master Clear forces the Mask and Data-Width

7 6 5 4 3 2 1 0

BIT NUMBER

X Don't Care

0 Must be 0 to write all

data - width bits

0
1

Channel 0 = 16-bit transfers
Channel 0 = 8-bit transfers

0
1

Channel 1 = 16-bit transfers
Channel 1 = 8-bit transfers

0
1

Channel 2 = 16-bit transfers
Channel 2 = 8-bit transfers

0
1

Channel 3 = 16-bit transfers
Channel 3 = 8-bit transfers

7 6 5 4 3 2 1 0

BIT NUMBER

00
01
10
11

Select channel 0 mask bit
Select channel 1 mask bit
Select channel 2 mask bit
Select channel 3 mask bit

0
1

Clear mask bit
Set mask bit

Must be 1 to write single
mask bit

Don't Care

82C237

160

registers to operate as in normal mode (Data-Width register
not accessible) until 16-bit transfer mode is again entered.
The four mask bits may also be cleared simultaneously by
using the Clear Mask Register command (see software com-
mands section). This command has no effect on the data-
width bits.

Temporary Register - The internal Temporary register is
used to hold data during memory-to-memory transfers. Fol-
lowing the completion of the transfers, the last byte moved
can be read by the microprocessor. In the case of 16-bit
transfers, only the least significant 8-bits of the last word
transferred are stored in this register. The Temporary regis-
ter always contains the last byte transferred in the previous
memory-to-memory operation, unless cleared by a RESET
or Master Clear.

Software Commands Affected by
16-Bit Mode

Master Clear - This software instruction has the same effect
as the hardware RESET. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. When the Master Clear instruction occurs while in 16-
bit transfer mode, the 82C237 enters normal (8-bit) transfer
mode in the Idle cycle.

Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
This command has no effect on data-width bits in 16-bit
transfer mode.

OPERATION

IOR

IOW

Read Status Register

Write Command Register

Read Request Register

Write Request Register

Read Command Register

Write Single Mask Bit (Note 1)

Write All Data-Width Bits (Notes 1, 2)

Read Mode Register

Write Mode Register

Set First/Last F/F

Clear First/Last F/F

Read Temporary Register

Master Clear

Clear Mode Reg. Counter

Clear Mask Register

Read All Mask/Data-Width Bits (Note 2)

Write All Mask Bits

NOTES:

1. The register to be written is determined by data bit 3.
2. Data-Width bits exist in 82C237, 16-bit mode only.

FIGURE 5. 16-BIT MODE SOFTWARE COMMAND CODES AND REGISTER CODES

82C237

161

82C237

CHANNEL

REGISTER

OPERATION

SIGNALS

FIRST/LAST

FLIP-FLOP

STATE

DATA

BUS

DB0-DB7

IOR

IOW

Base and Current Address

Write

A0-A7

A8-A15

Current Address

Read

A0-A7

A8-A15

Base and Current Word
Count

Write

W0-W7

W8-W15

Current Word Count

Read

W0-W7

W8-W15

Base and Current Address

Write

A0-A7

A8-A15

Current Address

Read

A0-A7

A8-A15

Base and Current Word
Count

Write

W0-W7

W8-W15

Current Word Count

Read

W0-W7

W8-W15

Base and Current Address

Write

A0-A7

A8-A15

Current Address

Read

A0-A7

A8-A15

Base and Current Word
Count

Write

W0-W7

W8-W15

Current Word Count

Read

W0-W7

W8-W15

Base and Current Address

Write

A0-A7

A8-A15

Current Address

Read

A0-A7

A8-A15

Base and Current Word
Count

Write

W0-W7

W8-W15

Current Word Count

Read

W0-W7

W8-W15

FIGURE 6. WORD COUNT AND ADDRESS REGISTER COMMAND CODES

162

82C237

Application Information

Figure 7 shows an application for a DMA system utilizing the
82C237 DMA controller and the 80C88 Microprocessor. In
this application, the 82C237 DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.

Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C237 DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most signifi-
cant bits of the address are output on the address/data bus.
Therefore, the 82C82 octal latch is used to demultiplex the

address. Hold Acknowledge (HLDA) and Address Enable
(AEN) are "ORed" together to insure that the DMA controller
does not have bus contention with the microprocessor.

Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge signal is returned to the DMA controller from the 80C88
processor. After the Hold Acknowledge has been received,
addresses and control signals are generated by the DMA
controller to accomplish the DMA transfers. Data is trans-
ferred directly from the I/O device to memory (or vice versa)
with IOR and MEMW (or MEMR and IOW) being active.
Note that data is not read into or driven out of the DMA con-
troller in I/O-to-memory or memory-to-I/O data transfers.

FIGURE 7. APPLICATION FOR DMA SYSTEM

MEMR

MEMW

IOR

IOW

MEMCS

MEMR

MEMW

MEMORY

47K

ADDRESS BUS

DATA BUS

80C88

M/IO

HRQ

HLDA

ALE
AD0

AD7

MN/MX

CLK

82C84A

82C85

HLDA

MEMCS

STB

82C82

DECODER

ADDRESS BUS

STB

82C82

A0-7

CLK

EOP

HLDA

IOR

DACK

ADSTB

AEN

DB0-7

IOW

MEMR

MEMW

HRQ

DREQ0

82C237

IOR
IOW

DREQ

I/O

DEVICE

NOTE: The address lines need pull-up resistors.

163

82C237

Figure 8 shows an application for a DMA system using the
82C237 DMA controller and the 80C286 Microprocessor.

In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write con-
trol signals from the 82C288 Bus Controller. The octal latch

for A8-A15 from the DMA controller's data bus is on the local
80C286 address bus so that memory chip selects may still
be generated during DMA transfers. The transceiver on A0-
A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow pro-
gramming on the upper or lower half of the data bus.

FIGURE 8. 80C286 DMA APPLICATION

MEMW

MEMR

MEMCS

MEMORY

A0 - A23

IOW

DACK

I/O

IOR

SYSTEM

BUS

TRANSCEIVER

T/R

DEVICE

DREQ

D0 - D15

TRANS-

CEIVER

TRANS-

CEIVER

LATCH

STB
OE

AEN

D0-D7

A0-A7

IOR

IOW

MEMR

MEMW

DACK 0-3

D0-D7

DREQ 0-3

EOP

AEN

ADSTB
HRQ
HLDA
CLK

READY

82C237

IOR
IOW
MEMR
MEMW

TO CORRESPONDING

82C288 SIGNALS AND

MEMORY/PERIPHERALS

TRANSCEIVER

LATCH

DECODE

CHIP SELECT

TO MEMORY/

PERIPHERALS

80C286

A0-A23

D0-D15

READY

HLD

HLDA

CLK

IORC

IOWC

MRDC

MWTC

IOR
IOW
MEMR
MEMW

CLK

82C288

82C284

CLK

PCLK

READY

165

82C237

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V

+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range

C82C237. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

C to +70

I82C237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

M82C237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

Thermal Resistance (Typical)

(

C/W)

(

C/W)

CERDIP Package . . . . . . . . . . . . . . . .

CLCC Package . . . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

N/A

PLCC Package . . . . . . . . . . . . . . . . . .

N/A

Storage Temperature Range . . . . . . . . . . . . . . . . .-65

C to +150

Maximum Junction Temperature Ceramic Package . . . . . . . +175

Maximum Junction Temperature Plastic Package . . . . . . . . +150

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300

Ceramic Package

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +260

Plastic Package

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications

= +5.0 ±

10%, T

= 0

C to +70

C (C82C237)

= -40

C to +85

C (I82C237)

= -55

C to +125

C (M82C237)

SYMBOL

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

VIH

Logical One Input Voltage

C82C237, I82C237

2.2

M82C237

VIL

Logical Zero Input Voltage

0.8

VIHC

CLK Input Logical One Voltage

-0.8

VILC

CLK Input Logical Zero Voltage

0.8

VOH

Output HIGH Voltage

3.0

IOH = -2.5mA

-0.4

IOH = -100

VOL

Output LOW Voltage

0.4

IOL = +2.5mA all output except EOP,
IOL = +3.2mA for EOP pin 36 only.

Input Leakage Current

-1

VIN = GND or V

, Pins 6, 7, 11-13, 16-19

Output Leakage Current

-10

+10

VOUT = GND or V

, Pins 1-5, 21-23, 26-30,

32-40

ICCSB

Standby Power Supply
Current

= 5.5V, VIN = V

or GND, Outputs

Open

ICCOP

Operating Power Supply
Current

mA/MHz

= 5.5V, CLK FREQ = Maximum,

VIN = V

or GND, Outputs Open

Capacitance

= +25

SYMBOL

PARAMETER

TYP

UNITS

TEST CONDITIONS

CIN

Input Capacitance

FREQ = 1MHz, All measurements are
referenced to device GND

COUT

Output Capacitance

CI/O

I/O Capacitance

166

82C237

AC Electrical Specifications

= +5.0V

10%, GND = 0V,

= 0

C to +70

C (C82C237),

= -40

C to +85

C (I82C237),

= -55

C to +125

C (M82C237)

SYMBOL

PARAMETER

82C237

82C237-12

UNITS

MIN

MAX

MIN

MAX

DMA (MASTER) MODE

(1)TAEL

AEN HIGH from CLK LOW (S1) Delay Time

105

(2)TAET

AEN LOW from CLK HIGH (SI) Delay Time

(3)TAFAB

ADR Active to Float Delay from CLK HIGH

(4)TAFC

READ or WRITE Float Delay from CLK HIGH

(5)TAFDB

DB Active to Float Delay from CLK HIGH

135

(6)TAHR

ADR from READ HIGH Hold Time

TCY-75

TCY-65

(7)TAHS

DB from ADSTB LOW Hold Time

TCL-18

(8)TAHW

ADR from WRITE HIGH Hold Time

TCY-65

TCY-50

(9)TAK

DACK Valid from CLK LOW Delay Time

105

EOP HIGH from CLK HIGH Delay Time

105

EOP LOW from CLK HIGH Delay Time

(10)TASM

ADR Stable from CLK HIGH

(11)TASS

DB to ADSTB LOW Setup Time

TCH-20

(12)TCH

CLK HIGH Time (Transitions 10ns)

(13)TCL

CLK LOW Time (Transitions 10ns)

(14)TCY

CLK Cycle Time

125

(15)TDCL

CLK HIGH to READ or WRITE LOW Delay

130

120

(16)TDCTR

READ HIGH from CLK HIGH (S4) Delay Time

115

(17)TDCTW

WRITE HIGH from CLK HIGH (S4) Delay Time

(18)TDQ

HRQ Valid from CLK HIGH Delay Time

(19)TEPH

EOP Hold Time from CLK LOW (S2)

(20)TEPS

EOP LOW to CLK LOW Setup Time

(21)TEPW

EOP Pulse Width

135

(22)TFAAB

ADR Valid Delay from CLK HIGH

(23)TFAC

READ or WRITE Active from CLK HIGH

(24)TFADB

DB Valid Delay from CLK HIGH

(25)THS

HLDA Valid to CLK HIGH Setup Time

(26)TIDH

Input Data from MEMR HIGH Hold Time

(27)TIDS

Input Data to MEMR HIGH Setup Time

(28)TODH

Output Data from MEMW HIGH Hold Time

TCY-50

(29)TODV

Output Data Valid to MEMW HIGH

TCY-35

TCY-10

(30)TQS

DREQ to CLK LOW (SI, S4) Setup Time

(31)TRH

CLK to READY LOW Hold Time

(32)TRS

READY to CLK LOW Setup Time

(33)TCLSH

ADSTB HIGH from CLK LOW Delay Time

(34)TCLSL

ADSTB LOW from CLK LOW Delay Time

120

167

82C237

(35)TWRRD

READ HIGH Delay from WRITE HIGH

(36)TRLRH

READ Pulse Width, Normal Timing

2TCY-60

2TCY-55

(37)TSHSL

ADSTB Pulse Width

TCY-50

TCY-35

(38)TWLWHA

Extended WRITE Pulse Width

2TCY-85

2TCY-80

(39)TWLWH

WRITE Pulse Width

TCY-85

TCY-80

(40)TRLRHC

READ Pulse Width, Compressed

TCY-60

TCY-55

(56)TAVRL

ADR Valid to READ LOW

(57)TAVWL

ADR Valid to WRITE LOW

(58)TRHAL

READ HIGH to AEN LOW

(59)TRHSH

READ HIGH to ADSTB HIGH

(60)TWHSH

WRITE HIGH to ADSTB HIGH

(61)TDVRL

DACK Valid to READ LOW

(62)TDVWL

DACK Valid to WRITE LOW

(63)TRHDI

READ HIGH to DACK Inactive

(64)TAZRL

ADR Float to READ LOW

-2.5

(65)TOEV

Output Enable Valid Before WRITE HIGH

TCY+20

(66)TOEH

Output Enable Hold Time from WRITE HIGH

TCY-50

PERIPHERAL (SLAVE) MODE

(41)TAR

ADR Valid or CS LOW to READ LOW

(42)TAWL

ADR Valid to WRITE LOW Setup Time

(43)TCWL

CS LOW to WRITE LOW Setup Time

(44)TDW

Data Valid to WRITE HIGH Setup Time

100

(45)TRA

ADR or CS Hold from READ HIGH

(46)TRDE

Data Access from READ

120

(47)TRDF

DB Float Delay from READ HIGH

(48)TRSTD

Power Supply HIGH to RESET LOW Setup Time

500

(49)TRSTS

RESET to First IOR or IOW

2TCY

(50)TRSTW

RESET Pulse Width

300

(51)TRW

READ Pulse Width

155

(52)TWA

ADR from WRITE HIGH Hold Time

(53)TWC

CS HIGH from WRITE HIGH Hold Time

(54)TWD

Data from WRITE HIGH Hold Time

(55)TWWS

WRITE Pulse Width

100

AC Electrical Specifications

= +5.0V

10%, GND = 0V,

= 0

C to +70

C (C82C237),

= -40

C to +85

C (I82C237),

= -55

C to +125

C (M82C237) (Continued)

SYMBOL

PARAMETER

82C237

82C237-12

UNITS

MIN

MAX

MIN

MAX

169

82C237

FIGURE 12. DMA TRANSFER

NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for an 8-bit trans-
fer with the 82C237 programmed in 16-bit mode. For a 16-bit transfer, DWLE will go low at least TASS before the falling edge of ADSTB in
S2, and remain low for the entire transfer.

Timing Waveforms

(Continued)

TEPW (21)

TAK (9)

TQS

(30)

TDQ

(18)

THS

(25)

TAEL

(1)

TCLSH

(33)

TQS

(30)

TCL (13)

TCY

(14)

TCH

(12)

TDQ

(18)

TAET

(2)

TSHSL

(37)

TCLSL

(34)

TEPS

(20)

TEPH

(19)

TRHAL

(58)

TAK (9)

TAFAB (3)

TAHW (8)

TAHR (6)

TRHDI (63)

TAFC (4)

TDCTR (16)

TDCL

(15)

CLK

DREQ

HRQ

HLDA

AEN

ADSTB

DB0-DB7

A0-A7

DACK

READ

WRITE

INT EOP

EXT EOP

(64)

TAZRL

TAFDB

(5)

TFAAB

(22)

TFADB

(24)

TASS

(11)

TAHS

(7)

A8-A15

TAK

(9)

TDCL

(15)

TFAC

(23)

TDCL (15)

TDVWL

(62)

TWLWHA

(38)

TDCTW

(17)

TAVWL

(57)

TDVAL (61)

(FOR EXTENDED WRITE)

TAK (9)

TDCL

(15)

TWLWH (39)

TDCTW (17)

TWRRD

(35)

TAVRL

(56)

TRLRH

(36)

TDCTR

(16)

TAHR

(6)

TAHW

(8)

TASM

(10)

ADDRESS VALID

TAHS

(7)

TASS

(11)

DWLE

(SEE NOTE)

170

82C237

FIGURE 13. MEMORY-TO-MEMORY TRANSFER

NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for a 16-bit memory-to-memory

transfer. For an 8-bit transfer in 16-bit mode, DWLE will go high at least TASS before the falling edge of ADSTB in S2, then low TAHS after the falling
edge of ADSTB, and will remain low until the next ADSTB where the cycle is repeated.

FIGURE 14. READY

NOTE: READY must not transition during the specified setup and hold times.

Timing Waveforms

(Continued)

(33)

TCLSH

CLK

S11

S12

S13

S14

S21

S22

S23

S24

S11/SI

ADSTB

A0-A7

DB0-DB7

MEMR

MEMW

EOP

EXT EOP

(34)

TCLSL

(7)

TAHS

TFAAB (22)

TASS (11)

TFADB (24)

(5) TAFDB

A8-A15

(16) TDCTR

TFAC (23)

ADDRESS VALID

(33)

TCLSH

(34)

TCLSL

TWHSH

(60)

TCLSH

(33)

TAFAB

(3)

TAFAC

(4)

TAFAC

(4)

(59) TRHSH

TAHS

(7)

A8-A15

(24)

TFADB

TIDH (26)

TIDS

(27)

TAFDB

(5)

TDCL

(15)

TDCL

(15)

TDCTW (17)

TAK(9)

TAK

(9)

OUT

TEPW

(21)

TEPS (20)

(19) TEPH

EXTENDED WRITE

TOVD

(29)

TODH (28)

TAZRL

(64)

TDCL

(15)

TASS

(11)

DWLE

TASS (11)

TAHS

(7)

TAHS

(7)

TASS (11)

TOEV (65)

(SEE NOTE)

CLK

EXTENDED WRITE

(16)

TDCTR

(15)

TDCL

(15)

TDCL

(15)TDCL

(31)TRH

(32)TRS

TRH

(32) TRS

(17)

TDCTW

READ

WRITE

READY

(31)

172

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Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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Die Characteristics

DIE DIMENSIONS:

148 x 159 x 19

1mils

METALLIZATION:

Type: 51Al
Thickness: 8k

0.75k

GLASSIVATION:

Type: Nitrox
Thickness: 10k

WORST CASE CURRENT DENSITY:

0.6 x 10

A/cm

Metallization Mask Layout

82C237

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 82C237-10

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 82C237-10