1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
ACS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
OE
Q0
D0
D1
Q1
Q2
D2
D3
9
10
12
11
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
April 1995
Spec Number
518799
File Number
3999
Truth Table
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
I
L
L
L
h
H
H
X
X
Z
NOTE:
L = Low Voltage Level
H = High Voltage Level
X = Don't Care
Z = High Impedance State
I
= Low voltage level one set-up time prior to the high to low latch enable transition
h = High voltage level one set-up time prior to the high to low latch enable transition
Functional Diagram
D
Q
LE
D
LE
Q
OE
LATCH
COMMON
OE
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
(2, 5, 6, 9, 12,
15, 16, 19)
(1)
(11)
CONTROLS
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
ACS373DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead SBDIP
ACS373KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
ACS373D/Sample
+25
o
C
Sample
20 Lead SBDIP
ACS373K/Sample
+25
o
C
Sample
20 Lead Ceramic Flatpack
ACS373HMSR
+25
o
C
Die
Die
Features
1.25 Micron Radiation Hardened SOS CMOS
Total Dose 300K RAD (Si)
Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
SEU LET Threshold >80 MEV-cm
2
/mg
Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current
1
A at VOL, VOH
Description
The Intersil ACS373MS is a radiation hardened octal transparent
latch with three-state outputs. The outputs are transparent to the
inputs when the latch enable (LE) is high. When the LE goes low,
the data is latched. When the Output Enable (OE) is high, the
outputs are in the high impedance state. The latch operation is
independent of the state of the output enable.
The ACS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
2
Specifications ACS373MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
DC Drain Current, Any One Output
. . . . . . . . . . . . . . . . . . . . . . .
50mA
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
(All Voltages Reference to VSS)
Thermal Impedance
JA
JC
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
o
C/W
24
o
C/W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . .
107
o
C/W
28
o
C/W
Maximum Package Power Dissipation at +125
o
C
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5W
Maximum Device Power Dissipation . . . . . . . . . . . . . . . . . . .(TBD)W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Gates
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . 10ns/V Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . VCC to 70% of VCC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
+25
o
C
-
20
A
2, 3
+125
o
C, -55
o
C
-
400
A
Output Current
(Source)
IOH
VCC = VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V, (Note 2)
1
+25
o
C
-12
-
mA
2, 3
+125
o
C, -55
o
C
-8
-
mA
Output Current
(Sink)
IOL
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0V,
(Note 2)
1
+25
o
C
12
-
mA
2, 3
+125
o
C, -55
o
C
8
-
mA
Output Voltage High
VOH
VCC = 5.5V, VIH = 3.85V
VIL = 1.65V, IOH = -50
A
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC -0.1
-
V
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOH = -50
A
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC -0.1
-
V
Output Voltage Low
VOL
VCC = 5.5V, VIH = 3.85V
VIL = 1.65V, IOH = 50
A
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOH = 50
A
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
Input Leakage
Current
IIN
VCC = 5.5V,
VIN = VCC or GND
1
+25
o
C
-
0.5
A
2, 3
+125
o
C, -55
o
C
-
1.0
A
Three-State Output
Leakage Current
IOZ
VCC = 5.5V,
Force Voltage = 0V or VCC
1
+25
o
C
-
1
A
2, 3
+125
o
C, -55
o
C
-
35
A
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 3)
7, 8A, 8B
+25
o
C, +125
o
C, -55
o
C
-
-
V
NOTE:
1. All voltages referenced to device GND.
2. Force/measure functions may be interchanged.
3. For functional tests, VO
4.0V is recognized as a logic "1", and VO
0.5V is recognized as a logic "0".
Spec Number
518799
3
Specifications ACS373MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
TPHL1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
14
ns
10, 11
+125
o
C, -55
o
C
2
15
ns
TPLH1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
15
ns
10, 11
+125
o
C, -55
o
C
2
18
ns
TPHL2
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
13
ns
10, 11
+125
o
C, -55
o
C
2
14
ns
TPLH2
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
14
ns
10, 11
+125
o
C, -55
o
C
2
16
ns
TPZL1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
14
ns
10, 11
+125
o
C, -55
o
C
2
15
ns
TPLZ1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
14
ns
10, 11
+125
o
C, -55
o
C
2
14
ns
TPHZ1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
15
ns
10, 11
+125
o
C, -55
o
C
2
16
ns
TPZH1
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25
o
C
2
15
ns
10, 11
+125
o
C, -55
o
C
2
16
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500
, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMP
LIMITS
UNITS
MIN
TYP
MAX
Capacitance Power
Dissipation
CPD
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25
o
C
-
25
-
pF
+125
o
C
-
30
-
pF
Input Capacitance
CIN
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25
o
C
-
-
10
pF
+125
o
C
-
-
10
pF
Output Capacitance
COUT
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25
o
C
-
-
20
pF
+125
o
C
-
-
20
pF
Pulse Width Time
TW
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
1
+25
o
C
7
-
-
ns
+125
o
C
7
-
-
ns
Setup Time
TSU
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
1
+25
o
C
5
-
-
ns
+125
o
C
5
-
-
ns
Hold Time
TH
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
1
+25
o
C
3
-
-
ns
+125
o
C
3
-
-
ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
518799
4
Specifications ACS373MS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
TEMP
RAD LIMITS
UNITS
MIN
MAX
Supply Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25
o
C
-
400
A
Output Current (Source)
IOH
VCC = VIH = 4.5V,
VOUT = VCC -0.4V, VIL = 0
+25
o
C
-8
-
mA
Output Current (Sink)
IOL
VCC = VIH = 4.5V, VOUT = 0.4V,
VIL = 0
+25
o
C
8
-
mA
Output Voltage High
VOH
VCC = 5.5V, VIH = 3.85V,
VIL = 1.65V, IOH = -50
A
+25
o
C
VCC -0.1
-
V
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOH = -50
A
+25
o
C
VCC -0.1
-
V
Output Voltage Low
VOL
VCC = 5.5V, VIH = 3.85V,
VIL = 1.65V, IOH = 50
A
+25
o
C
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOH = 50
A
+25
o
C
-
0.1
V
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25
o
C
-
1
A
Three-State Output
Leakage Current
IOZ
VCC = 5.5V,
Force Voltage = 0V or VCC
+25
o
C
-
35
A
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 2)
+25
o
C
-
-
V
Propagation Delay
TPHL1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
15
ns
TPLH1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
18
ns
TPHL2
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
14
ns
TPLH2
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
16
ns
TPZL1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
15
ns
TPLZ1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
14
ns
TPHZ1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
16
ns
TPZH1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25
o
C
2
16
ns
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO
4.0V is recognized as a logic "1", and VO
0.5V is recognized as a logic "0".
TABLE 5. DELTA PARAMETERS (+25
o
C)
PARAMETER
SYMBOL
(NOTE 1)
DELTA LIMIT
UNITS
Supply Current
ICC
4.0
A
Three-State Leakage Current
IOZ
200
nA
Output Current
IOL/IOH
15
%
NOTE:
1. All delta calculations are referenced to 0 hour readings or pre-life readings.
Spec Number
518799
5
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
Interim Test 1 (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
Interim Test 2 (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test 3 (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZL/H
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample/5005
1, 7, 9
Group D
Sample/5005
1, 7, 9
NOTE:
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUP
METHOD
TEST
READ AND RECORD
PRE RAD
POST RAD
PRE RAD
POST RAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. BURN-IN TEST CONNECTIONS (+125
o
C < TA < 139
o
C)
OPEN
GROUND
1/2 VCC = 3V
0.5V
VCC = 6V
0.5V
OSCILLATOR
50kHz
25kHz
STATIC BURN-IN 1 (Note 1)
-
1, 3, 4, 7, 8, 10, 11,
13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
20
-
-
STATIC BURN-IN 2 (Note 1)
-
10
2, 5, 6, 9, 12, 15, 16, 19
1, 3, 4, 7, 8, 11, 13,
14, 17, 18, 20
-
-
DYNAMIC BURN-IN (Note 1)
-
1, 10
2, 5, 6, 9, 12, 15, 16, 19
20
11
3, 4, 7, 8, 13,
14, 17, 18
NOTE:
1. Each pin except VCC and GND will have a series resistor of 500
5% for static burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25
o
C,
5
o
C)
FUNCTION
OPEN
GROUND
VCC = 5V
0.5V
Irradiation Circuit (Note 1)
2, 5, 6, 9, 12, 15, 16, 19
10
1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
NOTE:
1. Each pin except VCC and GND will have a series resistor of 47k
5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
Specifications ACS373MS
Spec Number
518799
6
Specifications ACS373MS
Spec Number
518799
Propagation Delay Timing Diagram and Load Circuit
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65
o
to +150
o
C)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125
o
C Min
100% Interim Electrical Test 1 (Note 1)
100% Static Burn-In 2 Method 1015, 24 Hours at +125
o
C Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125
o
C
or 180 Hours at +135
o
C
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
VS
INPUT
OUTPUT
VIH
VSS
VOH
VOL
TPLH
TPHL
VS
AC VOLTAGE LEVELS
PARAMETER
ACS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
DUT
TEST
CL
RL
POINT
50pF
500
7
Specifications ACS373MS
Spec Number
518799
Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit
Three-State High Timing Diagram and Load Circuit
Three-State Low Timing Diagram and Load Circuit
INPUT
VIL
VIL
VS
VIH
INPUT CP
VIH
TH = HOLD TIME
TSU = SETUP TIME
TW = PULSE WIDTH
TW
TSU
TH
TW
VS
DUT
TEST
CL
RL
POINT
50pF
500
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
ACS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
TPHZ
INPUT
VS
TPZH
VT
VIH
VSS
VOH
VOZ
OUTPUT
VW
DUT
TEST
CL
RL
POINT
50pF
500
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
ACS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VT
2.25
V
VW
3.60
V
GND
0
V
TPLZ
INPUT
VS
TPZL
VT
VIH
VSS
VOZ
VOL
OUTPUT
VW
CL
RL
DUT
TEST
POINT
VCC
500
50pF
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
ACS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VT
2.25
V
VW
0.90
V
GND
0
V
8
ACS373MS
Spec Number
518799
Metallization Mask Layout
ACS373MS
D1 (4)
Q1 (5)
Q2 (6)
D2 (7)
(8)
D3
(9)
Q3
(10)
GND
(11)
CP
(12)
Q4
(13)
D4
(18)
(17) D6
(16) Q6
(15) Q5
(14) D5
Q0
(2)
D0
(3)
OE
(1)
VCC
(20)
Q7
(19)
D7
NC
NC
NC
NC
Die Characteristics
DIE DIMENSIONS:
102 mils x 102 mils
2,600mm x 2,600mm
METALLIZATION:
Type: AlSiCu
Metal 1 Thickness: 6.75k
(Min), 8.25k
(Max)
Metal 2 Thickness: 9k
(Min), 11k
(Max)
GLASSIVATION:
Type: SiO
2
Thickness: 8k
1k
DIE ATTACH:
Material: Silver Glass or JM 7000 after 7/1/95
WORST CASE CURRENT DENSITY:
< 2.0 x 10
5
A/cm
2
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110
m x 110
m
9
ACS373MS
Spec Number
518799
D20.3
MIL-STD-1835 CDIP2-T20 (D-8, CONFIGURATION C)
20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.060
-
26.92
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.070
0.38
1.78
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
90
o
105
o
90
o
105
o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
N
20
20
8
Rev. 0 4/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb
C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
S
S
-D-
-A-
-C-
e
A
-B-
aaa
C A - B
M
D
S
S
ccc
C A - B
M
D
S
S
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
e
A/2
S2
M
A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
10
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
ACS373MS
Spec Number
518799
-D-
-C-
0.004
H A - B
M
D
S
S
-A-
-B-
0.036
H A - B
M
D
S
S
e
E
A
Q
L
D
A
E1
SEATING AND
L
E2
E3
E3
BASE PLANE
-H-
b
C
S1
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
PIN NO. 1
ID AREA
A
M
K20.A
MIL-STD-1835 CDFP4-F20 (F-9A, CONFIGURATION B)
20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.540
-
13.72
3
E
0.245
0.300
6.22
7.62
-
E1
-
0.330
-
8.38
3
E2
0.130
-
3.30
-
-
E3
0.030
-
0.76
-
7
e
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.00
-
0.00
-
6
M
-
0.0015
-
0.04
-
N
20
20
-
Rev. 0 5/18/94
Ceramic Metal Seal Flatpack Packages (Flatpack)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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