1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671601VEC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
16 Lead SBDIP
5962F9671601VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
16 Lead Ceramic Flatpack
ACTS161D/Sample
25
o
C
Sample
16 Lead SBDIP
ACTS161K/Sample
25
o
C
Sample
16 Lead Ceramic Flatpack
ACTS161HMSR
25
o
C
Die
Die
ACTS161MS
Radiation Hardened
4-Bit Synchronous Counter
January 1996
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP
P0
P1
P2
P3
GND
PE
VCC
Q0
Q1
Q2
Q3
TE
SPE
TC
MR
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
MR
CP
P0
P1
P2
P3
PE
GND
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96716 and Intersil's QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
1
A at VOL, VOH
Fast Propagation Delay . . . . . . . . . . . . . . . . 25ns (Max), 16ns (Typ)
Description
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter, featuring asynchronous reset and load ahead carry logic. The MR is
an active low master reset. SPE is an active low Synchronous Parallel Enable
which disables counting and allows data at the preset inputs (P0 - P3) to load
the counter. CP is the positive edge clock. TC is the terminal count or carry
output. Both TE and PE must be high for counting to occur, but are irrelevant
to loading. TE low will keep TC low.
The ACTS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Spec Number
518893
File Number
4095
2
ACTS161MS
Functional Diagram
TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
MR
CP
PE
TE
SPE
P
N
Q
N
TC
Reset (Clear)
L
X
X
X
X
X
L
L
Parallel Load
H
X
X
I
I
L
L
H
X
X
I
h
H
(Note 1)
Count
H
h
h
h (Note 3)
X
count
(Note 1)
Inhibit
H
X
I (Note 2)
X
h (Note 3)
X
q
N
(Note 1)
H
X
X
I (Note 2)
h (Note 3)
X
q
N
L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-
age level one setup time prior to the Low-to-High clock transition, X = Don't Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
= Low-to-High Transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while CP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
CP
MR
T3
P
D3
12
Q2
11
Q3
15
TC
Q3
TE
CP
MR
T2
P
D2
13
Q1
Q2
CP
MR
T1
P
D1
1
MR
Q1
CP
MR
T0
P
D0 Q0
14
Q0
GND
9
SPE
2
CP
10
TE
7
PE
TE
Q3
Q2
Q1
Q0
P3
6
P2
5
P1
4
P0
3
Spec Number
518893
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
ACTS161MS
Spec Number
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