1
CA3054
Dual Independent Differential Amp for
Low Power Applications from DC to
120MHz
The CA3054 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six NPN transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of f
T
in excess of 300MHz.
These feature make the CA3054 useful from DC to 120MHz.
Bias and load resistors have been omitted to provide
maximum application flexibility.
The monolithic construction of the CA3054 provides close
electrical and thermal matching of the amplifiers. This
feature makes these devices particularly useful in dual
channel applications where matched performance of the two
channels is required.
Pinout
CA3054
(PDIP, SOIC)
TOP VIEW
Features
Two Differential Amplifiers on a Common Substrate
Independently Accessible Inputs and Outputs
Maximum Input Offset Voltage . . . . . . . . . . . . . . . . .
5mV
Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 85
o
C
Applications
Dual Sense Amplifiers
Dual Schmitt Triggers
Multifunction Combinations
- RF/Mixer/Oscillator; Converter/IF
IF Amplifiers (Differential and/or Cascode)
Product Detectors
Doubly Balanced Modulators and Demodulators
Balanced Quadrature Detectors
Cascade Limiters
Synchronous Detectors
Pairs of Balanced Mixers
Synthesizer Mixers
Balanced (Push-Pull) Cascode Amplifiers
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CA3054
0 to 85
14 Ld PDIP
E14.3
CA3054M96
(3054)
0 to 85
14 Ld SOIC Tape
and Reel
M14.15
SUBSTRATE
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Q
4
Q
6
Q
5
Q
3
Q
2
Q
1
Data Sheet
September 1998
File Number
388.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
Intersil Corporation 1999
2
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
Collector-to-Emitter Voltage, V
CEO
. . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, V
CBO
. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, V
CIO
(Note 1) . . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, V
EBO
. . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, I
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 85
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . .175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The
substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Maximum Voltage Ratings
Maximum
Current Ratings
The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the termi-
nals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V.
(NOTE 4)
TERM
NO.
13
14
1
2
3
4
6
7
8
9
11
12
5
(NOTE 4)
TERM
NO.
I
IN
mA
I
OUT
mA
13
0, -20
Note 3
+5, -5
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
13
5
0.1
14
Note 3 Note 3 Note 3
+20, 0
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
+20, 0
14
50
0.1
1
+20, 0
Note 3
+20, 0
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
+20, 0
1
50
0.1
2
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
2
5
0.1
3
+1, -5
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
3
5
0.1
4
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
4
0.1
50
6
0, -20
Note 3
+5, -5
Note 3
+15, -5
Note 3
6
5
0.1
7
Note 3 Note 3 Note 3
Note 3
+20, 0
7
50
0.1
8
+20, 0
Note 3
Note 3
+20, 0
8
50
0.1
9
Note 3
+15, -5
Note 3
9
5
0.1
11
-1, -5
Note 3
11
5
0.1
12
Note 3
12
0.1
50
5
Ref.
Sub-
strate
NOTES:
3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe
if the specified limits between all other terminals are not exceeded.
4. Terminal No. 10 of CA3054 is not used.
Electrical Specifications
T
A
= 25
o
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
For Each Differential Amplifier
Input Offset Voltage (Figure 8)
V
IO
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
0.45
5
mV
Input Offset Current (Figure 9)
I
IO
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
0.3
2
A
Input Bias Current (Figure 5)
I
I
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
10
24
A
Quiescent Operating Current Ratio
(Figure 5)
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
0.98 to
1.02
-
-
Temperature Coefficient Magnitude of
Input Offset Voltage (Figure 7)
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
1.1
-
V/
o
C
I
C(Q1)
I
C(Q2)
------------------
I
C(Q5)
I
C(Q6)
------------------
or
V
IO
T
-----------------
CA3054
3
FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 8)
V
BE
V
CB
= 3V
I
C
= 50
A
-
0.630
0.700
V
I
C
= 1mA
-
0.715
0.800
V
I
C
= 3mA
-
0.750
0.850
V
I
C
= 10mA
-
0.800
0.900
V
Temperature Coefficient of Base-to-Emitter
Voltage (Figure 6)
V
CB
= 3V, I
C
= 1mA
-
-1.9
-
V/
o
C
Collector Cutoff Current (Figure 4)
I
CBO
V
CB
= 10V, I
E
= 0
-
0.002
100
nA
Collector-to-Emitter Breakdown Voltage
V
(BR)CEO
I
C
= 1mA, I
B
= 0
15
24
-
V
Collector-to-Base Breakdown Voltage
V
(BR)CBO
I
C
= 10
A, I
E
= 0
20
60
-
V
Collector-to-Substrate Breakdown
Voltage
V
(BR)CIO
I
C
= 10
A, I
CI
= 0
20
60
-
V
Emitter-to-Base Breakdown Voltage
V
(BR)EBO
I
E
= 10
A, I
C
= 0
5
7
-
V
DYNAMIC CHARACTERISTICS
Common Mode Rejection Ratio for each
Amplifier (Figures 1, 10)
CMRR
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
100
-
dB
AGC Range, One Stage (Figures 2, 11)
AGC
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
75
-
dB
Voltage Gain, Single Stage Double-Ended
Output (Figures 2, 11)
A
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
32
-
dB
AGC Range, Two Stage (Figures 3, 12)
AGC
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
105
-
dB
Voltage Gain, Two Stage Double-Ended Output
(Figures 3, 12)
A
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
60
-
dB
Low Frequency, Small Signal Equivalent Circuit Char-
acteristics (For Single Transistor)
Forward Current Transfer Ratio (Figure 13)
h
FE
f = 1kHz, V
CE
= 3V, I
C
= 1mA
-
110
-
-
Short Circuit Input Impedance (Figure 13)
h
IE
f = 1kHz, V
CE
= 3V, I
C
= 1mA
-
3.5
-
k
Open Circuit Output Impedance
(Figure 13)
h
OE
f = 1kHz, V
CE
= 3V, I
C
= 1mA
-
15.6
-
S
Open Circuit Reverse Voltage Transfer
Ratio (Figure 13)
h
RE
f = 1kHz, V
CE
= 3V, I
C
= 1mA
-
1.8 x
10
-4
-
-
1/f Noise Figure for Single Transistor
NF
f = 1kHz, V
CE
= 3V
-
3.25
-
dB
Gain Bandwidth Product for Single
Transistor (Figure 14)
f
T
V
CE
= 3V, I
C
= 3mA
-
550
-
MHz
Admittance Characteristics; Differential
Circuit Configuration (For Each Amplifier)
Forward Transfer Admittance (Figure 15)
Y
21
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
-
-20 + j0
-
mS
Input Admittance (Figure 16)
Y
11
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
-
0.22 +
j0.1
-
mS
Output Admittance (Figure 17)
Y
22
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
-
0.01 +
j0
-
mS
Reverse Transfer Admittance (Figure 18)
Y
12
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
-
-0.003
+ j0
-
mS
Electrical Specifications
T
A
= 25
o
C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
BE
T
----------------
CA3054
4
Admittance Characteristics; Cascode Circuit
Configuration (For Each Amplifier)
Forward Transfer Admittance (Figure 19)
Y
21
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
-
68 - j0
-
mS
Input Admittance (Figure 20)
Y
11
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
-
0.55 +
j0
-
mS
Output Admittance (Figure 21)
Y
22
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
-
0 +
j0.02
-
mS
Reverse Transfer Admittance (Figure 22)
Y
12
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
-
0.004 -
j0.005
-
S
Noise Figure
NF
f = 100MHz
-
8
-
dB
Electrical Specifications
T
A
= 25
o
C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test Circuits
FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP
FIGURE 2. SINGLE STAGE VOLTAGE GAIN TEST SETUP
FIGURE 3. TWO STAGE VOLTAGE GAIN TEST SETUP
ICUT
11
7
9
6
12
8
SIGNAL
SOURCE
10
F
V
IN
= 0.3V
RMS
0.5k
1k
0.5k
0.1
F
1k
V
OUT
0.1
F
V
CC
= +12V
V
X
V
CC
= +12V
V
EE
= -6V
ICUT
11
7
9
6
12
8
SIGNAL
SOURCE
10
F
V
IN
= 10mV
RMS
1k
1k
0.5k
0.1
F
V
EE
= -6V
V
CC
= +12V
1k
V
OUT
0.1
F
V
X
1k
V
CC
= +12V
ICUT
9
6
13
8
SIGNAL
SOURCE
10
F
V
IN
= 1mV
RMS
1k
1k
V
CC
= +12V
V
OUT
1k
14
12
1k
1k
1
F
3
11
2
7
1
4
1
F
1k
1k
0.5k
0.5k
1k
V
EE
= -6V
0.1
F
V
CC
= +12V
V
X
0.1
F
CA3054
5
Typical Performance Curves
NOTE: For CA3054 use data from 0
o
C to 85
o
C only.
FIGURE 4. COLLECTOR-TO-BASE CUTOFF CURRENT vs
TEMPERATURE FOR EACH TRANSISTOR
FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT
FOR EACH TRANSISTOR
NOTE: For CA3054 use data from 0
o
C to 85
o
C only.
FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH
TRANSISTOR vs TEMPERATURE
NOTE: For CA3054 use data from 0
o
C to 85
o
C only.
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR
DIFFERENTIAL PAIRS
FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT
OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs
EMITTER CURRENT
FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED
DIFFERENTIAL PAIRS vs COLLECTOR CURRENT
10
2
10
-1
10
1
10
-2
10
-3
10
-4
COLLECT
OR CUT
OFF CURRENT (nA)
0
25
50
75
100
125
TEMPERATURE (
o
C) (NOTE)
V
CB
= 15V
V
CB
= 10V
V
CB
= 5V
I
E
= 0
100
10.0
1.0
0.1
1.0
10
COLLECTOR CURRENT (mA)
INPUT BIAS CURRENT (
A)
V
CB
= 3V
T
A
= 25
o
C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
B
ASE-T
O-EMITTER V
O
L
T
A
GE (V)
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (
o
C) (NOTE)
V
CB
= 3V
I
E
= 3mA
I
E
= 1mA
I
E
= 0.5mA
5
4
3
2
0.75
0.50
0.25
0
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (
o
C) (NOTE)
V
CB
= 3V
I
E
= 10mA
I
E
= 1mA
I
E
= 0.1mA
OFFSET V
O
L
T
A
GE (mV)
0.8
0.7
0.6
0.5
0.4
B
ASE-T
O-EMITTER V
O
L
T
A
GE (V)
0.01
0.1
1.0
10
EMITTER CURRENT (mA)
V
CB
= 3V
T
A
= 25
o
C
V
BE
V
IO
= |V
BE1
- V
BE2
|
3
2
1
INPUT OFFSET V
O
L
T
A
GE Q
1
AND Q
2
(mV)
4
0
10
1.0
0.1
0.01
INPUT OFFSET CURRENT (
A)
0.01
0.1
1.0
10
COLLECTOR CURRENT (mA)
V
CB
= 3V
T
A
= 25
o
C
CA3054
6
FIGURE 10. COMMON MODE REJECTION RATIO
CHARACTERISTIC
FIGURE 11. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC
FIGURE 12. TWO STAGE VOLTAGE GAIN CHARACTERISTIC
FIGURE 13. FORWARD CURRENT TRANSFER RATIO (h
FE
),
SHORT CIRCUIT INPUT IMPEDANCE (h
IE
), OPEN
CIRCUIT OUTPUT IMPEDANCE (h
OE
), AND OPEN
CIRCUIT REVERSE VOLTAGE TRANSFER RATIO
(h
RE
) vs COLLECTOR CURRENT FOR EACH
TRANSISTOR
FIGURE 14. GAIN BANDWIDTH PRODUCT (f
T
) vs COLLECTOR
CURRENT
FIGURE 15. FORWARD TRANSFER ADMITTANCE (Y
21
) vs
FREQUENCY
Typical Performance Curves
(Continued)
110
100
90
80
COMMON MODE REJECTION RA
TIO (dB)
0
-1
-2
-3
-4
BIAS VOLTAGE ON TERMINAL 11 (V)
V
CC
= 12V
V
EE
= -6V
f = 1kHz
100
75
50
25
0
-25
-50
SINGLE ST
A
GE V
O
L
T
A
GE GAIN (dB)
0
-1
-2
-3
-4
-5
-6
-7
BIAS VOLTAGE ON TERMINAL 11 (V)
V
CC
= 12V
V
EE
= -6V
f = 1kHz
SIGNAL INPUT = 10mV
RMS
0
-1
-2
-3
-4
-5
-6
BIAS VOLTAGE ON TERMINALS 3 AND 11 (V)
-7
100
75
50
25
0
-25
-50
TW
O ST
A
GE V
O
L
T
A
GE GAIN (dB)
V
CC
= 12V
V
EE
= -6V
f = 1kHz
SIGNAL INPUT = 1mV
RMS
100
10
1.0
0.1
NORMALIZED h P
ARAMETERS
0.01
0.1
1.0
10
COLLECTOR CURRENT (mA)
V
CB
= 3V
f = 1kHz
T
A
= 25
o
C
h
OE
h
FE
h
RE
h
IE
h
FE
= 110
h
IE
= 3.5k
h
RE
= 1.88 x 10
-4
h
OE
= 15.6
S
AT
1mA
h
RE
h
IE
800
700
600
500
400
300
200
100
1000
900
GAIN B
AND
WIDTH PR
ODUCT (MHz)
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14
COLLECTOR CURRENT (mA)
V
CB
= 3V
T
A
= 25
o
C
20
10
0
-10
-20
30
FOR
W
ARD TRANSFER SUSCEPT
ANCE
OR CONDUCT
ANCE (mS)
DIFFERENTIAL CONFIGURATION
V
CB
= 3V
I
C
(EACH TRANSISTOR)
1.25mA
T
A
= 25
o
C
b
21
g
21
0.1
1.0
10
100
FREQUENCY (MHz)
CA3054
7
FIGURE 16. INPUT ADMITTANCE (Y
11
)
FIGURE 17. OUTPUT ADMITTANCE (Y
22
) vs FREQUENCY
FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y
12
) vs
FREQUENCY
FIGURE 19. FORWARD TRANSFER ADMITTANCE (Y
21
) vs
FREQUENCY
FIGURE 20. INPUT ADMITTANCE (Y
11
) vs FREQUENCY
FIGURE 21. OUTPUT ADMITTANCE (Y
22
) vs FREQUENCY
Typical Performance Curves
(Continued)
5
4
3
2
1
0
0.1
1
10
100
FREQUENCY (MHz)
INPUT SUSCEPT
ANCE OR
CONDUCT
ANCE (mS)
DIFFERENTIAL CONFIGURATION
V
CB
= 3V
I
C
(EACH TRANSISTOR)
1.25mA
T
A
= 25
o
C
b
11
g
11
0.1
1
10
100
FREQUENCY (MHz)
b
22
g
22
0.5
0.4
0.3
0.2
0.1
0
OUTPUT CONDUCT
ANCE (mS)
DIFFERENTIAL CONFIGURATION
V
CB
= 3V
I
C
(EACH TRANSISTOR)
1.25mA
T
A
= 25
o
C
OUTPUT SUSCEPT
ANCE (mS)
0
1
2
3
10
1
0.1
0.01
0.001
0.0001
REVERSE TRANSFER CONDUCT
ANCE (mS)
0.1
1
10
100
1000
1000
100
10
1
0.1
0.01
REVERSE TRANSFER SUSCEPT
ANCE (
S)
FREQUENCY (MHz)
-g
12
b
12
g
12
DIFFERENTIAL CONFIGURATION
I
C
(EACH TRANSISTOR)
1.25mA
T
A
= 25
o
C
V
CB
= 3V
80
60
40
20
0
-20
-40
0.1
1
10
100
FOR
W
ARD TRANSFER CONDUCT
ANCE OR
SUSCEPT
ANCE (mS)
CASCODE CONFIGURATION
V
CB
= 3V
I
C
(STAGE)
2.5mA
T
A
= 25
o
C
200
FREQUENCY (MHz)
g
21
b
21
0.1
1
10
100 200
FREQUENCY (MHz)
b
11
6
5
4
3
2
1
0
INPUT CONDUCT
ANCE OR
SUSCEPT
ANCE (mS)
g
11
CASCODE CONFIGURATION
V
CB
= 3V
I
C
(STAGE)
2.5mA
T
A
= 25
o
C
0
-2
-4
-6
-8
-10
-12
OUTPUT CONDUCT
ANCE (mS x 10
-4
)
0.1
10
1
100
FREQUENCY (MHz)
g
22
b
22
2
1
0
OUTPUT SUSCEPT
ANCE (mS)
CASCODE CONFIGURATION
V
CB
= 3V
I
C
(STAGE)
2.5mA
T
A
= 25
o
C
CA3054
8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y
12
) vs FREQUENCY
Typical Performance Curves
(Continued)
100
10
1
0.1
0.01
0.001
0.1
1
10
100 200
FREQUENCY (MHz)
REVERSE TRANSFER CONDUCT
ANCE OR
SUSCEPT
ANCE (
S)
g
12
-b
12
CASCODE CONFIGURATION
V
CB
= 3V
I
C
(STAGE)
2.5mA
T
A
= 25
o
C
CA3054
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