CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
7-56
Semiconductor
CA3194
Single Chip PAL
Luminance/Chroma Processor
Description
The Harris CA3194E is a silicon monolithic integrated circuit
designed to perform all of the signal processing functions for both
the chroma and luminance signals of PAL color television receivers.
This circuit performs all the functions needed between the video
detector and the video RGB output stages. DC contrast, bright-
ness, and saturation controls and average beam limiting functions
are included. The RGB buffer stages are capable of delivering
5mA of current into the video output stages.
NOTE:
Formerly Dev. No. TA10313.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
CA3194E
-40
o
C to +85
o
C
24 Lead PDIP
Features
All PAL Luminance and Chrominance Processing
Circuitry on a Single Chip in a 24-Lead Plastic
Package
Phase-Locked Subcarrier Regeneration Utilizing
Sample-and-Hold
DC Controls for Brightness, Contrast, and Color
Saturation Functions
Input for Average Beam-Current Limiting
Contrast Control Having Excellent Tracking of
Luma and Chroma Channels
Low-lmpedance RGB Outputs with Excellent
Tracking for Direct Coupling to Video Driver
Circuitry
May 1997
Pinout
CA3194
(PDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
GND
CHROMA OUT
SAT. CONTR.
CHROMA INPUT
ACC FILTER
ACC FILTER
APC FILTER
APC FILTER
90
o
INPUT
0
o
INPUT
V
CO
OUTPUT
V
CC
16
17
18
19
20
21
22
23
24
15
14
13
AVER. BEAM
PICTURE CONTROL
LOW PASS
LUMA INPUT
PEAK BEAM
G OUTPUT
V
R-Y
INPUT
V
B-Y
INPUT
SANDCASTLE
BRIGHTNESS
R OUTPUT
B OUTPUT
INFO
CONTROL
LEVEL
FILTER
TERMINAL VOLTAGE AND CURRENT RATINGS
TERMINAL
VOLTAGE (NOTE 1) -V
CURRENT - mA
MIN
MAX
I
IN
I
OUT
1
-
-
-
-
2
0
13
0
30
3
0
8
10
-
4
0
5
-
-
5
0
Note
-
-
6
-
-
0.1
0.5
7
0
Note
-
-
8
0
Note
-
-
9
0
8
-
-
10
0
8
-
0.7
11
0
13
-
10
12
0
13
-
-
13
0
12
-
-
14
0
5
-
1.5
15
0
5
-
1.5
16
0
13
-
10
17
0
13
-
10
18
0
13
-
10
19
0
Note
-
-
20
0
5
-
-
21
0
Note
-
-
22
0
8
-
-
23
0
5
-
-
24
0
12
-
-
NOTE:
1. The maximum should not exceed the V
CC
voltage. Voltage with respect to
Terminal 1 for V
CC
(Terminal 12) of 12V
10%.
File Number
1270.3
NOT RECOMMENDED FOR NEW DESIGNS
7-57
Specifications CA3194
Absolute Maximum Ratings
Operating Conditions
Supply Voltage and Current
Pin 12 Voltage Range . . . . . . . . . . . . . . . . 11V (Min) to 13V (Max)
Pin 12 Current Range . . . . . . . . . . . . . 44mA (Typ) to 60mA (Max)
Power Dissipation
Up to T
A
= +25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW
Above T
A
= +25
o
C. . . . . . . . . . . . . . . . Derate Linearly 8.7mW/
o
C
Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
Operating Temperature Range . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Thermal Package Characteristics (
o
C/W)
JA
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
A
= +25
o
C, V
CC
= 12V, V
S
= 2.85V, V
C
= 2.85V, V
AB
= V
PB
= V
CC
, V
B
adjusted for V
18
= 6.3V, C
X
adjusted
for F
OSC
= 4.43361875MHz, Sandcastle: V
BG
= 8.0V, V
BLANK
= 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit
PARAMETER
TEST CONDITIONS
TYPICAL
VALUE
UNITS
LUMINANCE SECTION
Input Impedance (Terminal 20)
6
k
5
pF
Luminance Channel Input Voltage
Luma Input Signal = 30% Sync.
0.5
V
P-P
Bandwidth of Luminance Channel
Luma Input Signal: 0.5V
P-P
(30% Sync) modulated CW
Adj. modulation frequency for -3dB at color outputs.
8
MHz
Brightness Control Range (Terminal 23)
For Control Characteristics, See Figures 1 and 2.
0 - 3.5
V
DC
Output Black Level
Luma Input Signal: 0.5V
P-P
(30% Sync)
V
B
0V - 5V,Measured at Pin 18 black level.
See Figures 1 and 2.
Range
5.9-9.7
V
DC
Offset
0.6 Max.
V
DC
Contrast Control Range (Terminal 22)
Luminance Input: 0.5V
P-P
(30% Sync), for Control Characteristics.
See Figure 3
0 - 5
V
DC
Luminance Gain Control Range
Luminance Input: 0.5V
P-P
(30% Sync), V
C
= 0.5V - 5V measure
Pin 18 black level to maximum white level. See Figure 4.
32
dB
RGB Output Swing
Luminance Input: 0.5V
P-P
(30% Sync), V
C
= 5V, read black
level to peak white. See Figures 5 and 6.
4
V
P-P
CHROMlNANCE SECTION
Input Impedance (Terminal 4)
See Figures 7 and 8.
4.5
k
5
pF
Chroma Channel Input Voltage
Chroma
220
mV
P-P
Burst
100
mV
P-P
ACC Range
+6 - (-20)
dB
Input Burst Level for Kill (Note 1)
Adjust chroma input Pin 4 until Pin 2
25mV
P-P
.
Measure Burst level at Pin 4.
10
mV
P-P
Contrast Control Chroma/Luma Tracking
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Luminance Input: 0.35V
P-P
, V
S
adjusted for Chroma at
Pin 18 = 2V
P-P
. V
C
is adjusted for luminance at Pin 18 = 2V
P-P
,
V
C
is again adjusted for luminance of +6 and -9dB.
Then read chroma percentage difference. See Figure 9.
5
%
7-58
Specifications CA3194
Saturation Control Range (Terminal 3)
For control characteristic, see Figure 10.
0 - 5
V
DC
Maximum Chroma Output Voltage (Terminal 2)
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust V
C
and V
S
for maximum Pin 2 output.
2.5
V
P-P
OSCILLATOR SECTION
Pull-In Range
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust C
X
for HI/LO f
OSC
without Chroma signal.
Apply signal to lock.
500
Hz
Static Phase Error
2
Deg./
100Hz
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
Chroma Input: Burst =100mV, Chroma = 220mV
P-P
,V
.
Adjust V
C
for V18 = 1V. Read V15. Calculate V18/V15.
10
Ratio
B-Y Demodulator Conversion Gain
Chroma Input: Burst = 100mV
P-P
, U
. Read V16 and V14.
Calculate V16/V14. V
C
remains as for R-Y gain.
18
Ratio
G-Y/B-Y Matrix Ratio
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, U
read V17 and V16, Calculate V17/V16. V
C
remains as above.
0.2
Ratio
G-Y/R-Y Matrix Ratio
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, V
.
Read V17 and V18. Calculate V17/V18. V
C
remains as above.
0.5
Ratio
Sub-Carrier and Harmonic Content at Outputs
No Chroma or Luma Input. Read residual carrier at outputs.
30
mV
P-P
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
2 - 5
V
Burst Gate Pulse
6.5 - V
CC
V
NOTES:
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
Electrical Specifications
T
A
= +25
o
C, V
CC
= 12V, V
S
= 2.85V, V
C
= 2.85V, V
AB
= V
PB
= V
CC
, V
B
adjusted for V
18
= 6.3V, C
X
adjusted
for F
OSC
= 4.43361875MHz, Sandcastle: V
BG
= 8.0V, V
BLANK
= 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued)
PARAMETER
TEST CONDITIONS
TYPICAL
VALUE
UNITS
Circuit Description
(See Block Diagram and Figure 20)
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
cuits are controlled from pins 24 and 19.
7-59
CA3194
Block Diagram
VCO
OUTPUT
0
o
INPUT
SAND
B OUTPUT
G OUTPUT
R OUTPUT
V
CC
GR
OUND
(SUB)
CHR
OMA
INPUT
SA
T
.
CONTR.
4
3
2
14
15
20
22
24
23
21
19
1
12
18
17
16
13
10
11
8
7
5
6
CHR
OMA
OUT
V
B-Y
INPUT
V
R-Y
INPUT
LUMA
INPUT
PICTURE
CONTR
OL
A
VER.
BEAM INFO
.
BRIGHTNESS
CONTR
OL
LO
W P
ASS
FIL
TER
PEAK
BEAM LEVEL
A
CC FIL
TER
APC FIL
TER
A
CC FIL
TER
APC FIL
TER
1ST CHR
OMA
ST
A
GE +
SWITCHING
SYNCHR
ONOUS
DETECT
OR
FOR APC AND A
C
C
SAMPLE
AND
HOLD
2ND CHR
OMA
ST
A
G
E
B
UFFER
ST
A
G
E
B-Y
DEMOD
R-Y
DEMOD
LUMA
AMPLIFIER
KILLER
AMPLIFIER
+PHASE EQ
AC
C
0 DEGRE CARRIER
COMP
ARA
T
O
R
+ LEVEL SHIFT
AMPLIFIER +
P
AL SWITCH
+ PHASE EQ
G - Y
MA
TRIX
A
VERA
GE
BEAM LIMITER
BRIGHTNESS
COMP
ARA
T
O
R
Y MA
TRIX
Y MA
TRIX
Y MA
TRIX
R OUTPUT
G OUTPUT
B OUTPUT
BLANKING
IDENT
FLIP FLOP
PEAK BEAM
LIMIT
COMP
ARA
T
O
R
SANDCASTLE
DECODER
90 DEGREE
CARRIER
90
o
AMPLIFIER
0 DEGREE
AMPLIFIER
SAMPLE
AND
HOLD
SAMPLE
AND
HOLD
CASTLE
BG
BG
BG
FF
FF
BG
BG
BG
BG
FF
BG
BG
BL
BG
90
o
INPUT
9
B
UFFER
7-60
CA3194
Typical Performance Curves
FIGURE 1. BRIGHTNESS CONTROL (V
B
) MEASURED AT PIN
18 OUTPUT TERMINAL
FIGURE 2. CONTRAST CONTROL (V
C
) MEASURED AT 2ND
CHROMA AMPLIFIER OUTPUT TERMINAL
FIGURE 3. CONTRAST CONTROL (V
C
) MEASURED AT PIN 18
OUTPUT TERMINAL
FIGURE 4. LUMA GAIN vs SUPPLY VOLTAGE (V
CC
) MEASURED
AT LUMA AMPLIFIER OUTPUT TERMINAL
FIGURE 5. LINEAR OPERATING RANGE AS A FUNCTION OF
V
CC
MEASURED AT PIN 16 OUTPUT TERMINAL
(BEST OPERATING RANGE IS 11-13V V
CC
)
FIGURE 6. LUMA/CHROMA TRACKING AS A FUNCTION OF V
C
MEASURED AT PIN 18 OUTPUT TERMINAL
V
C
= V
S
= 2.85V
V
CC
= 12V
PIN 20 : 0.5V
P-P
(30% SYNC)
11
10
9
8
7
6
5
4
3
0
PIN 18 - BLA
CK LEVEL (V)
1
2
3
4
5
PIN 23 - BRIGHTNESS CONTROL (V
B
, V)
V
S
= 2.85V
V
CC
= 12V
PIN 4 : BURST = 100mV
P-P
4
3
2
1
0
0
PIN 2 - CHR
OMA OUTPUT (V
P-P
) RED B
A
R
1
2
3
4
5
PIN 22 - COLOR CONTRAST CONTROL (V
C
, V)
CHROMA = 220mV
P-P
4
3
2
1
0
0
PIN 18 - LUMA OUTPUT (V)
1
2
3
4
5
PIN 22 - CONTRAST CONTROL (V
C
, V)
(WHITE T
O
BLA
CK LEVEL)
V
S
= 2.85V
V
CC
= 12V
PIN 20 : 0.5V
P-P
(30% SYNC)
BLACK LEVEL = 7V
24
16
8
0
7
LUMA AMPL GAIN (dB)
PIN 12 - SUPPLY VOLTAGE (V)
V
C
= V
S
= 2.85V
V
18
= 2V
P-P
AT V
CC
= 12V
V
B
SET TO BLACK LEVEL = 7V
4
12
20
28
32
8
9
10
11
12
13
14
15
16
17
18
14
10
6
2
11
BLUE OUTPUT (V
16
MAX, V)
12
13
14
15
16
PIN 12 - SUPPLY VOLTAGE (V)
V
S
= 2.85V
V
B
AND V
C
ADJUSTED FOR MAX
LINEAR V16
PIN 4: BURST = 100mV
P-P
16
CHROMA = 220mV
P-P
TOP CLIPPING
BLACK LEVEL
BOTTOM CLIPPING
12
8
4
20
10
0
-10
-20
0
V
18
- % DIFFERENCE LUMA/CHR
OMA
1
2
3
4
5
PIN 22 - CONTRAST CONTROL (V
C
, V)
CHROMA INPUT: BURST = 100mV
P-P
CHROMA = 220mV
P-P
LUMA INPUT: 0.5V
P-P
(30% SYNC)
ADJUST V
C
FOR V
18
= V
PEAK
LUMA,
THEN ADJUST V
S
FOR V
18
= 2V
PEAK
CHROMA (RED BAR)
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